JPS6161416B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an instruction control method for rationally detecting the timing of issuing a subsequent instruction in a vector processing device when the subsequent vector instruction uses the resultant operand of the preceding vector instruction as an input operand. FIG. 1 shows an overview of a vector processing device, in which VU is a vector processing device, 1 is a main memory, 2 is a main memory control device, 3 is a memory access processing unit, 4 is a vector register, 5 is a Reference numeral denotes an instruction control section, 6 an arithmetic processing section, 7 a load processing section, 8 a store processing section, 9 an adder, and 10 a multiplier, respectively. The main storage control device 2 controls data transfer between the main storage device 1 and the vector processing device VU. Memory access processing unit 3
has a load processing section 7 and a store processing section 8. The load processing section 7 issues a load request and stores vector data sent from the main memory control device 2 in the vector register 4. The store processing unit 8 issues a store request and stores the vector in the vector register 4.
This is to transfer data to the main memory control device 2. Although only one vector register 4 is shown, in reality there are multiple vector registers, and each vector register can store multiple elements. Command control unit 5
controls the memory access processing section 3, vector register 4, and arithmetic processing section 6. The arithmetic processing unit 6 has an adder 9 and a multiplier 10, and the adder 9 and the multiplier 10 have a pipeline structure. The same applies to the load processing section 7 and the store processing section 8. The vector processing unit VU processes a second operand A=a ₀ , a ₁ , ...a _i ...a _o- having a plurality of elements.
₁ and a third operand B with multiple elements
= b ₀ , b ₁ ... b _i ... b _o-1 , and the corresponding elements are operated on, and the first operand of the result C = c ₀ , c ₁ , ... C _i ... c _{o -1} . For example, when performing the calculation C=A+B,
C _i =a _i +b _i . On the other hand, a conventional general-purpose processing device in which the number of elements is limited to one is called a scalar processing device. A vector instruction has an instruction code, a first operand specification section, a second operand specification section, and a third operand specification section. For example, VM1, 2,
3 is a vector multiplication instruction that multiplies the contents of vector register 2 and vector register 3 and stores the result in vector register 1. Also, V.A.
4, 5, 1 is a vector addition instruction that adds the contents of vector register 5 and vector register 1 and stores the result in vector register 4. When processing vector instructions, in order to perform the processing at high speed, the load processing unit 7, store processing unit 8, adder 9, multiplier 10, etc. are arranged in a pipeline structure, and the processing is performed before the arithmetic processing of the preceding element is completed. It is designed to insert subsequent elements.
Figure 2 shows the vector addition process,
Vector addition processing consists of reading data (READ), comparing the exponents of both operands (COMPARE), and shifting to match the exponents (PRE−).
SHIFT) Addition Shift for normalization after operation (POST−
SHIFT) Data writing (WRITE) is a 6-step pipeline process. Instruction processing is represented by a parallelogram as shown in FIG. However, conventional vector processing devices have the disadvantage that they cannot perform arithmetic processing efficiently. For example, when there is a vector instruction sequence VM1,2,3 VA4.5,1, the result data of the vector instruction is used as the input data of the vector instruction. Therefore, the command must be issued after the result of the vector command is obtained. Now, in the conventional scalar processing device, processing was performed for each instruction. In a scalar instruction with one element, when executing the multiplication and addition instructions M1, 2, 3 A4, 5, 1, the third
As shown in the figure, the instruction after the instruction is completed is executed. In FIG. 3, IF represents an instruction fetch, D represents an instruction decode, A represents an address calculation, OF represents an operand fetch, and E represents each phase of execution. FIG. 4 shows command processing when a vector processing device is controlled in the same way as a scalar processing device. In FIG. 4, IF represents an instruction fetch, D represents an instruction decode, Q represents a waiting phase, and E represents an instruction execution phase. As shown in Fig. 4, in the conventional method, the vector instruction is executed after the vector instruction in I can't. The present invention is based on the above considerations, and includes:
It is an object of the present invention to provide an instruction control method that makes it possible to efficiently use the resources of a vector processing device and to process vector instruction sequences at high speed. Therefore, the command control method of the present invention is
Multiple vector registers, multiple arithmetic processing units that process vector data specified by vector instructions, multiple executing instruction management units that have an executing instruction register that holds instruction information of the vector instruction that is being executed, and arithmetic operations. A waiting register that holds instruction information before execution, if the arithmetic processing unit corresponding to the instruction information in the above waiting register is not free, or if there is no free executing instruction management, the instruction held in the above waiting register is In a vector processing device having a command transmission control circuit configured not to transmit a command, each of the executing command management units sets the write flag to a predetermined value after a time period determined by the type of the command has elapsed from the start of command execution. A write flag generating means is provided, and a register interference check circuit corresponding to each of the plurality of executing instruction management units is provided in the instruction transmission control circuit, and each of the register interference check circuits is configured to:
The instruction information in the above waiting register is compared with the instruction information held in the executing instruction register of the corresponding executing instruction management section, and the first operand register number of the instruction in the executing instruction register is compared with the instruction information in the waiting register. If the second operand register numbers of the instructions are equal, or if the first operand register number in the executing instruction register and the third operand register number in the waiting register are equal, the corresponding executing instruction management This is characterized in that the command transmission wait signal is held at a value indicating the command transmission wait state until the write flag of the section reaches a predetermined value. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 5 is a block diagram of one embodiment of the instruction control device of the present invention, FIG. 6 is a block diagram of one embodiment of the register interference check circuit in the instruction transmission control circuit, and FIG. 7 is a block diagram of one embodiment of the instruction processing according to the present invention. It is a figure explaining timing. In FIG. 5, 11 is an instruction fetch register, 12 is a decoder, 13 is a waiting register, 1
4 is an instruction transmission control circuit, 15-1 and 15-2 are executing instruction management units, 16-1 and 16-2 are executing instruction registers, 17-1 and 17-2 are counting circuits, 1
8-1 and 18-2 are write flags, 19 and 20
is a matching circuit, 21 and 22 are AND circuits, and 23 is a matching circuit.
A NAND circuit and 24 indicate an OR circuit, respectively. In FIG. 5, the fetched vector instruction is set in instruction fetch register 11.
The vector instruction in the instruction register 11 is sent to the decoder 12.
decoded by The decoded instruction information is set in the waiting register 13. The instruction transmission control circuit 14 reads information from the waiting register 13 and the executing instruction management units 15-1 and 15-2, and if the instruction can be issued, selects the arithmetic processing unit to which the instruction is to be issued and the vacant executing instruction. It associates it with the management section and sends startup information to the arithmetic processing section, and also sends instruction information in the queue register 13 to the associated executing instruction management section. The executing instruction management unit 15-1 stores the executing instruction register 16.
-1, counting circuit 17-1 and write flag 1
8-1. Executing instruction register 16-
1 is set with instruction information of the instruction being executed by the corresponding arithmetic processing unit. Counting circuit 17-1
starts time counting when instruction information is set in the executing instruction register 16, and when the time determined by the instruction information is counted, the write flag 18-1 is set.
Set. Assuming that the number of stages of the arithmetic processing unit that executes addition is 10 and the number of pipeline stages of the arithmetic processing unit that executes division is 20, an addition instruction will be executed 10 cycles after the start of instruction execution, and a division instruction will be executed 20 cycles after the start of instruction execution. After the cycle, write flag 18-1 is set. That is, the write flag is set to "1" when the first result element is written to the vector register after performing arithmetic processing by pipeline processing from the start of instruction execution. The executing command management unit 15-2 also has a similar configuration. The command transmission control circuit 14 determines whether (a) the arithmetic processing unit to which the command is to be transmitted is vacant; (b) Is the executing command management section vacant? (c) Is there any register interference? (d) Is the light flag raised? etc. and start executing the command. If the arithmetic processing unit to which the command is to be issued is not vacant or if there is no vacant executing command management unit, the command transmission control circuit 14 does not transmit the command. In addition, even if the arithmetic processing unit to which the instruction is to be issued is vacant and there is a vacant executing instruction management unit, if there is register interference,
The command is not issued immediately, but after the write flag goes up. FIG. 6 shows one embodiment of a register interference check circuit existing in the instruction generation control circuit 14. In addition, in Figure 6, E1WRITE
FLAG is the write flag 18-1, the E1 instruction first operand register number is stored in the executing instruction register 16-1, and the Q instruction second operand register number and Q instruction third operand register number is included in the queue register 13. In FIG. 6, the E1 instruction first operand register number and the Q instruction second operand register number do not match, and the E1 instruction first operand register number does not match the E1 instruction first operand register number.
If the register number and the third operand register number of the Q instruction do not match, the command transmission wait signal becomes logic "0", and if other conditions are met, the command is transmitted. If the E1 instruction first operand register number and the Q instruction second operand register number match, or if the E1 instruction first
If the operand register number and the Q instruction third operand register number match,
When E1WRITE FLAG becomes "1", the command transmission wait signal is turned off and command transmission becomes possible. Note that the register interference check circuit as shown in FIG.
There is actually another set for E2. FIG. 7 shows an example of vector instruction processing according to the present invention. Figure 7 shows the case of processing a vector instruction sequence VM1, 2, 3 VA4, 5, 1, and this vector multiplication instruction VM goes through six steps from reading the i-th element to writing the i-th result element. It is considered necessary. Vector instruction being executed instruction register 16-1
When set to , the counting circuit 17-1 starts counting time, and the counted value reaches a predetermined value (“6” in this case).
, the write flag 18-1 becomes logic “1”.
becomes. When the write flag 18-1 becomes "1", the vector instruction set in the waiting register 13 is set in the execution register 16-2 by the instruction transmission control circuit 14, and execution of the vector instruction is started. . As is clear from the above description, according to the present invention, resources of a vector processing device can be used efficiently,
Vector instruction sequences can be processed at high speed.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an overview of a vector processing device, Fig. 2 is a diagram explaining vector addition processing, Fig. 3 is a diagram showing processing timing of an instruction sequence in a scalar processing device, and Fig. 4 is a diagram showing conventional vector instructions. 5 is a block diagram of an embodiment of the instruction control device of the present invention, FIG. 6 is a block diagram of an embodiment of the register interference check circuit in the instruction transmission control circuit, and FIG. 7 is a diagram showing the timing of processing. is vector instruction processing 1
It is a figure which shows an example. VU...Vector processing unit, 1...Main memory, 2...Main memory control unit, 3...Memory access processing unit, 4...Vector register, 5...
Instruction control unit, 6... Arithmetic processing unit, 7... Load processing unit, 8... Store processing unit, 9... Adder, 10
... Multiplier, 11 ... Instruction fetch register,
12...Decoder, 13...Waiting register, 1
4... Command generation control circuit, 15-1 and 15-2...
...Executing instruction management unit, 16-1 and 16-2...Executing instruction register, 17-1 and 17-2...Counting circuit, 18-1 and 18-2...Write flag,
19 and 20...matching circuit, 21 and 22...AND
Circuit, 23...NAND circuit, 24...OR circuit.

Claims (1)

[Claims] 1. A plurality of vector registers, a plurality of arithmetic processing units that process vector data specified by a vector instruction, and a plurality of executing instruction management units that have an executing instruction register that holds instruction information of the vector instruction that is being executed; A waiting register that holds instruction information before execution of an operation; if the arithmetic processing unit corresponding to the instruction information in the waiting register is not free, or if there is no empty executing instruction management unit, the waiting register holds the instruction information. In a vector processing device having an instruction generation control circuit configured not to issue instructions, a write flag is set in each of the executing instruction management sections after a time period determined by the type of instruction has elapsed from the start of instruction execution. In addition to providing a write flag generating means for setting a predetermined value, the instruction transmission control circuit is provided with a register interference check circuit corresponding to each of the plurality of executing instruction management units, and each of the register interference check circuits is connected to the queue register. The instruction information held in the executing instruction register of the corresponding executing instruction management unit is compared, and the first operand register number of the instruction in the executing instruction register and the instruction in the waiting register are determined. If the second operand register numbers are equal, or if the first operand register number in the executing instruction register and the third operand register number in the waiting register are equal, write the corresponding executing instruction management section. - An instruction control method characterized in that a command transmission wait signal is held at a value indicating waiting for command transmission until the flag reaches a predetermined value.