JPS61289440A - Digital signal processor - Google Patents

Abstract

PURPOSE:To execute a complex signal processing efficiently by the small number of instructions by supplying a compared output obtained from a comparator to a microprocessor to control respectively memories. CONSTITUTION:A comparator 17 compares an output M from a multiplexer 14 with an added output N from an adder 18, and when M<N, inputs the compared output '1' to an exclusive OR (EXOR) circuit 28. The output of the EXOR circuit 28 is supplied to the switching control terminals of multiplexers 12, 19 and a latch circuit 29. The output of the EXOR circuit 28 is '1' when a flag F2 is '0' and M<N is formed, i.e. when the added output exceeds the value of an end address EA at the time of increment, and when the flat F2 is '1' and the compared output is '0', i.e. when the added output is less than the value of a start address SA at the time of decrement (M>N).

Description

[Detailed description of the invention] Hereinafter, the present invention will be explained in the following order.

A. Industrial field of application B0 Overview of the invention C9 Prior art 0 Problem to be solved by the invention E0 Ninth means for solving the problem F0 Effect G, Example G-1 Configuration G-2 Operation H0 Effects of the Invention A, Industrial Application Field The present invention relates to a digital signal processing device that digitally processes audio signals, etc. in real time, and more specifically, it sequentially multiplies different coefficients while repeatedly reading out the same cell in a large-capacity memory. The present invention relates to a digital signal processing device that can perform various operations with high processing efficiency.

B0 Summary of the Invention The present invention compares a pointer whose address value changes sequentially with a boundary address in a digital signal processing device that sequentially changes the address value of a pointer, accesses all large-capacity memory in sequential mode, and performs all signal processing. By supplying the comparison output of the comparison circuit to all microprocessors, the microprocessor can tell when the pointer has reached the boundary address, and can perform all data processing such as repeatedly reading the same cell and multiplying all the coefficients sequentially. This allows for high processing efficiency.

C0 Conventional technology for digital conversion of audio signals, video signals, etc.
Several digital signal processing devices have been proposed that perform all delay processing and multiplication processing with coefficients in real time. Examples of the above-mentioned digital signal processing device include JP-A-58-132844 and JP-A-58-13.
No. 7179, JP-A-58-137180, JP-A-58
Examples include those described in Japanese Patent Application Laid-open No. 144259 and Japanese Patent Application Laid-open No. 144272/1983.

In the digital signal processing device disclosed in the above-mentioned publication, a large-capacity memory is connected to a data bus and is divided into a plurality of memory blocks (cells). I remember it. This large-capacity memory is controlled by an MCU (memory control unit), and when a memory cell number is specified from the microprocessor to the MCU, the addresses of the specified cells are automatically set sequentially (sequentially). The A7j digital signal is sequentially read out from the cells of the large capacity memory t1 and is incremented by 1 using this method. Multiplication processing is performed.

By the way, when sequentially writing or reading signals to or from the above cell, all addresses in the cell will automatically return to the start address once they reach the end address (boundary address) of the cell, forming one infinite loop. I come to do it. At this time, the microprocessor has no knowledge that the address has returned to the start address, but this does not pose a problem if all signal delay processing is performed.

However, for example, there may be cases where it is desired to partially sample the original sound, attenuate it at the same attenuation rate C (0.8n in the example) as the entire original sound, and then perform envelope processing and the like. In this case, all digital signals (audio signals in this example) are stored so as to fit in one cell, and this signal is sequentially and repeatedly multiplied by the same number of other coefficient data (attenuation rate data).

At this time, the coefficient data is stored in a separate cell of the same size as the cell in which the digital signal is stored. Then, the digital signal and coefficient data are simultaneously read out from each cell and multiplication processing is performed.

When performing such processing, an inconvenient sound will occur if the microprocessor does not know that the address has returned to the start address.

Therefore, in the past, a separate counter corresponding to the number of words from the start address to the end address of one cell was provided, and all outputs of this counter were returned to the microprocessor.

D0 Problems to be Solved by the Invention As described above, in conventional digital signal processing devices, an operation is performed in which the audio signals, etc. stored in the cells of a large-capacity memory are repeatedly read out, and other coefficient data is completely lost. In such a case, it is necessary to provide separate cells for storing all the coefficient data or separate cells for each counter sound. Therefore, it is necessary to allocate all extra cells in the large-capacity memory, and the addition of the counter increases the hardware configuration. Further, the number of instructions in the microprogram of the microprocessor increases, such as the need to read the counter output while monitoring it on the microprocessor side, resulting in a problem that processing efficiency decreases.

Therefore, the present invention has been proposed to solve these conventional problems.It is a data processing method in which the same cell is read repeatedly and multiplied by different coefficients sequentially.
In order to do this, it is not necessary to store all the coefficient data in large-capacity memory, which saves memory capacity, eliminates the need for a counter corresponding to the number of words in a cell, and reduces the number of instructions for the microprocessor sensor. The object of the present invention is to provide a digital signal processing device that can perform highly efficient processing.

Efficient Means for Solving the E0 Problem In order to achieve all of the above objects, the digital signal processing device of the present invention includes a digital signal storage memory in which digital signals are stored, and a pointer for accessing all of this memory. a pointer memory for storing the digital signal, a start address memory for storing the start address of the digital signal storage memory, and an end address memory for storing the end address of the digital signal storage memory;
An adder circuit adds all of the adder data to the pointer from the pointer memory, stores the adder data, supplies the adder data to the adder port, and sets a flag to completely prohibit or permit addition in the adder circuit. an adder data memory for storing; a comparator circuit that compares the addition result from the adder circuit with the end address from the end address memory; a selection circuit which selects one of the start addresses from the start address memory and supplies all the selected outputs to the pointer memory; It is characterized by being supplied to a microprocessor.

Therefore, in the present invention, the addition output of the adder circuit that adds all the adder data to the pointer and the comparison output of the comparison circuit that completely compares the end address of the boundary address are supplied to the microprocessor. It is possible to know when the pointer, which changes sequentially, returns to the start address of the boundary address. This method allows complex signal processing to be performed efficiently with a small number of instructions.

G. Embodiments Hereinafter, embodiments of the present invention will be described in detail based on all the drawings.

G-1, Ne1. - FIG. 1 is a block circuit diagram of a digital signal processing device according to an embodiment of the present invention. In this digital signal processing device, digitally converted A7j audio signals, video signals, etc. are subjected to signal processing. In this digital signal processing device, each -1 = all addresses in the large capacity memory 1 are formed in the memory control unit 2 (hereinafter referred to as MCU 2), and these addresses can be sequentially decremented in a sequential mode. In addition, by keeping all the offsets for sequential address formation intermittently, the MCU 2 can form all the serial addresses in sequential mode.Furthermore, the cell address can be changed from the end address to the start address (or start address). One pin of the flag that is set when returning from the address to the end address is supplied to the microprocessor 3 side.

In Figure 1, the mounting density? In order to increase the capacity, the large capacity memory 1 consisting of dynamic RAM λ is connected to the data path DBK.
For example, each word is accessed by a 6-bit memory address formed in MeO2. The large-capacity memory 1 has a capacity for storing, for example, 64 words of a digital signal such as an audio signal of 1 word and 24 pints. The large capacity memory 1 is divided into, for example, 64 memory blocks (cells) (these cells may overlap each other depending on the purpose), and the start address of each cell is divided into 64 memory blocks (cells). SA and end address EA are the boundary addresses of each cell, and the address being accessed for each cell is the pointer (current address).
It is P.

Here, the difference between the start address SA, which is the access start address of the cell, and the end address EA, which is the access end address of the cell, is the number of words of the cell. The start address SA, end address EA, and pointer P are stored in each memory in MeO2, which will be described later, and are executed by the n1 microprocessor 3.
By specifying the cell number to the memory, a pointer P for accessing the word of each cell is sequentially made of MeO2 and supplied to the large capacity memory 1.

Mayu, MicroProcera, an Advanced Fist Digital O Signal Processor (ADSP)? 3 is connected to a data bus DBK. This processor 3 is composed of a logical operation unit (ALU), a multiplier, an instruction memory, a coefficient memory, a data memory, etc. η1. Here, instructions and coefficient data are written from the host computer 4 into the instruction memory and coefficient memory. This microprocessor? 3/a, the cell number mentioned above is specified for MeO2 and the MCU 1 is controlled, and the multiplication process between the digital signal read out from the large capacity memory 1 and the coefficient data stored in the coefficient memory is performed. . The above MicroProcera? A read control signal RD output from 3,
The write control signal WT, input control signal Ex IN , and output control signal 170UT are connected to the large capacity memory 1 and Me.
It is supplied to the control circuit 5 in O2. Further, the read control signal RD and the write control signal WT are supplied to the multiplexer 6 in the MCUz. The control circuit 5 fully controls the random mode, and the control output of the control circuit 50 is supplied to the switching control terminals of the multiplexers t6 and t7.

Here, random mode will be briefly explained. When the random mode is selected by the above-mentioned control signal outputted from the microprocessor 3 and random reading or writing is performed to the large-capacity memory 1, the microprocessor 3
The addresses supplied to the launch circuit 8 in the MCUZ are selected by the multiplexer t7 and supplied to the large capacity memory 1. As a result, a word in the large capacity memory 1 is arbitrarily accessed using the address created by the microprocessor 3, and random reading or writing is performed.

Next, the above MCU:1 will be explained. MeO2 stores the start address 5At of each cell of the large capacity memory 1 - memory 9, and end address EAi to store / memory 10.
, and a memory 11 for storing all the pointers P is provided. The memories 9, to, and tt of this group have, for example, 64 memory areas corresponding to the number of cells,
A 6-bit address signal (
Cell number designation signal) is a memo! J9,10. By sending the data to If, the cell number is specified, and the start address SA, end address EA1, and pointer P corresponding to that cell are output. SA, E when initializing or changing
Writing to each memory 9, 10, 11 of A and P is performed by the host computer 4. Here, the writing of pointer P is a maltegrek? 12'.

The start address SA of the memory 9701 is input to the multiplexer 13.14, and the end address EA of the memory 9701 is input to the multiplexer 13.14. The multiplexer 13゜140 switching control terminal has a flag output from the adder data memory 15.
A 1-bit signal (Ft) in the figure is supplied. This flag (2) is a flag for selecting either auto increment or auto decrement in sequential mode. When incrementing, the flag ■ is 101,
At this time, the B side input is selected in the multiplexers 13 and 14, and the start address SA,
End address EA is output from multiplexer 14. At the time of decrement, the flag ■ is l 1 f, and the input on the A side is selected. 13
The start address SA is output from the end address EA1 multiplexer 1470h. Multiplexer 1
The output of 3 is input to the adder circuit 16, which is the multiplexer 1.
The output of 4 is input to the comparison circuit 17.

Nine, the pointer P from the memory 11 is the adder circuit 1.
8 and Maltegrek? 7. In this adder circuit 18, the pointer P and the adder data from the adder data memory 15 are added, and the n1 addition output is sent to the comparator circuit 17.
and supplied to multiplexer 19.

Here, the adder data memory 15 is constituted by the number of cells, for example, 64 words, and stores adder data corresponding to each cell. The writing of the adder data into the memory 15 is performed from the host computer or the main controller. When a cell number designation signal is supplied from the microcomputer 3, the adder data corresponding to the cell is output. One word of the memory 15 is composed of, for example, 9 bits, and the breakdown of these 9 bits is 1 bit of the flag ■ (F1 in the figure), 1 bit of the flag ■
There are 7 bits of offset data (Os in the figure). This 7 lag ■ determines whether auto increment and auto decrement are completely prohibited or permitted (enabled) in sequential mode, and the 7 lag ■
When it is w, it is prohibited, and when it is 1110, it is allowed. As described above, the flag ■ is auto-incremented by log, and when it is "1" it is auto-decremented. The amount of offset during auto-increment or auto-decrement is determined by the 7-bit offset data, and since it is composed of 7 bits, the +
127, -128' when decrementing! Offcents are possible. However, when incrementing, O is treated as +1. This ofceno)? By setting, the memory addresses to be accessed in the large capacity memory 1 are sequentially formed intermittently by the offset.

The 1-bit signal of the seven lag ■ and the flag ■ is as follows.
The output of this AND circuit 20 is the upper 9 bits of the adder data [8. ~)
] is supplied to the adder circuit 18. Also, AND circuit 2
A 1-bit signal of 7 lags is input to one input terminal of 1, 22, 23, 24, 25, 26, 27, and 1-bit of offset data (7 bits) is input to the other input terminal. The outputs of the AND circuits 21 to 27 are supplied to the adder circuit 18 as the lower 7 bits (D6 to 0 in the figure) of the adder data.

Then, in the adder circuit 18, the 16 bits of the pointer P from the memory 2 (CXS~ in the figure) and the adder data (Dss
-o) is added and output. Here, 7 lag ■ (F
! ] is l. When increment and decrement are prohibited at OI, the outputs of AND circuits 20 to 27 are 1.
01, and adder data CD15~. ) becomes IO1, so the pointer P does not change. Maku,
Flag ■ (Fl) is l ll and 7,7g ■ (F2) is l
When OI is incremented, the output of the AND circuit 20 is 101, and the n lower adder data (Da~.) determined by the 7 bits of the offset data (OB) is incremented (added) to the pointer P as an offset. ), and the pointer P advances.Furthermore, the flag ■(F,) is set to 111.
When the 7 lag ■ (F2) is decremented by 11, the output of the AND circuit 20 becomes 111, and the top 9 of the adder data
All bits (D3.~.) become 111.

If you want to decrement (subtract) 1t from the pointer P by setting the offset amount to -1, use the offset data (0
8) All 7 bits of gold are set to wll, and the lower 7 bits of adder data, CD, ~o)k are all set to III. At this time, the 16-bit 1-dar data (Dls~o) becomes FFFF in hexadecimal, and the pointer P (Cxs~0) is set to FFFF.
By adding FF, l is decremented from pointer P. Also, if you want to set the total offset amount to -2, just set the adder data (Dl, ~o) as FFFE in hexadecimal notation.

Further, in the comparison circuit 17, the output from the multiplexer 14 (M in the figure) and the addition output from the adder circuit 18 (N in the figure) are compared. It is input to the sibu-or (EXOR) circuit 28.
A bit signal is input, and the output of the EXOR circuit 28 is supplied to the switching control terminal of the multiplexer 12.19 and the launch circuit 29.

Here, the output of the EXOR circuit is 111 because F
When 2 is °0'' and M(N, that is, when incrementing, the above addition output exceeds the value of end address EA, and when Ft is 111 and the above comparison output is 101, that is, when decrementing, the addition output is Start address SA
(when CM>N).

The 1-bit output of the latch circuit 29 is input to a 1-bit port of the microprocessor 3.

Further, in the comparison circuit 17, the output of the multiplexer 14 is subtracted from the addition output from the addition circuit 18, and this subtraction output (NM) is supplied to the addition circuit 16. This subtraction output is the end address E when the above-mentioned addition output is incremented when the above-mentioned offset amount is 2 or 12 or more.
This is the t value exceeding A't, and is the value obtained by decrementing the start address SA at the time of decrement, and becomes negative at the time of decrement.

In the adder circuit 16, the subtracted output from the comparator circuit 17 is added to the output from the multiplexer 13, and the output ratio value is returned to the start address SA after the end address EA is incremented. When decrementing, the start address SA is subtracted from the end address EA by a ratio value. The addition output of this addition circuit 16 is input to the multiplexer 19.

In the multiplexer 19, the addition circuit 1817t selects and outputs one of the 16 addition outputs based on the main power of the EXORXOR circuit. Is the output of the multiplexer 19 a multiplexer? 12, on the other hand, is supplied to the memory 11 where the pointer P is stored.

This process prevents the pointer P from being rewritten. That is, in the auto-increment mode, when the output of the t addition circuit 18 adds the full offset to the pointer P and exceeds the end address E/l at 9 o'clock, the pointer P reaches the start address S.
Return to side A. , in the mode of macro autodecrement,
At 9 o'clock, the output of the adder circuit 18 obtained by subtracting the offset from the pointer P becomes smaller than the start address SA.
The pointer P returns to the end address EA side.

The cell number is specified by the microcomputer 3,
The pointer P read from the memory 11 is supplied to the mass memory 1 through a multiplexer 7 which is switched so that the output from the memory 11 is selected in the sequential mode.

As a result, the words of that cell of the mass memory 1 are sequentially accessed by the pointer P which is auto-incremented or auto-decremented.

Here, read control signal π) and write control signal WT
The active low write signal is sent to the write terminal 1:W of the memory 11.15 from the multiplexer 6 to which
By supplying the data to T), the pointer P is updated and the adder data is changed. Note that in the random mode, the input side of the multiplexer 6 111 is selected by being switched by the control output of the control circuit 5, and the input side of the multiplexer 6 is supplied to the write terminal (WTE), so changing the contents of the memories 12 and 15 is prohibited. Ru.

G-2 Operation Next, what is the operation of the above-mentioned digital signal processing device having such a configuration? In the auto-increment operation in the 〇mass, sequential mode, as described above, the 7 lag ■ is set to 11'' and the flag ■ is set to 10'.At this time, if the offset amount is set to +1, the microprocessor ?3 by MeO2
As the cell number is specified for each cell, the pointer P of the specified cell is sequentially incremented by one. Furthermore, the pointer P that has reached the end address EA is
Automatically returns to start address SA. This pointer P then accesses the word of that cell in the mass memory 1, and the above-mentioned control signals RD and WT are applied.

Based on ExIN and ExOUT, when writing digital signals, reading is performed sequentially for the cells.

The moving direction of the pointer P at this time is in the direction of the end address in the direction of the arrow X, as shown in FIG. 2 with one cell CLt- taken out. Such an auto-increment operation can be used for delay processing of digital signals by delaying the read operation compared to the write operation. At this time, if the flag t101 is set and the adder data Io is added by the adder circuit 18, each time each memory 9, 10, 11, 15 is accessed from the microgroceno t3, The auto-increment operation for the write pointer P or the read pointer P can be temporarily stopped, and the entire delay time can be changed by the number of stops.

In addition, in the auto-decrement operation, if the flag ■ is set to 111, the 7 lag ■ is set to 11', and the off sector amount is -1, the pointer P of the cell specified by the microprocessor 3 is sequentially decremented by 1. I'm going to go. Then, upon reaching the start address SA, the nine pointer P automatically returns to the end address EA. The moving direction of the pointer P at this time is the Y direction on the start address SA side in FIG.

By providing such an auto-decrement function, data replacement such as the above-mentioned first-in-last-out or last-in-first-out becomes possible in sequential mode.

Is it possible to normalize signal waveforms, etc. with fewer instructions and higher processing efficiency? Be able to do it. In the microprocessor 3, the nz flaw signal is read out from the large capacity memory 1 and subjected to multiplication processing to efficiently perform normalization, thereby preventing signal loss and noise incorporation.

Note that when auto-decrementing the pointer P, instead of providing the multiplex registers 213 and 11, the end address EA is stored in the memory 9 only during the decrement operation.
In addition, in the digital signal processing device described above, the 7-bit offset data Os is stored in the adder data memory 15.
By setting all values appropriately, the pointer P' can be successively advanced to pointer P' with an appropriate offset during auto-increment or auto-decrement operation.

Next, proportionality will be explained by applying this offset function to a total oversampling filter. FIG. 3AK shows sample data E-11. First, cell n of large capacity memory 1
In cell n1, interpolation data axk is sequentially written from start address SA of 00 (hexadecimal) to sample data E to 11 with an offset amount of +2.
Starting from the start address 8A of f (hexadecimal number), the offset amount +2 is sequentially written. Then, in cell n2, by sequentially reading out both data ob (hexadecimal number) from the start address SA by offset amount + l (auto increment state), the data is multiplexed as shown in FIG. 3B and t data are obtained. be able to.

In this way, for example, set the offset amount to +2 and create two cells n. +nl pointer P (effective address) difference is set to 1, cell n. Input temple data into , interpolation data into another cell n1, and input temple data into another cell n1.
By configuring the address of 2 in a range that includes both cell n(1+nl), it is possible to efficiently and easily convert the data arrangement in the sequential mode without using the random mode.

Furthermore, in the above digital signal processing device, when the pointer P reaches the end address EA and returns to the start address SA during auto-increment, and when the pointer P reaches the start address SA and returns to the end address EA during decrement, the latch A 1-bit signal is supplied from the circuit 29 to the 1-bit input port of the microprocessor f3. Therefore, microproceno? Immediately after accessing memories 9, 10, 11, and 15 in step 3,
By checking all of these 1 pinto signals, the pointer P returns to the start address SA when incrementing, and the pointer P returns to the end address E when decrementing.
You can know everything about going back to A. Note that the latch circuit 29 is reset at the next access of the microprocessor 3.

By using such a function, it is possible to easily carry out an operation (envelope processing, etc.) in which the same cell is repeatedly read out and sequentially multiplied by another coefficient.

Next, an example of this operation will be explained. FIG. 4A shows data (original signal) dα that fits exactly between the start address SA and end address EA of one cell. Now data d from this cell. are read out sequentially n
, the A7e coefficient stored in the coefficient memory is multiplied by + (for example, =0.8) in the microprocessor 30 multiplier.

In the microprocessor 3, while checking all the above l-bit signals, this coefficient is multiplied by all end addresses EA.
Continue until you reach . The new data d obtained by the multiplication is sequentially written into the cells again. When the data d is sequentially read out from the cell, the multiplier of the microprocessor 30 sequentially multiplies another coefficient by 2 (for example, 2=0.8") to create new data d2. Also, After multiplying by a different coefficient (for example, =0.8'), new data d is created.As shown in Figure 4B, the envelope processing (indicated by S in the figure) of the original signal d0 is performed. I'm sorry.

In addition, the above 1-bit signal? Latch circuit 2 to store
Instead of using 9 cells, it is also possible to have a memory area of 1 pint in the number of cells (64 cells in this example) all around the memory. In this case, microproceno? From 3, address signal for specifying all cell numbers (cell number specification signal)
We need to supply that memory.

As described in detail of the H1 invention, in the digital signal processing device of the present invention, the comparison output of the comparison circuit that compares the addition output of the addition circuit that adds all the adder data to the pointer and the boundary address is supplied to all microprocessors. , a microprocessor can tell when a pointer has reached a boundary address.

Therefore, when performing data processing in a fully sequential mode, in which the same cell is read out repeatedly and multiplied by different coefficients sequentially, compared to the conventional method, large capacity memory is saved and the number of words in n1 cells is reduced. A corresponding counter is also not required. The number of instructions for the microprocessor is reduced, such as not having to monitor the counter output, and the microprocessor is able to perform its own processing, increasing processing efficiency. However, the above comparison output is simply fed back to the microprocessor, and no circuit modification is required.

It is also compatible with conventional MCUs and microprocessors that are capable of sequential access and random access.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a digital signal processing device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the movement of a pointer within a cell of a large-capacity memory, and FIG. 3 is a block circuit diagram of a digital signal processing device according to an embodiment of the present invention. FIG. 4 is a waveform diagram illustrating an example of use in array conversion processing of gold digital data, and FIG. 4 is a waveform diagram illustrating proportionality when the above-mentioned digital clock processing device is utilized in gold and other digital data processing. 1... Large capacity memory 2... Memory control unit (MCU) 3.
・・Microprocessor ◆Fist・e Host computer 9.10.11 --・Memory 12.13, 14, 19・・Red multiplex length 150・
Adder data memory 16.18...O addition circuit 170/comparison circuit 20-27-...AND circuit 28...φ EXOR circuit 29...latch circuit

Claims (1)

[Claims] A digital signal storage memory in which a digital signal is stored, a pointer memory in which a pointer for accessing this memory is stored, and a start address memory in which a start address of the digital signal storage memory is stored. a memory, an end address memory in which the end address of the digital signal storage memory is stored, an adder circuit that adds adder data to the pointer from the pointer memory; an adder data memory that supplies the data to the adder circuit and stores a flag for prohibiting or permitting addition in the adder circuit; and a comparison circuit that compares the addition result from the adder circuit with the end address from the end address memory. and a selection circuit that selects either the addition result from the addition circuit or the start address from the start address memory in accordance with the comparison output from the comparison circuit and supplies this selected output to the pointer memory. , A digital signal processing device characterized in that a comparison output from the comparison circuit is supplied to a microprocessor that controls each of the memories.