JPS61245264A - Control storage device patrol access method - Google Patents

Abstract

PURPOSE:To patrol simultaneously a control storage during executing a job by reading the instruction of a patrol system, specifying alternately a state and a control storage patrol state and detecting a CS error. CONSTITUTION:A micro instruction CS 12 is accessed through an OR circuit 11 from the instruction buffer 10 of a job program. By a CS read state, CS data is read out and transmitted to an execution instruction processing circuit 13, and then the state of each phase of a pipe line is sequentially executed. The data read out of the CS 12 is branched, entered to an ECC check/correct circuit 14 to check an error. If the error is present, its address is stored in an error CS address register 15, and the CS 12 is accessed through the OR circuit 11. Simultaneously the data concerned from the ECC check/correct circuit 14 is inverted, corrected and written in the CS 12. A CS patrol circuit 16 patrols the CS 12 by the patrol CS read state.

Description

[Detailed Description of the Invention] [Summary] The present invention incorporates a control storage device (hereinafter abbreviated as O8) such as control storage (aS), and stores one word in multiple words.
The command reading state from the normal O8 and the OS patrol reading state of the present invention are alternately specified, and the battlerol program is accessed for one word by the C8 patrol circuit in the OS patrol reading state. Then, each read word is checked by 100 circuits,
If there is an error, correct it and rewrite the CS data.
This method restarts the patrol, and has the advantage that the CS patrol can be performed while the command is being executed.

[Industrial application field]

The present invention relates to a CS patrol access method in a pipeline type information processing device incorporating a control storage device such as a control storage (OS).

[Conventional technology]

Conventionally, in a pipeline type information processing unit (OPU) with a built-in control storage (aS), as will be described later in the embodiment, instruction decoding, operand access, and calculation are performed on one word list of a job program.

It is divided into multiple phases such as checking and storing calculation results, and each of the 7 aes is further divided into 2 to 3 states, and the information stored in the control storage (aS) is read out in the first state of one word. , sequentially move to the next state. In this case, the job program data check is performed in the pipeline, but the O8 itself is not checked for read errors during program execution;
When the PU is held off, that is, when the operation is stopped or in a standby state, a CS patrol is performed according to the patrol program, and if there is an error, it is corrected by the ECC circuit.

However, with this method, one OPU hole-off results in 1 of O8.
It just checks the words.

[Problem that the invention seeks to solve]

In the conventional CS patrol method described above, the OPU processes the job program and the CS patrol in series, which takes time and reduces the processing efficiency of the J OPU.

By performing CS patrol in parallel while the job is being executed, this time can be shortened and the OP
The burden on U can be reduced.

The object of the present invention is to provide a pipelined O8 with a built-in O8.
An object of the present invention is to provide a CS patrol access method that allows a PU to perform CS patrol in parallel while a job is being executed.

[Means for solving problems]

In order to achieve the above object, in the present invention, a CS patrol state is specified alternately with a patrol-type command read state, and in the CS patrol state, a single word is accessed by a hatroll circuit, and this is checked by an EOO circuit, and an error is detected. If such error occurs, the correction site OS patrol is interrupted, the data is rewritten to O8, and the CS patrol is restarted.

[For production]

As shown in the above configuration, in pipelined instruction execution, one word of 7 aes is further divided into 2 to 6 states,
A CS read is performed in the first state of one word, but since the 08 read is performed at a high speed compared to the progress of the pipeline, the next state becomes an empty time.

Therefore, a CS patrol is set up in that free time state.
If there is an error, it is corrected by the B00 circuit and rewritten using the period of the CS patrol state, and the CS patrol is restarted. This allows CS patrol to be performed in parallel while the job program is being executed.
This improves the utilization efficiency of U.

〔Example〕

FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the embodiment corresponding to states of the pipeline system.

The information processing device (MPU in this case) of the present invention incorporates an aS and performs pipeline control. That is, as shown in FIG. 2(α), a job program is divided into, for example, four phases of instruction decoding, operand access, operation, and operation result, and each phase is divided into two or three states. Instruction decode is address decode state D of control data of O8.

Register read stay) H, operand access is performed in operand address calculation state A, and buffer stay 1'B1+B2 extracts and stores the operand at that address.
The operation is divided into operation state El + E, and the operation result is divided into check state OK and write state W.

For these stays) D-W, the CS read state for reading the control code from O8 is as shown in the same figure (b), 99 people, B2. . . , and the patrol 08 read state of the present invention is alternately assigned as RI Bl + El . . . as shown in FIG. In this way, CS lead and patrol C
By alternately reading the S leads, the utilization efficiency of p MI'U can be effectively increased.

FIG. 1 shows a configuration for realizing the above-mentioned control. In the figure, from the instruction buffer 10 of the job program
Microinstruction C812 is accessed via R circuit 11. Then, the OS data is read in the CS read state shown in FIG. 2 (α), and the state of each phase of the send/write line is sequentially executed by the execution command processing circuit 13. The data read out from C8 is branched and input into the EOO check/collect circuit 14 to perform an error check.
If there is an error), record this address in the CS address register (FO8AR) 15, access the aS via the OR circuit 11, invert the corresponding data from the FiOO check/collect circuit 14, and send it to O812. Write the correction.

On the other hand, in order to patrol O8 in the patrol CS read state shown in FIG. 2(b) of the present invention, an aS patrol circuit 16 is provided in the above configuration.

This patrol program is read out and sent to the patrol CS address register (P (3SAR) 17, and then incremented (
+1) Step by step in the circuit 18 and access 0812 t- for one word via the OR circuit 11. Send the data of B to the E00 check/collect circuit 14, and if there is an error, send the address to F'08AR15, and send this content to the OR circuit 11.
Access 0812 via. On the other hand, the corrected data from the E00 check/collect circuit 14 is sent to O8 and rewritten.

This situation is shown in FIG. 2(d). In the state of patrol 08IJ-do in FIG.
The i00 check/collect circuit 14 checks. If an O8 error occurs here, this data is inverted and the collected data is sent to O812 and rewritten.
do. During this time, reading of O812 is interrupted, and after rewriting, a retry is performed in a predetermined patrol CS read state.

In Figure 2 (g), the patrol CS in Figure 2 (c)
The period between the read and the CS rewrite period in the same figure (FIG.) is divided into two,
They are represented by an OS patrol cycle (R+A) and an OS rewrite cycle (B (+B2)).

Of these, the OS rewrite cycle (Bs+Bz) is O8
It is started when the patrol circuit is disconnected and the OS patrol state is met. After rewriting to the aS for a predetermined period of time, the CS controller is restarted and an attempt is made to execute the instruction.

〔Effect of the invention〕

As explained above, the aS patrol in the pipeline system of the present invention is performed in the previously vacant state alternately with the instruction y = de during instruction execution, and when a C8 error is detected, the 08 corrected data is rewritten. By simply interrupting the OS patrol during the 08IJ write cycle, the command execution can be executed in parallel without affecting the execution of the command. This makes it possible to perform OS patrol quickly, correct errors in job execution commands before they occur, and reduce the rate of occurrence of errors. Furthermore, it is highly effective in efficiently performing OPU processing and reducing overhead.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of an embodiment of the present invention. In the figure, 10 is an instruction buffer, 11 is an OR circuit, and 12 is a microinstruction control storage. (03), 13 is an execution instruction processing circuit, 14 is an ECC check/collect circuit, 15 is an error OS address register, 16 is an OS patrol circuit, 17 is a patrol CS address register, and 18 is a step circuit. Fig. 1 is an explanatory diagram of the configuration of an embodiment of the present invention. Fig. 2 is an explanatory diagram of the operation of an embodiment of the present invention.

Claims (1)

[Claims] Built-in control storage device (OS) that stores control data,
In a pipeline type information processing apparatus that divides a job execution instruction into multiple states for one word, reads a corresponding instruction in the first state of one word, sends it to an instruction execution processing circuit, and executes the instructions sequentially, the control storage device The patrol state for checking the reading of the code is specified alternately with the instruction reading state, and in the patrol state, the patrol circuit accesses the patrol program for one word, and the read word is checked by the ECC circuit to check for errors. A patrol access method for a control storage device is characterized in that the patrol is corrected, the patrol is interrupted, the data is rewritten to the control storage device, and the patrol is restarted.