JPS61182036U - - Google Patents
Info
- Publication number
- JPS61182036U JPS61182036U JP6635685U JP6635685U JPS61182036U JP S61182036 U JPS61182036 U JP S61182036U JP 6635685 U JP6635685 U JP 6635685U JP 6635685 U JP6635685 U JP 6635685U JP S61182036 U JPS61182036 U JP S61182036U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead frame
- view
- sectional
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の一実施例の断面図、第２図は
第１図の実施例を基板に実装した場合の断面図、
第３図は本考案の製造工程の説明図であつて、第
３図イはリードフレームの平面図、第３図ロは第
３図イの線Ａ―Ａに沿つた断面図、第３図ハは半
導体チツプを固定した場合の断面図、第３図ニは
ワイヤボンデイングと樹脂封止をした場合の断面
図、第４図及び第５図はそれぞれ従来例の断面図
、第６図は第４図の半導体装置を基板に実装した
場合の断面図である。
１……半導体チツプ、５……樹脂。
Fig. 1 is a sectional view of an embodiment of the present invention, Fig. 2 is a sectional view of the embodiment of Fig. 1 mounted on a board,
FIG. 3 is an explanatory diagram of the manufacturing process of the present invention, in which FIG. 3A is a plan view of the lead frame, FIG. C is a sectional view when the semiconductor chip is fixed, FIG. 3 D is a sectional view when wire bonding and resin sealing are performed, FIGS. 4 and 5 are sectional views of the conventional example, and FIG. 6 is a sectional view of the conventional example. 5 is a cross-sectional view of the semiconductor device of FIG. 4 mounted on a substrate. FIG. 1...Semiconductor chip, 5...Resin.
Claims (1)
素子とリードフレームをボンデイングするための
ワイヤとを樹脂により前記半導体素子の基板側が
露出するように封止した半導体装置。 A semiconductor device in which a semiconductor element, a lead frame, and a wire for bonding the semiconductor element and the lead frame are sealed with resin so that a substrate side of the semiconductor element is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6635685U JPS61182036U (en) | 1985-05-02 | 1985-05-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6635685U JPS61182036U (en) | 1985-05-02 | 1985-05-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61182036U true JPS61182036U (en) | 1986-11-13 |
Family
ID=30599185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6635685U Pending JPS61182036U (en) | 1985-05-02 | 1985-05-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61182036U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02158159A (en) * | 1988-12-12 | 1990-06-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit device and its manufacturing method |
| JP2003068958A (en) * | 2001-08-28 | 2003-03-07 | Dainippon Printing Co Ltd | Discrete package and method of manufacturing the same |
-
1985
- 1985-05-02 JP JP6635685U patent/JPS61182036U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02158159A (en) * | 1988-12-12 | 1990-06-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit device and its manufacturing method |
| JP2003068958A (en) * | 2001-08-28 | 2003-03-07 | Dainippon Printing Co Ltd | Discrete package and method of manufacturing the same |