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JPS61124094U - - Google Patents

Info

Publication number
JPS61124094U
JPS61124094U JP885585U JP885585U JPS61124094U JP S61124094 U JPS61124094 U JP S61124094U JP 885585 U JP885585 U JP 885585U JP 885585 U JP885585 U JP 885585U JP S61124094 U JPS61124094 U JP S61124094U
Authority
JP
Japan
Prior art keywords
transistor
semi
diode
fixed resistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP885585U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP885585U priority Critical patent/JPS61124094U/ja
Publication of JPS61124094U publication Critical patent/JPS61124094U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Picture Signal Circuits (AREA)
  • Color Television Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案にかかる映像増幅回路の一実
施例を示す回路図、第2図は従来の映像増幅回路
を示す回路図である。 20a…入力端子、21a…ゲート回路、22
a…抵抗、23a…半固定抵抗器、25a,27
a…トランジスタ、29a…カソード、30a…
ダイオード、31a…電源端子、33…直流可変
電源、35…陰極線管。
FIG. 1 is a circuit diagram showing an embodiment of the video amplification circuit according to this invention, and FIG. 2 is a circuit diagram showing a conventional video amplification circuit. 20a...input terminal, 21a...gate circuit, 22
a...Resistor, 23a...Semi-fixed resistor, 25a, 27
a...Transistor, 29a...Cathode, 30a...
Diode, 31a...Power terminal, 33...DC variable power supply, 35...Cathode ray tube.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 映像信号が入力されるゲート回路と、このゲー
ト回路の出力端と電源との間に直列に接続された
抵抗および半固定抵抗器と、これらの抵抗および
半固定抵抗器の接続点に一方の電極が接続された
ダイオードと、このダイオードの他方の電極に接
続された直流可変電源と、上記半固定抵抗器の中
点にベース回路が接続された第1のトランジスタ
と、この第1のトランジスタと直列に接続された
第2のトランジスタとを備え、上記第2のトラン
ジスタの出力を陰極線管のカソードに与えるよう
にしたことを特徴とする映像増幅回路。
A gate circuit into which the video signal is input, a resistor and a semi-fixed resistor connected in series between the output end of this gate circuit and the power supply, and one electrode connected to the connection point of these resistors and the semi-fixed resistor. a diode connected to the diode, a DC variable power supply connected to the other electrode of the diode, a first transistor having a base circuit connected to the midpoint of the semi-fixed resistor, and a transistor connected in series with the first transistor. a second transistor connected to the circuit, and an output of the second transistor is applied to a cathode of a cathode ray tube.
JP885585U 1985-01-23 1985-01-23 Pending JPS61124094U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP885585U JPS61124094U (en) 1985-01-23 1985-01-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP885585U JPS61124094U (en) 1985-01-23 1985-01-23

Publications (1)

Publication Number Publication Date
JPS61124094U true JPS61124094U (en) 1986-08-05

Family

ID=30488525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP885585U Pending JPS61124094U (en) 1985-01-23 1985-01-23

Country Status (1)

Country Link
JP (1) JPS61124094U (en)

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