JPS61102047U - - Google Patents
Info
- Publication number
- JPS61102047U JPS61102047U JP18715484U JP18715484U JPS61102047U JP S61102047 U JPS61102047 U JP S61102047U JP 18715484 U JP18715484 U JP 18715484U JP 18715484 U JP18715484 U JP 18715484U JP S61102047 U JPS61102047 U JP S61102047U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- fixed
- light
- wiring connection
- external wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000009977 dual effect Effects 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims 1
Description
第１図は、本考案の半導体封止パツケージの実
施例の各部品を組立状態に配列した斜視図、第２
図は第１図の組立後の斜視図、第３図ないし第６
図は従来の半導体封止パツケージを示し、第３図
及び第５図はそれぞれ斜視図、第４図、第６図は
それぞれ第３図、第５図の底面図である。
１……固定ブロツク、４……外部配線接続リー
ド端子、７……半導体、８……基板付リードフレ
ーム、９……上部デユアルインラインパツケージ
、１１……下部デユアルインラインパツケージ、
１２……基板。
FIG. 1 is a perspective view of an embodiment of the semiconductor encapsulation package of the present invention in which each component is arranged in an assembled state;
The figures are a perspective view of Figure 1 after assembly, and Figures 3 to 6.
The figures show a conventional semiconductor encapsulation package, with FIGS. 3 and 5 being perspective views, respectively, and FIGS. 4 and 6 being bottom views of FIGS. 3 and 5, respectively. 1... Fixed block, 4... External wiring connection lead terminal, 7... Semiconductor, 8... Lead frame with board, 9... Upper dual in-line package, 11... Lower dual in-line package,
12...Substrate.
Claims (1)
を有する固定ブロツクに固定され半導体を封止内
蔵し外部配線接続リード端子が取り出されてなる
ものにおいて、上記半導体を接続し上記固定ブロ
ツクに対しリード端子を介し接続されると共に一
体に固定され上記外部配線接続リード端子を有す
る基板付リードフレームが、上下部デユアルイン
ラインパツケージ間に密封挟着し構成されている
ことを特徴とする半導体封止パツケージ。 In a device that is fixed to a fixed block having an optical connector portion equipped with light-emitting and light-receiving semiconductors, has a semiconductor sealed therein, and has an external wiring connection lead terminal taken out, the semiconductor is connected to the fixed block through the lead terminal. 1. A semiconductor encapsulation package characterized in that a lead frame with a substrate, which is connected and integrally fixed and has the external wiring connection lead terminals, is hermetically sandwiched between an upper and a lower dual in-line package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18715484U JPS61102047U (en) | 1984-12-10 | 1984-12-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18715484U JPS61102047U (en) | 1984-12-10 | 1984-12-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61102047U true JPS61102047U (en) | 1986-06-28 |
Family
ID=30744619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18715484U Pending JPS61102047U (en) | 1984-12-10 | 1984-12-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61102047U (en) |
-
1984
- 1984-12-10 JP JP18715484U patent/JPS61102047U/ja active Pending
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