JPS61101073A - Nonvolatile random access semiconductor memory - Google Patents

Abstract

PURPOSE:To enable to easily perform a storage and readback of information by a nonvolatile random access semiconductor memory by a method wherein the semiconductor memory is constituted of bistable circuits consisting of CMOS transistors, an insulated gate field-effect transistor and so forth. CONSTITUTION:VDD1 and VDD2 are both set at 5V (Vcc) in the read-out and wire-in state periods (t1) of the RAM and the usual read-out and write-in by the RAM are performed. When an IGFET38 is turned-OFF in low, and the IGFET38 and a nonvolatile memory element 37 are disconnected and a signal conductor R for data regeneration is electrically cut off from the RAM. At this time, this RAM is actuated as an ordinary RAM consisting of 6 elements, CMOSs. In a storage period (t2) of information to the nonvolatile memory element 37 from the RAM, the VDD1 and the VDD2 are both made to translate to 20V from the 5V and that state is held during a certain period of time. When the respective output points 3A and 3B of the RAM are respectively high and low in the readout state period (t1), in the storage period (t2) of information, the output point 3A is made to translate to 20V from 5V and the output point 3B is made to hold at 0V. The control gate of the nonvolatile memory element 37 at this time is set at 20V, the drain is set at 0V, a 'write-in' by the nonvolatile memory element 37 is performed and the storage of information is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile random access semiconductor memory, and in particular to a nonvolatile random access semiconductor memory that is capable of retaining data for a long period of time and is used as a data rewritable storage element for a computer. Related to access semiconductor memory.

[Conventional technology]

Conventionally, various configurations of this type of semiconductor memory have been announced, but all of them require a large number of elements to configure the semiconductor memory. The process of reading the information stored in the non-volatile memory element into the random access memory and the process of returning it back are complicated and have drawbacks such as difficulty in use.

[Problem that the invention seeks to solve]

The present invention has been proposed in view of the above-mentioned problems of the prior art, and has a small number of elements and is capable of storing information from a random access memory to a non-volatile memory element and accessing information stored in a non-volatile memory element by random access. It is an object of the present invention to provide a non-volatile random access semiconductor memory that can be read back into the memory in a short time without requiring a complicated process.

[Means for solving problems]

A nonvolatile random access semiconductor memory according to the present invention includes a bistable circuit constituted by complementary insulated gate field effect transistors, and first and second voltage supply means connected to respective power supply terminals of the bistable circuit. a pair of address selection insulated gate field effect transistors each having a source connected to the output of the bistable circuit and a gate connected to a word line; and a pair of address selection insulated gate field effect transistors each connected to a drain thereof. The drain is connected to one of the pair of outputs of the bistable circuit, and the control gate is connected to the other output, and the electric field between the drain and the control gate is A non-volatile memory element whose threshold voltage and voltage can be changed by controlling the input and output of charges into and out of a charge storage region formed in an insulating film under a control gate according to the direction of The insulated gate field effect transistor is connected to the source of the storage element, has a gate connected to a data reproduction signal line, and has a J drain connected to a third voltage supply means.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a cross-sectional view of a nonvolatile memory element used in an embodiment of the present invention, in which 1 is a semiconductor substrate, 2 is an N-type drain region, and 8 is an N-type source region. 5 is silicon oxide film 4
A floating gate for charge storage is provided inside, and 6 is a control gate. Reference numeral 7 denotes a silicon oxide film formed particularly thinly in a portion where the drain region 2 and the floating gate 5 overlap.

FIG. 2 is a diagram showing the characteristics of the nonvolatile memory element shown in FIG. 1, where the horizontal axis shows the potential VCG of the control gate, and the vertical axis shows a constant voltage applied to the drain with the source of the nonvolatile memory element grounded. It shows the current flowing between the drain and source when . In FIG. 1, when the control gate 6 is grounded and a high voltage is applied to the drain 2, a strong electric field is generated in the thin oxide film portion 7 from the drain 2 to the floating gate 5, and holes flow toward the floating gate 5. Injected. As a result, an inversion layer is easily formed on the surface of the silicon substrate 1, and as shown by the curve 21 in FIG. 2, a current flows even when the control gate potential VCG is negative, that is, the threshold voltage takes a negative value. This will be referred to as erasure, for example. On the other hand, a state opposite to erasing, that is, writing can be realized by applying a high voltage to the cositroll gate 6 and grounding the drain 2. That is, by adopting the above-mentioned potential relationship, a strong electric field is generated in the thin oxide film portion 7 from the floating gate 5 toward the drain 2, and electrons are injected into the floating gate, resulting in a state in which the surface of the silicon substrate l is difficult to invert. Therefore, the threshold voltage becomes a positive high value as shown by the curve 22 in FIG. When reading the information stored in the nonvolatile memory element, as shown in FIG. 182, a positive voltage VR lower than the threshold voltage after 1 loading is applied to the control gate. If the nonvolatile memory element is in an erased state, it is conductive and can obtain an IR current, and if it is in a written state, it is non-conductive. The above-mentioned nonvolatile memory element is, for example, an Electronic
s magazine February 28, 1980 issue 11B-11? EE on page
There are examples of application to FROM (electrically erasable programmable read-only memory), which are well known.

FIG. 8 is a circuit diagram of a nonvolatile random access semiconductor memory according to an embodiment of the present invention. A bistable circuit composed of phase-sleeved insulated gate field effect transistors (0MO8) is an inverter consisting of a P-channel IGFET 81 and an N-channel IGFET 821, a P-channel IGFET 8 B, and an N-channel IGFET.
The input terminal and output terminal of each inverter consisting of 84 are cross-connected, and each power supply terminal of the inverter is connected to a first and second voltage supply means VDDI.
, VDDZ is provided. 85 and 86 are a pair of address selection IGFETs, whose sources are respectively connected to a pair of output points 8A and 8B of the bistable circuit, whose gates are connected to a word line W, and whose drains are connected to a pair of digit lines D. There is. 87 is the nonvolatile memory element shown in FIG. 1, and its drain is connected to the output point 8B of the bistable circuit, and its control gate is connected to the output point 8A.

Reference numeral 88 has a source connected to the source of the nonvolatile memory element 87, a gate connected to the data reproduction signal line R, and a drain connected to the eighth voltage supply means VCC.

Next, the operation of the example circuit will be explained. FIG. 4 shows a voltage supply source Vcc for explaining the operation of the embodiment circuit of FIG.
This is a timing chart of VDDI and VDDZ, and t
I is the read/write state period of the random access memory, t2 is the storage period of information from the random access memory to the nonvolatile storage element, t3 is the cutoff period of the voltage supply means,
t indicates a period during which information stored in the nonvolatile storage element is read back to the random access memory.

First, random access memory continues to be generated and the state period is 1. Then, both VDDI and VDDZ are 5 V (Vcc
(same as the power supply voltage) and performs normal random access memory reading and writing. This upper data reproduction signal line R is -LOW'' and IGFET 88 is 'Off.
f', and is electrically separated from the nonvolatile memory element 87 from the random access memory, and at this time operates as a normal 6-element CMO 8 random access memory. Since this operation is well known, the explanation here will be omitted.

Next, during the storage period t of information from the random access memory to the nonvolatile storage element, VDDI, VDD21
both shift from 6V to high voltage zOv and maintain that state for a certain period of time. When a high voltage is applied to VDDI and VDDZ, data is sent to the non-volatile storage element 87 corresponding to each piece of information in the random access memory.
Write 1 or erase 1.

For example, during the read state period t1, each of the output points 8A, 8B of the random access memory becomes "High".
", "Low@, the storage period t of information from the random access memory to the non-volatile storage element.

Then, the voltages at the respective output points 8A and 8B shift as follows. Output point 8A shifts from 5v to 20v, and output point 8B maintains Ov. Nonvolatile memory element 87 at this time
Considering the state of , the control gate is set to 20V, the drain is set to Ov, and one write to the nonvolatile memory element 87 is performed.

In this way, when the respective output points 8A and 8B of the random access memory are "High" and "Low", respectively, one write to the non-volatile memory element 87 is performed during the period t, and information storage is executed. be done.

Next, during the successive state period t, the respective output points 8A and 8B of the random access memory become -Low""Hi.
gh'', during the storage period 1t''lc of information from the random access memory to the nonvolatile storage element 87, the voltages at the respective output points 8A and 8B transition as follows. Output A8A holds Ov and 8B transitions from 5V to 20V. Considering the state of the nonvolatile memory element 87 at this time, the Ov drain of the control gate is set to 20V, and lightning erasure of the nonvolatile memory element 87 is performed. That is, each output point 8A of the random access memory
, 8B are "Low" and "High", respectively, 1 erasure 1 of the nonvolatile element 87 occurs in the period t8.
is performed and the information is stored. In this way, one write or one erase of the nonvolatile memory element is performed corresponding to each piece of information in the random access memory, and the information is stored. After the information is stored in the nonvolatile memory element, the voltage Even if the voltage supply means is lowered or cut off, information is stored and retained in the nonvolatile memory element.This state period is referred to as the cutoff period t of the voltage supply means.

Next, consider the period t during which information stored in the nonvolatile storage element is read back to the random access memory. f) VDr) 1, VDD2 is the rise of VDD21 for the rise of VDDI from Ov to 5V.
Set to delay. This makes it possible to read information stored in the nonvolatile storage element back into the random access memory. Third voltage supply means VCC at this time
and the data reproduction signal R are VDDI, VDI)2
(It is set to rise from Ov to 5V.)

First, consider the case where the non-volatile memory element is in the write state. Vcc and the data reproduction signal R rise from Ov to 5V, and the IGFKT 88 turns I on 1, but since the nonvolatile memory element 87 is in the write state, the nonvolatile memory element is in the "off-state". In this state, VDD
When I rises from Ov to 5V, and then VDD21 rises from Ov to 5V with a delay of time td, each output point 8A8B of the random access memory becomes "H".
high (5V)” and “Low (OV)”. At this time, Vl') DI and VDD2 are set to O with the same rise time.
When raised from V to 5V, non-volatile memory element 8? but"
In the case of “off”, output points 8A and BB are respectively “H”
It is uncertain whether it will be "High" or "Low".Therefore, the rise times of VDD I and VDD21 are intentionally different.

Next, consider the case where the nonvolatile memory element is in the warning erase 1 state. VCC and data reproduction signal R from Ov to 5
When V rises, IGFIET 88 turns "on". At this time, the nonvolatile memory element 87 is in the erased state, so the nonvolatile memory element 8? is in the "on-" state, and the output point 8B is charged via the nonvolatile memory element B7 and the IGFET 88. Next, when VDD 1 and VDD2 are turned on with a delay time td, the output points 8A and 8B become -Low. ”,”
The random access memory enters the operating state by reading back the "High" information. In this way, information is returned to the random access memory in response to each state (writing, erasing) of the nonvolatile memory element. By making the voltage supply means VDD1 and VDD9 independent of each inverter that constitutes a bistable circuit, and raising VDD21 from 0v to 5v with a delay of iD from VDDI at the time of return, a non-volatile This makes it possible to easily read back the information in the random access memory into the random access memory.

Note that since VnD 2 can be generated on the same substrate more easily than Vcc, a single power supply may be used.

〔Effect of the invention〕

As described above, according to the present invention, the number of components of a nonvolatile random access semiconductor memory can be reduced, and the operation of storing and reading back information is easy, and the CMO8 configuration reduces power consumption. can do.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a nonvolatile memory element used in an embodiment of the present invention, FIG. 2 is a diagram showing characteristics of the nonvolatile memory element of FIG. 1, and FIG. 8 is a cross-sectional view of a nonvolatile memory element used in an embodiment of the present invention. FIG. 4 is a circuit diagram of a non-volatile random access semiconductor memory. FIG. 4 is a timing chart for explaining the operation of the embodiment circuit of FIG. ■...Silicon substrate, 2...Drain. 8... Source, 4... Silicon oxide film. 5・・・・・・・・・Floating gate. 6・・・・・・・・・Control gate. ?・・・・・・・・・Thin oxide film. 81.88...P channel IGFET. 82,. 84.8ri, 86.88...N-channel IGFET. 87...Nonvolatile memory element.

Claims (1)

[Claims] A bistable circuit constituted by complementary insulated gate field effect transistors, first and second voltage supply means connected to respective power supply terminals of the bistable circuit, and respective sources thereof. connected to the output of the bistable circuit;
a pair of address selection insulated gate field effect transistors whose gates are connected to word lines; a pair of digit lines connected to respective drains of the address selection insulated gate field effect transistors; and a drain connected to the bistable circuit. A control gate is connected to one of the pair of outputs, and a control gate is connected to the other output of the bistable circuit, and the insulating film below the control gate is a non-volatile memory element whose threshold voltage can be changed by controlling the input and output of charge into a charge storage region formed therein; a source connected to the source of the non-volatile memory element, and a gate used for data reproduction. and an insulated gate field effect transistor connected to the signal line and having its drain connected to a third voltage supply means.
Access semiconductor memory.