JPS60541A - Isolation circuit of single device - Google Patents
Isolation circuit of single deviceInfo
- Publication number
- JPS60541A JPS60541A JP58106804A JP10680483A JPS60541A JP S60541 A JPS60541 A JP S60541A JP 58106804 A JP58106804 A JP 58106804A JP 10680483 A JP10680483 A JP 10680483A JP S60541 A JPS60541 A JP S60541A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- becomes
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は一重化装置と二重化装置とがシステムパスを介
して接続された二重化構成において一重化装置をシステ
ムパスから切シ離すためのアイソレーション回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an isolation circuit for separating a singlexing device from a system path in a duplexing configuration in which a singlexing device and a duplexing device are connected via a system path.
従来、二重化装置と一重化装置とがシステムパスを介し
て接続される二重化構成のシステムにおいては、−ｉ他
装置に対するアイソレーション機能が装備されておらず
、−重化装置に障害が発生した場合等には、システムパ
スがスタックしてシステム障害になるという欠点があっ
た。Conventionally, in a system with a duplex configuration in which a duplex device and a duplex device are connected via a system path, an isolation function for other devices is not provided, and if a failure occurs in the duplex device, etc. had the drawback that the system path could become stuck, resulting in a system failure.
本発明の目的は上記従来の欠点を解決した一重化装置の
アイソレーション回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an isolation circuit for a multiplexing device that solves the above-mentioned conventional drawbacks.
本発明の他の目的は構成が簡単な一重化装置のアイソレ
ーション回路を提供することにある。Another object of the present invention is to provide an isolation circuit for a multiplexing device that has a simple configuration.
本発明によれば、−重化装置側に、中央処理装置からの
オンライン状態を表わすＡＣＴ情報とアイソレーション
状態を表わすＩＳＬ情報を受けて制御信号を発する第１
のダート回路と、前記制御信号によシ前記−重化装置の
出力信号を制御する第２のダート回路とを有する一重化
装置のアイソレーション回路が得られる。According to the present invention, - the multiplexing device receives the ACT information representing the online state and the ISL information representing the isolation state from the central processing unit and issues a control signal;
An isolation circuit for a multiplexing device is obtained, which has a dart circuit and a second dart circuit that controls the output signal of the multiplexing device in accordance with the control signal.
以下図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.
図は本発明の一実施例の構成を示した回路図である。図
において、１は一重化装置、２は二重化装置、３は第１
のダート回路、４は第２のダート回路、５はシステムバ
スインタフェース回路を示している。これらシステムは
、２台の中央処理装置（図示せず）によって制御されて
いる。このシステムの一方を＃０系、他方を＃１系とす
る。以下図面を参照して本発明の詳細な説明する。The figure is a circuit diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is a single device, 2 is a duplex device, and 3 is a first
4 is a second dart circuit, and 5 is a system bus interface circuit. These systems are controlled by two central processing units (not shown). One of these systems is called #0 system, and the other is called #1 system. The present invention will be described in detail below with reference to the drawings.
先ず、二重化装置２の＃０系２−０がオンライン状態に
あると仮定する。そのとき＃０系中央処理装置からの制
御によｆｉ ＡＣＴ −０信号が有効（負信号）、＃１
系中央処理装置からの制御によりＡＣＴ −１信号が無
効（正信号）となっている。First, it is assumed that the #0 system 2-0 of the duplexing device 2 is in an online state. At that time, under the control from the #0 system central processing unit, the fi ACT -0 signal is valid (negative signal), #1
The ACT-1 signal is disabled (positive signal) under control from the system central processing unit.
讃−０信号を受ける第１のダート回路３の受信ダート回
路３Ａ−０は、負信号を出力し、その負信号を受ける接
続ケ゛−ト回路３Ｂは、負信号を出力している。接続ダ
ート回路３Ｂから出力される負信号及び譜−０信号によ
り、第２のダート回路３の出力ダート回路３−０は、出
力可の状態となる。そのため−重化装置１は、システム
バスインタフェース回路３−〇を介してシステムパスＳ
ＢＯと接続され、＃０系に組み込まれている。The reception dirt circuit 3A-0 of the first dirt circuit 3 which receives the SR-0 signal outputs a negative signal, and the connection gate circuit 3B which receives the negative signal outputs a negative signal. The output dart circuit 3-0 of the second dart circuit 3 becomes in an output enabled state due to the negative signal and the score-0 signal output from the connection dart circuit 3B. Therefore, the multiplexing device 1 connects the system path S via the system bus interface circuit 3-0.
Connected to BO and incorporated into #0 system.
この状態において、−重化装置１を系から切シ離しを行
ないたい場合、霞チー〇信号を送出している＃０系中央
処理装置からの制御により、慝−〇信号が有効（負信号
）となる。受信ゲート回路３Ａ−０の入力がどちらも負
信号となり、受信ダート回路３Ａ−０の出力は正信号と
なる。この正信号は、接続ダート回路３Ｂを介して、第
２のケ８−ト回路４に送出される。そのため、それまで
出力可の状態であった出力グート回路４−０は、出力不
可の状態となる。このとき、＃１系中央処理装置からの
制御によシで一１信号は無効（正信号）であるので、出
力ダート回路４−１も、出力不可の状態となっている。In this state, if you want to disconnect the overlaying device 1 from the system, the 〇-〇 signal is valid (negative signal) under the control of the #0 system central processing unit that is sending out the Kasumi Chi〇 signal. becomes. Both inputs of the reception gate circuit 3A-0 become negative signals, and the output of the reception gate circuit 3A-0 becomes a positive signal. This positive signal is sent to the second gate circuit 4 via the connecting dart circuit 3B. Therefore, the output gate circuit 4-0, which had been in an output-enabled state until then, becomes an output-disabled state. At this time, under the control from the #1 system central processing unit, the 11 signal is invalid (positive signal), so the output dart circuit 4-1 is also in a state where it cannot output.
したがって、−重化装置１はシステムパス５ＢＯ２ＳＢ
Ｉから切り離される。Therefore, - the weighting device 1 is the system path 5BO2SB
Separated from I.
以上の説明では、二重化装置２の＃０系２−０がオンラ
イン状態の場合について述べたが、＃１系２−１がオン
ライン状態の場合にも同様に動作するのはいうまでもな
い。In the above description, the case where the #0 system 2-0 of the duplexing device 2 is in the online state is described, but it goes without saying that the same operation occurs when the #1 system 2-1 is in the online state.
なお図に示されているＩＳＬ ＫＥＹは２手動作によシ
強制的に一重化装置１を切シ離したい場合に使用される
。The ISL KEY shown in the figure is used when it is desired to forcibly disconnect the duplexing device 1 by a two-handed operation.
以上述べたように２本発明によれば、簡単な構成で一重
化装置を系から切シ離すことができるという効果がある
。As described above, the present invention has the advantage that the unifying device can be separated from the system with a simple configuration.
図は本発明の一実施例の構成を示した回路図である。
記号の説明＝１は一重化装置、２は二重化装置。
３．４はケゞ−ト回路、５はシステムバスインタフェー
ス回路、 ＳＢＯ、ＳＢＩはシステムパスをそれぞれあ
られしている。The figure is a circuit diagram showing the configuration of an embodiment of the present invention. Explanation of symbols = 1 is a single device, 2 is a duplex device. 3.4 is a gate circuit, 5 is a system bus interface circuit, and SBO and SBI are system paths.
Claims (1)
接続された二重化構成システムにおける前記−重化装置
側に、中央処理装置からのオンライン状態を表わすＡＣ
Ｔ情報とアイソレーション状態を表わすＩＳＬ情報を受
けて制御信号を発する第１のダート回路と、前記制御信
号により前記−重化装置の出力信号を制御する第２のダ
ート回路とを有する一重化装置のアイソレーション回路
。1. In a duplex configuration system in which a duplex device and a duplex device are connected via a system path, an AC signal indicating an online state from the central processing unit is sent to the duplex device side.
A duplexer comprising: a first dart circuit that receives T information and ISL information representing an isolation state and issues a control signal; and a second dart circuit that controls an output signal of the multiplexer using the control signal. isolation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58106804A JPS60541A (en) | 1983-06-16 | 1983-06-16 | Isolation circuit of single device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58106804A JPS60541A (en) | 1983-06-16 | 1983-06-16 | Isolation circuit of single device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60541A true JPS60541A (en) | 1985-01-05 |
Family
ID=14443042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58106804A Pending JPS60541A (en) | 1983-06-16 | 1983-06-16 | Isolation circuit of single device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60541A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS538030A (en) * | 1976-06-17 | 1978-01-25 | Fujitsu Ltd | Fault processing method |
| JPS5471537A (en) * | 1977-11-18 | 1979-06-08 | Hitachi Ltd | Failure processing system for multiprocessor |
-
1983
- 1983-06-16 JP JP58106804A patent/JPS60541A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS538030A (en) * | 1976-06-17 | 1978-01-25 | Fujitsu Ltd | Fault processing method |
| JPS5471537A (en) * | 1977-11-18 | 1979-06-08 | Hitachi Ltd | Failure processing system for multiprocessor |
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