JPS6052451B2 - Microinstruction execution control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device in which there is no problem even if there is an error in a microinstruction read from a control memory (CS).

Conventionally, error detection and correction circuits (ECC circuits) in memory devices have been relatively commonly installed in main storage devices (MSs), but CSs are not equipped with ECC circuits because the performance deteriorates significantly when the ECC circuits are used. That was rare.

Therefore, a 1-bit error in the CS causes a large overhead in error recovery processing or causes a system down. Therefore, the present invention is designed to quickly execute only whether there is an error in the microinstruction read from the CS, and only when there is an error, to execute the microinstruction using the error-corrected contents by the ECC circuit. .

As a result, most error-free microinstructions can be executed at the same processing speed as before, and if an error occurs, it can be corrected. In the present invention, for example, both a parity bit and a Hamming code are added to a microinstruction, a parity check is performed to quickly determine whether or not a read microinstruction has an error, and error correction is performed if an error is found. uses Hamming chords.

An embodiment of the present invention will be described below.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
The format of each microinstruction stored in S is shown.

To explain the general operation of the present invention using FIG. 1, first, when the storage address of the microinstruction to be executed next is set in the control memory address register (CSAR) 2,
The microinstruction at the address indicated by CSAR2 is read from the CSI.

The read microinstruction consists of a microinstruction word part, a parity bit for the microinstruction word, and a Hamming code for the microinstruction word, as shown in FIG.
A Hamming code is a check code that can detect a 2-bit error and correct a 1-bit error. The microinstruction read out from CS1 is first input to a parity error detection circuit (PCC) 3 and its parity is checked.

If a parity error is not detected in the PCC 3, the read microinstruction is immediately set in the control memory data register (CSDR) 5, and a microinstruction execution instruction signal (EXECUTE) is sent to the microinstruction execution control section (EC) 6. Send. EC6 is EXECU
Upon receiving the TE signal, it immediately executes the microinstruction set in CSDR5. After completion of execution, EC6 sets the address of the next microinstruction to be executed in CSAR2. Next, when a parity error is detected in the microinstruction read by the PCC3, the error is corrected by the Hamming code added to the microinstruction in the ECC4, and then the output of the ECC4 is set to CSDR5 and the EXECUTE signal is is sent to EC6.

The following operation is the same as when there is no parity error. Next, the logic operation around the PCC 3 will be explained in more detail.

Figure 3 shows a logic diagram around the PCC3, Figure 4 shows a time chart of the eight-phase basic timing pulses from TO to T7 required for microinstruction execution control, and Figure 5 shows a parity error detected in the PCC3. The operation time chart of FIG. 3 when the parity error is not detected is shown in FIG. 3, and the operation time chart of FIG. 3 when the parity error is detected in the PCC 3 is shown in FIG. 6. (1) When there is no parity error (
Figure 5) When the microinstruction address to be executed is set in CSAR2 at the timing of TO, the T
CSDATA read from CS1 at timing 1 is sent to parity checker (PC) 401 in PCC3 in FIG.
After a certain period of time, the output indicating that there is no parity error (the value of O of PC4O1) becomes "1".

As a result, the control flip-flop (
FF) 404 is set, and at timing T3, the output of the AND gate (,AND) 407 becomes ゜゜1゛. AN
CSD by AND gate 408 by the output of D4O7
ATA is directly connected to C via 0R gate (CR) 412.
It is set to SDR5 and 0R gate (0R)4
11 sends an EXECUTE signal to EC6.
In EC6, this controls flip-flop (FF) 4.
05 is set to execute the microinstruction, and at the timing of the next machine cycle TO, the AND gate 410
A set signal SETCSAR of the microinstruction address to be executed next is sent to CSAR2. {11) When there is a parity error (Figure 6) When CSDATA is input to PC4Ol using the same procedure as when there is no parity error, the value of Q of PC4Ol becomes ゜“1” after a certain period of time.
It becomes ゛. As a result, the control flip-flop 402 is set at timing T2, and the control flip-flop (FF) 403 is further set at timing T6. When FF4O3 is set, T3 after the ECC4 output is determined,
That is, at T3 of the next machine cycle, AND gate 40
6 is taken, and the output of ECC4 is set to CSDR5 via AND gate 409 and 0R412, and an EXECUT'E signal is output from 0R411 to EC6. The subsequent operation is the same as in the case where there is no parity error. As described above, one embodiment of the present invention has been described.According to the present invention, micro-instructions without most of them can be executed at the same processing speed as before, and micro-instructions with errors can be executed after correcting the errors. Therefore, a very efficient microprogram control device can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a diagram showing the format of microinstructions stored in the CS of FIG. 1, and FIG. 3 is a diagram of the PCC of FIG. 1. The peripheral logic diagrams and FIGS. 4 to 6 are time charts for explaining the operation of FIG. 3.

In FIG. 1, 1... control memory (CS),
2...Control memory address register (CSAR),
3... Parity error detection circuit (PCC), 4...
... Error correction circuit (ECC), 5 ... Control memory data register (CSDR), 6 ... Micro instruction execution control unit (EC).

Claims (1)

[Claims] 1. A control memory that stores a plurality of microinstructions, a control logic that executes microinstructions read from the control memory, an error detection circuit that detects errors in the read microinstructions, and errors in the read microinstructions and their correction. an error detection and correction circuit that is independent of the error detection circuit and whose speed is slower than the error detection circuit;
A microinstruction read from the control memory is simultaneously applied to both the error detection circuit and the error detection and correction circuit, and if no error is detected by the error detection circuit, the microinstruction read from the control memory is applied to the control logic. A micro-instruction execution control method, characterized in that when an error is detected by the error detection circuit, a corrected micro-instruction from the error detection and correction circuit is provided to the control logic.