JPS60187990A - Data delay circuit - Google Patents

Abstract

PURPOSE:To prevent the degradation of effective use rate of a data delay circuit without making the constitution large-sized, by using a first in first out (FIFO) circuit for delay and performing the data input operation only when data exists in an input terminal. CONSTITUTION:One-bit information indicating existence of data in the input signal applied to a terminal 7 is supplied to a one-bit delay circuit 8 and an input circuit 9, and input data on a signal line is set to an FIFO circuit 10 for data delay only when the input signal exists in an input terminal 1. This data is read out from the circuit by an output circuit 11, which takes the output signal of the circuit 8 as the input and is operated only when the signal exists, and is outputted. Thus, it is sufficient if the capacity of the FIFO circuit corresponds to a maximum number of data generated within a delay time, and dummy bits are made unnecessary, and the degradation of the effective use rate of the data delay circuit is prevented without making the constitution large in size.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data delay circuit for delaying gage digital data in various signal processing devices.

(Prior Art) Conventionally, this type of data delay circuit uses a data delay circuit using a shift register as shown in FIG. 1, or a random access memory 11 (RAM) as shown in FIG.
1 data delay circuit.

In the data delay circuit shown in FIG. 1, when the period of the input signal is constant, the input period to the shift register and the shift period are selected to be the same as the period of the input signal. On the other hand, if the generation period of the input (i) is undefined, the input period and shift period of the shift register should be selected to be equal to or less than the minimum value of the input signal frequency or the required delay time resolution. In this case, even during the 1 period when there is no input signal, double-difference data, for example, data in which all the focus points are 0, is input to the shift register.Therefore, compared to the input period of the shift register, When the average generation period of input data is long, the ratio of dummy data to the total capacity of the shift register becomes high, which causes a problem that the effective utilization rate of the data delay circuit decreases. When a large delay time is required or when the number of hits per 1 data is large, the data delay circuit has the drawback of becoming large.

In addition, the data delay circuit shown in Figure 2 uses slow memory addresses and advances the address for each input data to record the data inside the RAM, while at the same time recording the data corresponding to the delay time. The data is delayed by reading and outputting the data with the address difference.
Similar to the method using the shift register, dummy data is input in the case of a human input signal with an irregular period, so there is a drawback that the effective utilization rate of the data delay circuit is reduced.

(Objective of the Invention) The object of the present invention is to delay a single-point information signal indicating the presence of input data, temporarily store input data in the order of preceding input only when a data crab exists, and when outputting It is an object of the present invention to provide a data delay circuit which eliminates the above drawbacks and can be constructed with a relatively small circuit film by configuring the data to be read and output in the order of preceding input.

(Structure of the Invention) The data delay circuit according to the present invention inputs temporally discrete data that occurs at irregular intervals,
It is configured to include a 1-bit delay circuit, a FIFO circuit, an input circuit, and an output circuit.

The 1-bit delay circuit is used to delay a 1-bit information signal indicating the presence of input data.

The FIFO circuit temporarily stores input data and outputs the data in the order of previous input.

The input circuit is only capable of writing input data to the FIFO circuit if the input data is present at the input terminal.

The output circuit inputs the delayed output signal of the 1-bit delay circuit, and outputs the input categorization signal only when input data exists.
This is for reading and outputting from the FTFO circuit.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of a data delay circuit according to the present invention. In FIG. 3, 1.7 is an input terminal, 2 is an output terminal, 8 is an l-bit delay circuit, 9 is an input circuit, a 10-digit FIFO circuit, and 11 is an output circuit.

In FIG. 3, among the input signals applied to the input terminal 7, a 1-bit information signal indicating the presence of data is delayed by a 1-bit delay circuit 8.

The 1-bit delay circuit 8 has the same structure as the conventional delay circuit shown in FIG. 1, except that the data bit length is 1 bit. The 1-bit information signal passes to the input circuit 9, and only when the input signal is present at the input terminal 1, the input data on the signal line is set to the FIFO circuit 10.

The output circuit 11 inputs the output signal of the 1-bit delay circuit 8, and only when the signal exists, outputs the output signal ? 4, data is read from the FTP'O circuit 10 and output. Note that the data capacity required for the FIFO circuit 10 only needs to be equal to the maximum number of input data that may occur within the delay time. Furthermore, the 1-bit delay circuit 8 has the same configuration as that in the conventional system, but since the data length is 1 bit, the circuit scale is relatively small. Furthermore, in order to increase the time resolution of the delay time, it is sufficient to add the capacity of 1-bit delay line 8 and to speed up the shift cycle, and there is no need to add the capacity of the FIFO circuit itself. Powerful.

(Effect of issuing) As explained above, in the present invention, data is delayed by the PIF"0 circuit, and the data input operation is performed only when input data is present at the input terminal. This has the effect that the utilization rate of the data delay circuit does not decrease due to dummy data.Therefore, when the input signal generation rate is small relative to the delay time, or when data with a large out-of-focus per data In the case of processing, the effect of reducing the circuit scale is large, and in the case of increasing the resolution of delay time, the effect of reducing the circuit size is particularly large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a data delay circuit using a conventional shift register. FIG. 2 is a block diagram showing an example of a data delay circuit using a conventional RAM. FIG. 3 is a block diagram showing one embodiment of a data delay circuit according to the present invention. 1.2.7...Terminal 3...Shift register 4...Data switching circuit 5/9 reference m#/RAM 6...Address generation circuit 8... ...1-bit delay recall 9...Fist input circuit No. 10 - FIF'0 circuit 11 - e fist - Output circuit Patent applicant NEC Corporation agent Patent attorney + Soup day Fig. 1 Fig. 2 Fig. 1 and 3

Claims (1)

[Claims] A data delay circuit that inputs data that is temporally discrete and occurs at irregular intervals includes a 1-bit delay circuit for delaying a 1-bit information signal indicating the presence of input data, and a 1-bit delay circuit for delaying a 1-bit information signal indicating the presence of input data; an F'fFO circuit for storing the data in advance and outputting the data in the order of preceding inputs at the time of output, and writing the input data to the P'FO circuit only when the input data exists in the input conjugate. an input circuit to input the delayed output Q of the 1-bit delay circuit, and an output circuit to read the input data from the FIFO circuit and output it only when the input data exists. A data delay circuit comprising: