JPS5840852B2 - preset receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (4) Object of the present invention The present invention relates to a receiving device that is capable of preset tuning, and in particular stores the tuning voltage of the broadcast to be preset in a non-volatile analog memory. The present invention relates to a preset receiving device configured as follows.

(B) Explanation of the prior art At present, tuners using variable capacitance diodes are widely used, but when preset tuning is performed in a receiving device equipped with such a tuner, in the past, the number of preset tunings is limited. A variable resistor corresponding to this is provided, and the desired tuning voltage is obtained by dividing a constant voltage with this variable resistor, and when any preset tuning switch is operated, the tuning corresponds to this preset tuning switch. A variable resistor is selected, and a tuning voltage obtained from the variable resistor is applied to a variable capacitance diode constituting the tuner, thereby performing preset tuning.

In this conventional example, since a number of variable resistors corresponding to the number of preset selected stations is required, it is difficult to miniaturize the receiving device.

Also, a receiving device has been proposed that stores the tuning voltage as a digital value in a digital memory, reads the digital value from this memory when selecting a preset channel, and converts it from digital to analog to obtain the tuning voltage.
In this case, it is sufficient to provide a digital memory having addresses corresponding to the number of preset selected channels, so that the device can be made smaller, but there is a drawback that the analog-to-digital converters are expensive and require a plurality of analog-to-digital converters.

(q Summary of Disclosure of the Present Invention Therefore, the preset receiving device according to the present invention has a configuration in which a tuning voltage is stored in a non-volatile analog data memory, and also has a configuration in which the tuning voltage is stored in a non-volatile analog data memory. A non-volatile address memory is provided for storing whether the address of the preset station has been designated or whether the preset station of interest has been selected.

The present invention is characterized in that the data memory and address memory are set to erase, write, and read modes using only one control circuit.

Incidentally, there are Japanese Patent Application Nos. 52-126962 and 1985-128538 as similar applications to the present application, but compared to the inventions related to these related applications, the present invention has two memories (
A unique feature is that the data memory and address memory are configured to be set to erase, write, and read modes using only one control circuit.

(0 Description of Analog Memory Prior to explaining the preset receiving device according to the present invention, first, the structure and characteristics of a non-volatile analog memory will be explained.

M
There is a known nonvolatile memory that can be electrically written and erased by changing the threshold voltage of an OS transistor and making it correspond to information "1" and "O". By varying the amount of accumulated charge in response to erasing, it is also possible to store analog amounts.

Figure 1 shows the structure of such a memory.
It is a floating gate type memory replaced with a triple structure of a dioxide film 1, a molybdenum film 2, and a S is N4 film 3.

Setting the threshold voltage Vt of a MOS transistor in a more negative direction is called "erase," and conversely, moving the threshold voltage Vt in a more positive direction is called "writing." , erasing will utilize the Forer-Nordheim tunnel effect from the floating gate, and writing will utilize avalanche injection from silicon.

FIG. 2 shows the relationship between memory read voltage and drain current, and FIG. 3 shows the relationship between memory erase/write voltage and threshold voltage.

In FIG. 3, curve a shows the writing characteristics,
For example, when the write drain voltage is Vd', the threshold voltage is Vt'.

The curve shows the erase characteristic; for example, when the erase gate voltage is Vg, the threshold voltage is ■tlc.

Figure 2 shows the read characteristics. When the read gate voltage is G, the drain current when the write voltage is Vd' is Id', and the drain current when the write voltage is Vd'' is Ia/ / indicates that.

In other words, the threshold voltage changes in response to the difference in the write voltage, and the drain current at the time of reading changes in response to the change in the threshold voltage. It is possible.

Now, if the threshold voltage of the MOS transistor is t' due to the write voltage Vd', then the new write voltage Vd"
By applying , the threshold voltage of the MOS transistor becomes
t''.

That is, writing from C to A in FIG. 3 is possible.

Since writing from reverse VCA to C is practically difficult, in this case, after erasing and shifting to B and setting the threshold voltage to Vt, write to C by applying the write voltage Vd'. to do.

Figure 4 shows M in erase, read, and write modes.
FIG. 3 is a diagram showing the bias state of an OS transistor memory.

In erase mode, the drain is grounded, the source is open, and a negative pulse is applied to the gate.

In read mode, the source is grounded and a negative power supply is supplied to the gate and drain.

In write mode, the source is open, the gate is grounded, and a negative pulse is applied to the drain.

(G) This is the first explanation of the normal channel selection operation.The block diagram of the preset receiving device according to the present invention using such a non-volatile analog memory is as shown in FIG. First, the normal channel selection operation will be explained.

To perform normal channel selection, the tuning voltage may be swept by switching the switch 101 to the N side and operating the variable resistor constituting the tuning voltage generation circuit 102.

When a predetermined tuning voltage is applied to the variable capacitance diode constituting the tuner circuit 201, the tuner circuit 201 is tuned to a predetermined broadcast frequency.

The intermediate frequency signal output from the tuner circuit 201 is amplified by an intermediate frequency amplifier 202, and further amplified by a detection circuit 203.
The signal is detected by a low frequency amplifier 204, and then amplified by a low frequency amplifier 204 and applied to a speaker 205.

In this way, reception by normal channel selection is achieved.

Note that instead of the method in which the tuning voltage generation circuit 102 is configured with a variable resistor and the tuning voltage is manually swept by manually operating the variable resistor, the tuning voltage generation circuit 102 can be configured with a conventionally known sawtooth wave generation method. It can be configured with a circuit to automatically sweep the tuning voltage and stop the sweep when a broadcast is received, or it can be configured with a variable resistor to enable both manual and automatic sweeps. A configuration may also be adopted in which both a tuning voltage generation circuit constituted by a sawtooth wave generation circuit and a tuning voltage generation circuit constituted by a sawtooth wave generation circuit are provided and selectively connected to the tuner circuit 201 by a switch.

(F') Description of the overall configuration and operation of the device according to the present invention The preset receiving device according to the present invention adjusts the tuning voltage for the broadcast received by the normal channel selection operation described in the above (g) to an analog. Preset reception is performed by storing it in memory.

The overall configuration and operation of the apparatus of the present invention will be briefly described below with reference to FIG.

The selection gate control circuit 106 is driven by operating the band selection switch 104 and the preset channel selection switch 105, which act as address designation switches to specify which analog memory the tuning voltage is to be stored in. , a predetermined address of the non-volatile data analog memo IJ-107 is selected by the output of this circuit 106, while the erase/write/read mode control circuit 108 is driven by operating the preset memory switch 103. Thus, the write voltage output from the erase/write/read voltage generation circuit 109 is written into the data memory 107 at the predetermined address.

The voltage written in data memo IJ-107 is immediately read out and compared with the tuning voltage output from tuning voltage generation circuit 102.

Note that the data memo IJ-107 does not store the tuning voltage itself, so the data memo IJ-107 does not store the tuning voltage itself.
The read output of 107 is suitably amplified by a conversion circuit 1101c, and the output of this conversion circuit 110 is compared with the tuning voltage.

Such write and read operations are repeated until the tuning voltage and the read output of the data memory 107 match. When they match, a stop signal is generated from the comparator 111, and the data memory IJ- Writing to 107 is completed.

That is, data corresponding to the tuning voltage output from the tuning voltage generation circuit 102 has been written into the data memory 107.

To perform preset tuning after data (tuning voltage) has been written to the data memory in this manner, switch 101 to the P side and operate band selection switch 104 and preset tuning switch 105. Good.

Then, the readout output read from the data memory at the address specified by these switches 104 and 105 is amplified by the conversion circuit 110, and the output of this circuit 110 is applied as a tuning voltage to the tuner circuit 201. Therefore, broadcast reception can be performed by preset channel selection.

By the way, after receiving a certain broadcast by preset channel selection, there are cases where it is desired to turn off the power to the receiving device, and when the power is turned on again, to be in the receiving state of the previously received broadcast.

In order to realize such an aspect, it is sufficient to provide a non-volatile address memory for storing which band selection switch 104 and preset channel selection switch 105 has been operated.

Therefore, in the embodiment shown in FIG. 5, when the band selection switch 104 and the preset tuning switch 105 are operated, the address specified by this operation is first stored in the address memo IJ-112, and this address The configuration is such that the aforementioned selection gate control circuit 106 is controlled by the readout output of the memory 112.

That is, a non-volatile memory and selection gate circuit 112 for storing addresses, a selection gate control circuit 113 that controls this selection gate circuit, and an erase/write/read voltage generator that applies erase/write/read voltages to this address memory. The circuit 114iC makes it possible to store the specified address described above.

According to the above-described configuration, when the power is turned on again, the selection gate control circuit 1 is activated by the readout output of the address memo IJ-112.
06 will be driven, thereby giving data memory IJ-107 the same addressing as before.

(q Detailed explanation of each operation of the device according to the present invention)Next: Regarding the operations of [writing the specified address to the address memory], [writing the tuning voltage to the data memory], and [preset tuning] , explain in detail.

In the following embodiments, in order to simplify the explanation, a preset receiving apparatus with two preset stations and two bands (AM, FM) will be described as an example.

[Writing of specified address to address memory] Band selection switch 104, preset tuning switch 105
The address specified by is stored in a nonvolatile analog memory having the configuration described above.

Since the address itself is a digital quantity, the address
Non-volatile digital memory may be used as the memory.

The specific configuration of the address memory and selection gate circuit 112 is as shown in FIG.

An address memory MB12MB2 is provided to store band addresses, and an address memory Ms12Ms2 is provided to store channel selection addresses.

Gates G and ~G7, which are constructed of field-effect transistors for selectively erasing, writing, and reading address memories MB1 and MB2, also operate similarly for address memories Ms1 and MB2. Gate 08
~G14 are provided, respectively.

Since writing of the band address and writing of the channel selection/address are performed in exactly the same way, only the writing of the band address will be explained below.

Gate G1. G2 selectively applies the write voltage ■w or the read voltage y6 supplied from the erase/write/read voltage generation circuit 114 to the drain of the memory MB19MB2 to set the memory MB12MB2 in the write mode or the read mode. It is something.

Gate G3. G4 is open in both the erase mode and the read mode, and in the write mode, only one side is closed to set one side of the memory MB12MB2 in the write mode.

Gate G5. G6 selectively applies erase voltage ■E1 or read voltage ■□ supplied from erase/write/read voltage generation circuit 114 to the gate of memory MB12MB2, and sets memory MB19MB2 to erase mode or read mode. It is for.

Gate G7 opens in read mode to read memory MB.
This is for grounding the source of 12MB2, and in this read mode, a band addressing output is obtained from both ends of the source resistor.

It should be noted that the voltages (E), (W), (R9) and (R') supplied from the erase/write/read voltage generation circuit 114 are all constant voltages.

The erase/write/read mode control circuit 108 and the selection gate control circuit 11 explain how the band address is stored in the memory MB when the band selection switch 104 is operated to select the AM band in rice.
A detailed explanation will be given with reference to FIG. 13 showing a specific example of No. 3.

When the band selection switch 104 is operated, OR gate 1
0 11 12 opens.

The high level output of the OR gate 12 (hereinafter the high level output will be referred to as "1" and the low level output as 44041) clears the counter 14 and the serial-in-parallel-out type shift register 16, and also clears the oscillator 13.
is driven.

The pulse output from the oscillator 13 is appropriately frequency-divided by the counter 14 and applied to the data terminal of the shift register 16.

The shift register 16 sequentially outputs pulses from the terminals 1, 2, and 3, but when the pulse is output from the terminal 3 and the output of the NOR gate 15 becomes "0", the clock terminal CK of the shift register 16 no longer outputs pulses. No clock input is applied and operation of shift register 16 is stopped.

When a pulse is first output from terminal 1 of the shift register 16, both of the AND gates 29 become high level, and the output of the NOR gate 30 changes from "1" to "0". Further, the output of the inverter 31 is inverted from "011" to "1".

The "1" output of the inverter 31 opens the gate G5.

On the other hand, the single power of the ungate 28 is "011", and the outputs of the NAND gates 24 and 25 are both 1".

The "1" outputs of NAND gates 24 and 25 cause gates G3. G4 is open together.

Therefore, gate G3. G4. Memory MB via G5
Erasing voltage ■E is applied to the gate of 19MB2, and the information (band address) previously stored in memory MB1 or memory MB□ is erased.

That is, when a pulse is output from terminal 1 of the shift register 16, the gate G3. G4. G5 is opened and address memories MBt and MB2 are set to erase mode.

Next, when a pulse is output from terminal 2 of the shift register 16, the AND gate 28 is driven and its output becomes "'
1".

At this time, both of the two powers of the NAND gate 24 become "1"', and the output becomes 1 (011).

Nand gate 25, Noah gate 30, inverter 3
The state of 1 is similar to the erase mode.

Therefore, the outputs of NAND gate 25, AND gate 28, and inverter 31 each become "1", so that gate G1. G4. G5 opens.

Then, the write voltage ■w is applied to both drains of memories MB1 and MB2 through gate G1, but since gate G3 is closed, the gate of memory MB1 is grounded through the gate resistor, while the memory -MB2
Gate G5. Since the erase voltage (E) is applied via G4, writing is performed only to the memory MB.

When the band selection switch 104 is operated to select the FM band, the gate G1. G3. G5 opens and notes')
- A write is made to MB2.

When a pulse is output from terminal 2 of the shift register 16 in this way, the memory MB1 or memory MB
2 is set to write mode.

After that, when a pulse is output from terminal 3 of the shift register 16, the operation of the shift register 16 is stopped.
and the output "1" of the NOR gate 30 causes the gate G2 .
G3. G4. G6. G7 is open.

Therefore, the read voltage ■'R is applied to the drain of memory MB12MB2 via gate G2, and
1. Gate G3. for the gate of MB2. G4. G6
A read voltage ■R is applied through the memory MB
Since the source of 19MB2 is grounded through gate G7, both memories MB19MB2 are in read mode,
The information stored in either memory, ie the band addressing output, is read.

Writing of the channel selection address is performed in the same manner.

That is, by operating the preset channel selection switch 105, the Nantes gates 26, 27, and gates 32, 33
, Noah gate 34, inverter 35, and gate 0
8 to G14 are selectively controlled as appropriate, and the channel selection and address are written to the memory M81 or MB2.

Furthermore, since the above-mentioned erasing and writing operations to the memory are performed instantaneously, when the switches 104 and 105 are configured with touch switches, even if the finger is in contact with the touch switches for a short time, it is sufficient. can be erased and written to.

[Writing tuning voltage to data memory]

As explained in the previous section, by operating the band selection switch 104 and the preset tuning switch 105, the band address and the tuning address are written into the memory 1121c, and after that, the mode is continuously set to read from the memory 112. A band/address designation output and a channel selection/address designation output are output, and the tuning voltage generation circuit 102 outputs the data memo IJ-107 at the address designated by these two outputs. How the tuning voltage is written will now be explained.

The tuning voltages are stored in a non-volatile data analog memory configured as described above.

The specific configuration of the data memory and selection gate circuit 107 is as shown in FIG.

In order to simplify the configuration of gates provided around the data memory, the data memory IJ-MA is used.

The MA22MF19MF2 are arranged in a matrix, with bands corresponding to rows and preset stations corresponding to columns.

Gate G21. G2□, gate G23. G24, gate G25. G26, gate G2. , G28 are controlled in connection with addressing.

A specific example of the selection gate control circuit 106 that controls the gates 021 to G28 is shown in FIG. Erasing, writing, and reading are performed only to the data memory at a predetermined address.

Gates G29-G33 are controlled in relation to erase, write, read, and mode.

Erase/write/control gates 029 to G33
A specific example of the read/mode control circuit 108 is shown in FIG. 7, and timing waveform diagrams for each mode are shown in FIG. 8.

Gate G29. Read voltage ■□ for G3o.

■R' (constant voltage), write voltage (sawtooth wave voltage) for gate G31, and erase voltage (constant voltage) for gate G3□ are the erase/write/read voltage generation circuits. 109.

With paddy, terminal T1. When the address/designation output is applied to T2, when the preset/memory switch 103 is operated, how can the memory M
A description will be given of whether a tuning voltage is written to A1.

When the preset memory switch 103 configured with a touch switch is operated, switches 104 and 105 are activated.
The oscillator 13, counter 14,
Shift register 16 is driven.

When a pulse is first output from terminal 1 of the shift register 16, both the outputs of the AND gate 23 become 1'', and the output of the AND gate 23 becomes "1".

Due to the output “'1” of the AND gate 23, the gate G3
2 opens.

On the other hand, the inverter 2122 whose output is normally "1"
Of these, only the inverter 21 is inverted by the output "1" of the AND gate 23, so the output of the AND gate 38 becomes "1" and the gate G2□ is opened.

Therefore, the erase voltage VE is applied only to the memory MA+ via the gates G2□ and G32, erasing previously stored information and making it possible to write new information.

That is, when a pulse is output from terminal 1 of the shift register 16, the erase mode is entered (see FIG. 8C).

The monostable multi-by-break 24 is triggered by the output "1" of the AND gate 23, and its output is inverted from "1" to "0" during the metastable period T. It is possible to write to the memory inside (8th
(see figure).

That is, unlike address writing, data writing cannot be accomplished instantaneously, so during the metastable period T, the NOR gate 20 is driven to keep the oscillator 13 in continuous operation.

The stop signal is normally 14011, and when the desired tuning voltage is written into the memory, the stop signal becomes "1", stopping the operation of the oscillator 13 and preventing new writing.

The stop signal will be explained in detail later.

For rice, the output of terminal 1 of the shift register 16 is ``0''
After being inverted, the outputs of the NOR gates 1-18 and 19 respond to the output of the counter 14 (alternately becoming "1", and the write/read mode is repeated alternately).

When the output of the NOR gate 19 is "1", it is the write mode (see FIG. 8C), and when the output of the NOR gate 118 is "1", it is the read mode (see FIG. 8). (See C)
.

When the stop signal becomes "1" (see Figure 8C), Noah
The output of the gate 17 is continuously "0", so the output of the NOR gate 18 is continuously "1".

Therefore, the read mode is maintained continuously.

As described above, since the shift register 16 stops operating after the output of the terminal 3 becomes "1", the output of the terminal 1 does not become "'1" again.

That is, the erase mode appears only once immediately after the preset memory switch is operated.

In the write mode, the output "1" of NOR gate 19 and AND gate 37 causes gate G21.
3. is opened, the write voltage ■w is supplied only to the drain of the memory MA1 through these gates G2□ and G3°, and writing is performed to the memory IJ-MA1vc.

In the read mode, the gate G2 is
□, G2□, G29. G3o and G33 are opened, and the read voltages ■□, ■R/ are applied to the memory MA through these gates.
1 to the drain and gate of memory M
A readout output is obtained from a resistor R connected between the source of A1 and ground.

Since the source current of the memory MA1 changes depending on the write voltage, the read output differs depending on the write voltage.

The readout output taken out from memory MA1 is sent to conversion circuit 1.
After being inverted and amplified at 10, it is compared with the tuning voltage generated by the tuning voltage generation circuit 102, and a match is found.

The write/read mode is repeated until.

When the two match, a stop signal is generated from the comparator 111, and the read mode continues and new writing is blocked (see FIG. 8C).

Figure 9 shows the memory M obtained from the source resistance R.

This shows a specific example of a conversion circuit 110 that converts the readout output of 1 to an actual tuning voltage.
It is considered to be the tuning voltage.

The comparator 111 is configured to output a stop signal when the output of the inverting amplifier 50 becomes larger than the output of the tuning voltage generator 102.

According to such a configuration, even if there is no read output of the memory MA1 and the output of the inverting amplifier 50 is O in the erase mode or the write mode, no stop signal is generated.

That is, the stop signal is generated only in the read mode.

In this way, the analog value corresponding to the tuning voltage generated by the tuning voltage generating circuit 102 is written into the memory MA1.

Similarly for memory MA22MF12MF21c,
By selectively driving and controlling the antenna gates 39 to 47 and gates 023 to G28 as appropriate, an analog value corresponding to a desired tuning voltage can be written.

Next, the write voltage applied to the data memory will be explained in more detail with reference to FIG.

In FIG. 10, waveform a shows the output of the NOR gate 20, and T is the metastable period of the monostable multivibrator 24, during which writing is possible.

The figure shows time t. (When the preset memory switch 103 is operated for the first time at C, no stop signal is generated during the period T, writing is performed to the data memory at the highest write voltage, and at time t1 When the preset memory switch 103 is operated for the second time, a stop signal is generated at time t2VC, and writing is performed using the write voltage at time t21c.

The waveform indicates a sawtooth wave write voltage generated from the erase/write/read voltage generation circuit 109, and this sawtooth wave starts sweeping in response to the operation of the preset/memory switch 103, and is The sweep is stopped in response to the end of the operation of the stable multi-by-break 24 or a stop signal.

Waveform C is the write mode output (
8C), that is, the write voltage actually applied to the data memory.

Here, the relationship between the width of the write/read pulse and the sawtooth wave C sweep time T will be explained.

The write pulse width ta and the read pulse tb are determined by the memory's loading/reading speed characteristics and the tuning frequency deviation (△■) allowed by the tuner2, that is,
If the width (ta+tb) is too small, there is a risk that sufficient writing and reading from the memory will not be possible.
If the width (ta+tb) is too large, the difference in the write voltage value between the write pulse (n) and the write pulse (n+1) becomes large, and the tuning accuracy deteriorates.

Roughly, 4 mV ri (ta+tb) is required for Δ■ and 2 m5ec.

(Here, assume that the tuning voltage is changed from (1) to (2).

The following formula holds true.

That is, the sweep time T is as follows.

(■2 Vl) differs depending on the broadcast hand, but ■2
-■1=8■ to find the sweep time T, T==4s
It becomes ec.

That is, it takes a maximum of 4 seconds to preset the tuning voltage in the memory, which is not desirable in practice.

In order to eliminate this drawback, the relationship between the tuning voltage and the write voltage must be determined in advance, and for example, the write voltage ■w
- If you want to write a tuning voltage corresponding to nlc into the memory, you can start writing at a write voltage (for example, ■w-n') that is slightly lower than the write voltage -n.

That is, if the sawtooth wave is swept as shown in FIG. 10d, the writing time can be shortened from t' to t.

FIG. 11 shows a specific example of a circuit 109 that generates such a sawtooth wave write voltage.

The operational amplifier 51 has a tuning voltage generation circuit 10 at its input.
When the tuning voltage Tu''n generated by the tuning voltage Tu''H is applied, a voltage VW-n' which is slightly lower than the write voltage (2)/n corresponding to the tuning voltage Tu''H is output.

Gate G. When the output of the Noah gate 20 is “1”,
It opens.

Now, Gate G.

is closed, the potentials at points A and B are both Vc (■
w−n′).

Then, when the preset memory switch 103 is operated, the output of the NOR gate 20 becomes "1" and the gate G is set.

opens. Then, the capacitor C starts discharging, and the potential at point A changes from (■w-n) to the potential obtained by dividing the potential difference (VVW-n') by the resistors R1 and R2.

That is, it is possible to obtain the write voltage ■w as shown in FIG. 10d from point A, and writing can be performed immediately after the preset memory switch 103 is operated.

[Preset channel selection]

After presetting a desired tuning voltage in the data memory 107, reception by preset tuning is possible.

That is, it is sufficient to switch the switch 101 to the P side and operate any band selection switch 104 and preset channel selection switch 105.

For example, if the AM band is selected by switch 104, address memory MB19MB2 goes into erase mode, then goes into write mode, where only memory MB1 is written, and then continues into read mode, where memory MB1 A band address output indicating the AM band is output.

Similarly, when the first channel is selected by the switch 105, a channel selection/address output instructing the first channel to be selected is outputted from the memo ')'-MS1.

The data memory 107 is addressed by these two address outputs.

On the other hand, in the normal state when the preset memory switch 103 is not operated, the data memory 107 is continuously in the read mode, as is clear from the above explanation. A readout output is derived from the data memory, ie, memory MA1, is amplified by a conversion circuit 110, and then applied to a tuner circuit 201 via a switch 101.

In this way, reception can be achieved by preset channel selection.

Now, let us consider the case where the power to the receiving device is turned off once after receiving the message through preset channel selection, and then the power is turned on again.

Address memory 112 is normally in read mode as previously described.

Therefore, the same addressing output as before is derived from the non-volatile address memory 112.

That is, the same broadcast as before can be received.

0 Effects of the present invention The preset receiving device according to the present invention described above includes a nonvolatile data memory that stores an analog quantity corresponding to a tuning voltage, and a memory that stores which address is designated for this data memory. A unique erase/write/read mode control circuit is provided for both the non-volatile address and memory for storage, and once the data memory is set to erase mode in response to the preset memory switch. By alternately and repeatedly setting the write mode and read mode, it is possible to write an analog amount corresponding to the desired tuning voltage.
Since the address can be written by sequentially setting the address/memory to erase, write, and read modes in response to the band selection switch), the configuration is simple, and the preset writing and preset tuning operations are easy. is extremely simple.

[Brief explanation of drawings]

Figure 1 is a diagram showing the structure of a MOS transistor memory, Figure 2 is a diagram showing the relationship between memory read voltage and drain current, Figure 3 is a diagram showing the relationship between memory erase/write voltage and threshold voltage, and Figure 4 is a diagram showing the relationship between memory read voltage and drain current. 5 is a diagram showing the bias state of the memory in erase, read, and write modes, FIG. 5 is a block diagram of the preset receiver according to the present invention, and FIG. 6 is the data memory and selection gate circuit 107. Figure 7 shows a specific example of erasing, writing,
Read mode control circuit 108 and selection gate control circuit 1
06, FIG. 8 is a timing waveform diagram for each mode of erase, write, and read, and FIG. 9 is a diagram showing the conversion circuit 11.
Figure 10 is a waveform diagram of the write voltage.
FIG. 11 is a diagram showing a specific example of the write voltage generation circuit.
2 is a diagram showing a specific example of the address memory and selection gate circuit 112, and FIG. 13 is a diagram showing a specific example of the erase/write/read mode control circuit 108 and the selection gate control circuit 113. 101 is a normal tuning/preset tuning switch; 1
02 is a tuning voltage generation circuit, 103 is a preset memory switch, 104 is a band selection switch, 10
5 is a preset channel selection switch, 106.113 is a selection gate control circuit, 107 is a data memory and selection gate circuit, 108 is an erase/write/read mode control circuit, 109° 114 is an erase/write/read voltage generation circuit, 110 is a conversion circuit, 111 is a comparator (stop signal generation circuit), and 112 is an address memory and selection gate circuit.

Claims (1)

[Claims] 1. A nonvolatile data memory that stores an analog quantity corresponding to a tuning voltage, a preset memory switch that instructs writing of the analog quantity to the data memory, and a preset memory switch that instructs writing of the analog quantity to the data memory. an address designation switch that designates an address; a non-volatile address memory that stores the address designated by the address designation switch; - a control circuit that sets the memory to erase, write, and read mode; the control circuit sequentially sets the address memory to erase, write, and read mode in response to the address designation switch; On the other hand, in response to the preset memory switch, the data memory is once set to erase mode, and then set to write mode and read mode alternately and repeatedly, so that the read output of the IC data memory is set to a desired tuning voltage. 2. A preset receiving device that continuously sets the data memory in a read mode in response to a stop signal generated when the data memory coincides with a stop signal. 2. The preset receiving device according to claim 1, wherein the address designation switch is a preset channel selection switch. 3. The preset receiving device according to claim 1, wherein the address designation switch is a preset channel selection switch and a band selection switch.