JPS58166876A - image process equipment - Google Patents

Abstract

PURPOSE:To ensure a fixed level fot the MTF of a lens and the space frequency of a CCD containing the lens, by providing CCD, ALL, AGC, A/D converter, peak detector, magnitude comparator, etc. CONSTITUTION:An ACC circuit 5 clamps the black level of a video signal of a CCD 3 at a fixed level of voltage. An AGC circuit 6 produces automatically a signal having a fixed level of maximum amplitude regardless of variations of the aperture value of a lens 2 and the sensitivity of the CCD 3. A shading compensating circuit 7 compensates the marginal illumination characteristics of the lens 2 and the variance of sensitivity of the CCD 3. An A/D converter 8 converts an analog video signal into a digital signal. A peak detector 11 compensates the MTF characteristics of the lens 2 and the frequency characteristics of the CCD 3 together with a contout emphasizing circuit 10. A magnitude comparator 12 compares a digital signal underwent the compensation of characteristics with the dither matrix data which is previously written to an ROM 13 and delivers a digital video signal of 1-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device that passes an output image signal of an image reading device that electrically captures an original image.
0D (tcha'1I-aojipteddema1ce) When using a solid-state image sensor to electrically read, transmit, and print a digital image, it is converted into a black and white binary code. During transmission, the quality of the reproduced image is poor (due to the influence of shading of the camera element and optical system).In other words, when reading an image with a solid-state image sensor such as 00D, the entire image is uniform. The output image signal waveform of a solid-state image sensor may not necessarily be flat even when the image is white. This phenomenon is called shading. The main cause of shading is the In addition, the transfer efficiency may not be 100%.Other reasons include manufacturing variations in solid-state image sensors such as 00D, vignetting at the periphery of the optical lens interposed between the document and the OOD, and unevenness in the light source that illuminates the V1 document. In contrast to this, which also causes shading, Japanese Patent Application Publication No. 5
3-139421 and Japanese Unexamined Patent Publication No. 54-21219, methods to eliminate this phenomenon using relatively simple circuits such as a low-pass filter and a delay element have been introduced. However, if you want to reproduce half-tones, the methods described above cannot be used, and the level, gain, and linearity of the video signal must be precisely matched to that of the original document, and analog-to-digital conversion is required to achieve faithful reproduction. High-quality print production cannot be expected.0 On the other hand, when faithful reproduction is performed, the desired image may become unclear due to the background color reproduction of the document.

Also, noise during image signal processing and grasshopper ground are eliminated.
Processing that emphasizes the ``1 link in the image'' is known, but this process can degrade the image quality. If this is done, the slight noise generated in the processing circuit in the back ground will be emphasized, making the reproduced image very unsightly. This is mechanically moved relative to the sub-scanning direction, or the optical system is moved to scan the entire image of the document.
When scanning an original, if such contour enhancement is performed in both the main scanning direction and the sub-scanning direction, the resulting reproduced image will have a different resolution in the main scanning direction and a resolution in the sub-scanning direction. (The image is the one that was rotated by 90'' and the image signal was reproduced, and the image is continued without rotation.)
The reproduced image will be different. Also, when reading a wide document by reading multiple OODs serially in the line direction7), the processing circuit 100D(2) may be operated in accordance with the characteristics. 〇Also, if one contour strengthening treatment is performed after converting the image signal into a digital signal, contour strengthening 1g to perform such strengthening processing! Roads require many components. If this contour strengthening circuit is provided for each of multiple θ/S image pickup elements, the cost will increase and the device will become larger. (continued) When obtaining an 1Dm image signal, the MTF of the lens constituting the optical system and the spatial frequency characteristics of the OOD including the lens are not constant. For example, OOD.

The back center of the image pickup device made of 70 mm is large and the spatial frequency characteristics are not constant.Also, if the lens is controlled by the light intensity, the MTF will deteriorate as the aperture 9 is opened. The object of the present invention is to eliminate the above-mentioned drawbacks and to provide an image processing device capable of bird-quality reproduction. The object of the present invention is to provide a copying apparatus capable of converting the level or gain of a bj image signal to the least significant bit (1) of a converter.
The purpose of the present invention is to provide an image signal processing device that can be controlled with an accuracy of L8B), and an image forming device that can be reproduced and printed. The purpose of the present invention is to improve an image processing apparatus that can eliminate noise during processing.The present invention aims to provide an image forming apparatus that can perform image linkage to eliminate the above-mentioned noise.

The purpose of the present invention is to provide an image signal processing device that can perform optimal blur correction in each direction of main scanning and sub-scanning. The purpose of the present invention is to provide an image processing device that can perform convenient pairwise ink correction, and an image processing device that can perform correction.

The object of the present invention is to provide an image processing device for processing document sequence and read image data using a time share technique. 1 Image processing device 1 that processes using an emphasis circuit
1, and the present invention also aims at an image processing device that reduces deterioration in the quality of reproduction due to the spatial frequency of an image signal. 1 is a basic block diagram of an embodiment of a 1IiIII7 signal processing device according to the present invention; FIG. In the figure, ■ is the manuscript;
Line CCD photography gI as if using a mechanical conveyance device (not shown)! However, other imaging means may be used as long as they can remove the brightness and darkness on the original image and generate an image signal (video signal). For example, an MO8 type light receiving element may be used. Instead of conveying the original l, the lens 2 and CCD 3 may be moved to perform sub-scanning. A video amplifier 4 amplifies the output voltage of the CCI 3 to a required level. If an AC amplifier is used instead, a powerful lamp circuit is required. 5
is an automatic level control circuit (ALC circuit) that clamps the black level of the video signal to a constant voltage, for example, zero voltage. Therefore, the video amplifier 4 may be an AC amplifier. Reference numeral 6 denotes an automatic gain control circuit (AGC circuit), which is capable of controlling even if there is a change in the light intensity of a light source illuminating a document (not shown), a change in the aperture value of the lens 2, a variation in the sensitivity of the CCD 3, etc.
Automatically creates a video signal with a constant maximum amplitude. 7#
The I/D/G correction circuit calculates the unevenness of the light intensity of the light source, the peripheral light intensity characteristics of the lens 20, the CO8θ characteristics, and the CC
This is to correct the sensitivity unevenness of D3. The shading correction circuit 7 is disclosed in the patent application filed in 1982 by the present applicant.
I used the one shown in No. 140787 Km. (Described later) 8 is an A-D converter, and a clock pulse (not shown) -! The analog video signal is sampled into a digital signal. The sampling level may be greater than the required gradation depth; for example, a case of 6 bits and 64 gradations will be explained.

9 is a limiter circuit for removing small flaws ftjl from the white and black parts of dIigll.

IO is a digital filter (contour enhancement circuit) that performs edge enhancement processing on the digital image signal.

Reference numeral 11 denotes a peak detector for automatically determining the supplementary +E amount of the contour emphasizing circuit 1O so as to be able to equally emphasize one link regardless of main scanning, sub-scanning, or spatial frequency. This constitutes an equalization circuit that corrects the MT1% property of the lens 2 and the frequency characteristics of the CCl 3.

＾ Show examples of low and low values. For example, 5 black pieces (51
p/wm), the spatial frequency is called 10 pe/.

12 is a read-only memory (ROM) for a magnitude conoperator and a 13H dither matrix. digital video signal whose characteristics have been compensated by the comparator 12)
10M13 is compared with the dither matrix data written in advance, and a 1-bit (1/ine) digital video signal is output from the output terminal 14.

The digital video signal output terminal 14 is connected to a printer via a modulator (not shown) or directly connected to the printer to reproduce the image.

FIG. 2 is a basic block diagram of an embodiment of the image signal processing apparatus of the present invention when two CCD image sensors are used. As the manuscript for shooting becomes larger, a larger CCD is also required, but in reality, due to the manufacturing constraints of silicon elements, large CCDs are difficult to manufacture, and even if they were realized, they would be difficult to manufacture. The KA value becomes extremely high. Therefore, a method of reading guns using a plurality of CODs is generally well known. FIG. 2 shows two systems of automatic equalization of the video signal in the reproduction frequency range according to the example shown in FIG. 1, and finally a continuous digital video signal 29 can be obtained by the parallel-serial converter 28. .

However, configuring two video signal processing circuits in this manner is economically disadvantageous. Therefore, FIG. 3 shows an embodiment in which the edge enhancement circuit 1O1 and the edge enhancement circuit 23, which have the most complicated and large-scale circuit configurations, are configured with one edge enhancement circuit 30 and are controlled in a time-division manner. . In this case, since the ALC, AGC, and A-D converters are separate from the CCD, it is possible to deal with variations in the characteristics of the CCD.

In Figures 2 and 3, the 15Fi lens.

161; tccD, l 7 is a video amplifier, 18 is an automatic level control circuit (ALC), 19 is an automatic gain control circuit (
AGO circuit), 20 is a shading/guessing correction circuit, 21#
'1 A-D converter, 22 a square ivy circuit, 23 and 30 digital filters, 24 a peak detector, 25 a magnitude comparator, and 26tli dither matrix fLOM, each of which is connected to the lens 2 in FIG. CCD3
．． Video amplifier4. ALC5, AGC6, shading correction circuit 7. A-D converter8. Limiter circuit 91
Contour enhancement circuit 10. Peak detector 11, magnitude comparator 12. aOM for dither matrix
It has the same function as 13. Further, 27 and 29 are video signal output terminals, and 28 is a parallel/serial converter.

The details of each circuit in Figures @1 to ta3 are explained below □
"do.

(1) Automatic Level Control Circuit (ALC Circuit) 1114 A block diagram of an embodiment of the ALCl circuit according to the present invention is shown in FIG. In this example, a specific black signal from the CCD is stabilized and clamped to a certain value.

This allows you to shift the overall level.

is the input terminal, bn (n = 0, 1, 2...) is the output terminal, SO is the adder, 51 is the multiplier, 52 is the A-D converter and the clock -! It is Sanopuru. The multiplier 51 is
This is not necessary for the LC circuit, but it must be inserted in this stage when combined with an AGO circuit, which will be described later. The adder 50 outputs the relationship A+B=C.

The analog video signal that has passed through the adder 50 and multiplier 51 is quantized into, for example, a 6-bit digital signal by the A-D converter 52, and applied to the magnitude comparator 53, where it is combined with the preset data of the preset switch 54. be compared. A 6-bit magnitude comparator can be easily constructed by cascading 4-bit magnitude comparators. Preset switch 54#i, & for example (000
001). In this case, the video signal is (00
0000), the A<B output terminal becomes high level (hereinafter referred to as "H"), and the A=B output terminal becomes low level (hereinafter referred to as "H").
The video signal becomes (ooooo i
>, the A(B output terminal is L", and the A-B output terminal is @H". Furthermore, the video signal is (ooo).

10) When it is larger, both become @L'''.

A counter 55 is reset by the CCD read horizontal synchronizing signal - summer, counts the pixel signal transfer lock φT, and outputs it to Qn (n=0.1.2...).

The number n of pits is set to the number necessary to separate the image section of the CCD 3 from the non-image black level section. For example, if 12 bits are set, 4096 pixels (1247 minutes) can be addressed. The counter 55 is constructed by, for example, three stages of four-pit synchronous counters connected in cascade.

In this example, for example, the reference point pulse B R, -it 13 F outputted from C'CD in FIG. 26 is taken as the non-image black level.

The 56#i gate circuit is a fi1 gate circuit for addressing the black level section of the non-picture area in the video signal, and is configured using, for example, a multi-input ANDid path. GVi is its output terminal and is connected to AND gate 57 so that rA<B
It is gated in the J wound signal low level section.

58 is an up/down counter, which receives the vertical synchronization signal "C0P
YJ (appears just before the start of the St job selection for each member of the document)
The preset switch 59 is loaded with preset data, and the horizontal synchronizing signal φX is counted up (or down). up/down counter 58
The output of QAQrFiD-me is input to the converter 60 and transferred to the lock! It is converted into an analog signal and sent to an adder 50.
The other input electronic BK is input.

The level control mechanism is as follows. First, at the start of reading, the up/down counter 5B loads the data of the preset switch 59 using the signal ('-COPYJ), transmits the value as it is to the DA converter 60, and converts it into an analog signal.The analog signal and video input The signals are summed by adder 50 and then sent to converter 52.
D-converted. As a result, the black level is 0ooot
o > When the directivity is greater than "Person < HJ output is @L#
Then, the up/down counter 58 enters the countdown mode and counts down the previously loaded data in synchronization with the horizontal synchronizing signal φX. Then, A-D
The DC level of the video signal applied to the input terminal of the converter 52 begins to fall for each COD line reading scan, and [A=BJ output is @H'', that is, the black level of the output signal of the human-D converter 52 becomes ( 000001), the up/down counter 58 stops counting the number of sets because the INHJ input becomes "H". That is, the black level of the video signal is (000001). If the black level of the output video signal of the A-D converter 52 is (00oooo
>, the “A〈b” output terminal is
When the level becomes "H", the up/down counter 58 enters the count-up mode, and the DC level of the video signal acts in the opposite direction to rise. Thus, in this case as well, the black level of the video signal is ti (000001). The setting value of the preset switch 59 is such that the value is D-A converted and added to the video input signal, and the black level when A-D converted becomes equal to or closest to the value of the preset switch 54. Set to . Preset switches 54 and 59
For example, it is convenient to use a 16m code switch.ALC control can also be performed by using an integrator instead of the counter 5g and the DA converter 60 and inputting its output to the adder 50. It is also possible to create a closed loop before reaching the A-D converter.

As described above, since the pIi addition circuit constitutes a closed loop circuit, the -I digital value corresponding to the analog ijI signal at a predetermined level can be converged to the data. The camera level can be controlled with an accuracy of 1 bit of the image digital value.

Further, by changing the data of the preset switches 54 and 51, the overall density of the print image can be arbitrarily determined.

(2) Automatic gain control circuit (400 circuit) FIG. 5 shows a block diagram of an embodiment of the AGCl path according to the present invention.

C is the analog video input terminal *bn(” = 0.1
゜2...) is the output terminal. 51 is an analog multiplier and has the relationship X-Y=Z (1). In other words, by varying the DC level Y, the amplitude X of the video signal can be controlled. As a result, the difference between the lowest level and the IjIk^ level (gain =
Contrast) Sleep while maintaining a constant level.

Note that components with the same number are the same in all drawings. The video signal quantized by the human error converter 52 is applied to a peak hold circuit 61. Details of the peak hold circuit 61 are shown in FIG.

In Figure 418, the fin (n = 0.1.2-) F
1 input signal, ω. is the peak held output signal. 207 is a latch circuit, and 208 is a magnitude comparator. When the two outputs Qm~Qr are holding a certain value, a new input is V.

Suppose it is applied to a horse. Both values have a magnitude of 1
The signal becomes "H" and the AND gate 209 is set.

On the other hand, the clock -T that passes through the AND gate 210 corresponding to the IIIiigl region further passes through the AND gate 209 and acts on the load terminal LD of the latch 207, so that the large new data is transferred to the latch 207.
is latched as the peak value. Since the nine latch 207 is cleared by the horizontal synchronizing signal φX, the latch data immediately before clearing is the peak value of the previous l line.

In this example, AGC is performed using the signal when the background (white background) of the document is taken.
A peak hold circuit was used. This is not necessary if a standard white document or the like is used.

In FIG. 5, the peak-held video signal is applied to the harmonic controller 62 and compared in magnitude with the data of the preset switch 63.
0). 64-digit up-down counter, 6
5 is a preset switch, 66 is a D-A converter,
The operation is the same as that in the ALC' circuit described above. That is, the preset switch 65 is a switch that initially determines the amplitude of the video signal;
3 stores the white level peak value of the video signal to be converged as a set value. In the previous reading scan, the white level peak hold value of the input video signal was set to the preset switch 63 (111110).

If the white level peak value of the video signal is larger than the set value of the preset switch 63, the gain of the multiplier 51 is increased by counting up the up/down counter 64 by 1 bit. is controlled in the downward direction. Further, when the white level peak value of a video number is equal to the setting value of the preset switch 63, the gain of the multiplier 51 is held at 1 as is.

Furthermore, the counter 64. Human GC control can also be performed by using an integrator that integrates the output of the comparator 62 instead of the DA converter 66 and inputting the output to the multiplier 51.

As described above, since the multiplication circuit constitutes a closed loop circuit, the image digital value obtained by converting the input analog tooth image signal of a predetermined level converges to the above data, and the human input analog vM signal is always stabilized. This makes it possible to amplify the signal.

Furthermore, by changing the data of the preset switch 63, the contrast of the print image can be arbitrarily determined.

1 Set of Limiter Circuits FIG. 6 shows a block diagram of an embodiment of the limiter circuit 9 (Figure m1) according to the present invention.

dn (n=0.1, 2...) is an input terminal, and en is an output terminal.

70 is a preset switch for magnitude combo fi, 'Ild high level (white) limit, 72-77
is 01 (circuit, 78 is the magnitude comparator, 7
Preset switch for 9u low level (black) set,
It is an 80-85F'1AND circuit.

For example, if the preset switch 71 is set to (111011), if the input signal becomes larger than that, the rA>BJ output terminal of the magnitude comparator 70 will be @
The output of Oa gates 72 to 77 becomes (1111
11). Furthermore, if the preset switch 79 is set to (000100), for example, and the input signal becomes smaller than that, the magnitude converter 78
The “λ〉B” output terminal becomes @L”, and the AND gate 8
The output of 0 to 85 is (0oooooo >).The input/output characteristics of this circuit are shown schematically in analog form in Figures 1 and 19. Shown in Figure 20 u) and (b). The waveform is an analog schematic. By providing this ivy (filter), not only the noise in the white background and black background parts of the 2. When emphasizing with an emphasizing circuit, the characteristic is that the waveform can be made easier to emphasize. Therefore, the limiter circuit described in t can be sufficiently effective by installing it before the contour emphasizing circuit.

As described above, this embodiment includes a conversion circuit that converts an analog image signal into a digital value having a plurality of bits, and a conversion circuit that converts an analog image signal into a digital value having a plurality of bits, and a second predetermined digital value that matches the digital value that is less than or equal to the first predetermined digital value. Since the digital value that is higher than the digital value is made to match the maximum digital value, the noise in the warped white background and black background part of -Run is removed, and the image with the noise removed in - is #! When a portion of a line drawing with a low double signal amplitude is emphasized by an edge enhancement circuit, it is possible to change the waveform to a waveform that is more easily emphasized. Furthermore, even if the limiter is either low level or high level, it is useless.

(4) Contour enhancement circuit (1) Figure 7 shows a circuit diagram of the contour enhancement circuit according to this example. This circuit is an edge enhancement circuit using a transpersal filter. By the way, it has been known that contour enhancement can be performed by subtracting the Laplacian from the original image signal f(x, y). The discrete value of Lagracia/ for a digital image is 2f(i,j)=△x2f(i,j)+△, Jf(i,
j)=r(i+t, j)+f(*-t, j)+r(
:, j+1)+f(i, j-1)-4f(!,
j) (3) is given by. If i is the main scanning direction and `` is the sub-scanning direction, the calculation coefficients of equation (3) can be diagrammed as shown in 812 (Figure 812). ``4'' is the number of threads for emphasis of the pixel of interest, ``-1''
is the number of surrounding emphasizing threads.

However, the sign is reversed, and this negative Lagradian may be added to the original image. In this case, the second-order partial differential coefficient in the main scanning direction and the second-order partial differential coefficient in the sub-scanning direction are set to be equal.

However, if this operator is used to emphasize the outline as it is, the resolution in the main scanning direction and the resolution in the sub-scanning direction will be different. Therefore, I read and reproduced the original by rotating it 90 times! A different soul image arises between the ii image and the one I read and reproduced without rotating. The inventors investigated the reason for this and found the following facts.

That is, immediately as shown in FIG. When reading an image using a dimensional CCD image sensor, main scanning is performed electrically using an internal register of the COD, but sub-scanning is performed mechanically, such as by moving the CCD along the document.

Therefore, the reason for the deterioration of the resolution of the bookmark me is that - in the scanning direction, only the resolution of the lens (MTF) is caused, but in the main scanning direction, it is due to the finite transfer efficiency of the CCD. It has been found that the resolution in the main scanning direction is inferior to that in the 1th11 scanning direction because of the addition of s'Fi deterioration.

For example, FIG. 21 shows a spatial frequency characteristic 220 including a lens and a CCD, and a spatial frequency characteristic 221 of a lens casing. However, the frequency characteristic of the lens is the MTF of the lens normalized by the frequency of the transfer lock φte of the CCD.

In this way, the spatial frequency characteristic in the main scanning direction is more than twice as bad as the spatial frequency characteristic in the sub-scanning direction.

Therefore, the partial differential coefficient in the -scanning direction is set to half the partial differential coefficient in the main scanning direction, as shown in FIG. 12 (b). O,1!12
The frequency characteristics of the video signal obtained by multiplying the operator in Figure (b) and the level of the image signal in the main scanning direction (by summing or subtracting the multiplication by 9), and the lens and CC in Figure 421
When multiplied by the frequency characteristic 220 including D, the second
It will look like Figure 2. Furthermore, if we multiply the frequency characteristic of the video signal obtained by folding the operator → in the sub-scanning direction in Figure 12 and the frequency characteristic 221 of the lens alone in Figure 21, we get the result as shown in Figure 23. Figure 22 shows a total frequency characteristic diagram in the main scanning direction, and Figure 23 shows a combined frequency characteristic diagram in the sub-scanning direction.Here, the main scanning direction of the operator in Figure 12 (b) When performing convolution into , the sub-scanning direction operators are ignored in the calculation.

When the input waveform is a cosine wave (2) (ωt), the frequency transfer function G(ω) in the main scanning direction is G(a+) = 3-2am(a+r) i
4). Similarly, the frequency transfer function H(ω) of the filter in the sub-scanning direction is H(ω) = 1.5 - width (ωr) +
5). Note that τ indicates a fixed delay time.

The circuit shown in FIG. 7 specifically performs this calculation. That is, if the partial differential coefficient in the main scanning direction is M, and the partial differential coefficient in the sub-scanning direction is N, then 2f(i, j)=MA)(" f(i, j)+Na
y” f(i, j)=ur(i-+-t, j)+u
t(t-t, j)+Nf(arc, j+1) ten Nf(i,
j-1)-2(M+N)t(i, j)
This is the calculation of the formula given by (6). Attention - When the coefficients of the calculation for an amateur are diagrammed, it becomes as shown in FIG. 13.

In Figure M7, 100 is a shift register that delays one line of video signals. 101 is also a shift register game.

llI with 102#-i latch! Delay the video signal for j elements. 103 to 106 are also latches.

107 and 109 are adders, and 108 and 110 are multipliers. Multiplier 108 and 11O#-j: Since the multiplier is 2, the concrete circuit can be constructed by simply replacing the data lines as shown in FIG.

δn is an input, and Pn is an output.

tii and 112 are subtracters, which can be realized, for example, by a two's complementer using an adder, as shown in FIG. Here, 150 is an adder, and 152 to 15 are inverters. In FIG. 7, with 113 and 115F1 multipliers,
For example, a parallel multiplier as shown in FIG. 11 is used. In FIG. 11, 160 to 164/Ii adders and 165 to 200 are AND circuits. In FIG. 7, 114 and 116
is a preset switch, and the switch 114ii sets the coefficient N, and the switch 116 sets the coefficient M, respectively. 1
17 is an adder, and 131 is a multiplier. For the multiplier 131, for example, the circuit shown in FIG. 11 is applied (described later). 1
18 is an adder, and 119 is a latch.

The operation will be explained with reference to FIG. First, the -scanning direction will be explained. Shift registers 100 and 101 each have l
Image data for 1247 main scans of the CCD delayed by a line is blown. Therefore, the outputs of latches 104-106 corresponding to the 1*element are shown, for example, by 1-C in FIG. 28, respectively. 2b - (a+c) of the output d processed by 1 link is obtained by calculating a - C. This is as shown in the figure. This result is used by the multiplier 113 to
Multiply by and change the height of the level of d.

An adder 117 adds and outputs the processed waveform in the paper main scanning direction. The processed waveform is further subjected to spatial frequency correction control, which will be described later, by multiplier 1314C. The result is further latched 102
is added to the output of to obtain e. Therefore, it is possible to obtain image data in which the link cuff is emphasized using the coefficient in the sub-scanning direction N.

A similar calculation is performed in the main scanning direction to obtain a link cuff output, and a multiplier 115 obtains a coefficient M glue/cuff output.

In this way, by calculating the differential coefficient in the main scanning direction and the differential coefficient in the sub-scanning direction using independent multipliers,
Optimal blur correction can be applied in both horizontal and vertical directions. Also, the S multiplier 131 is used to vary the sand coefficients M and N simultaneously while maintaining a proportional relationship, and the control signal for automatic equalization in the frequency domain is added here, but is limited to this only. Instead of stations, for example, instead of providing preset switches 114 and 116, they may be used as control lines. In that case, the differential coefficients M and N
If the relationship is twice (n is an integer), it is sufficient to simply replace the signal lines; otherwise, a multiplier (not shown) is inserted in either one for parallel control.

As described above, in this embodiment, the ll1iII signal is transmitted in the main scanning direction and ff1 with the pixel of interest of the image signal as the center.
l Since it has one contour enhancement path for contour enhancement in the scanning direction, it is possible to correct blur in each direction, and the differential coefficient M as a correction coefficient for contour enhancement in the main scanning direction of the contour enhancement circuit is used in the sub-scanning direction. Since the resolution of the reproduced image is set to be larger than the differential coefficient in the main scanning direction and the -scanning direction,
Unfortunately, there is no difference between the reproduced image that was read after rotating the manuscript 90 times and the one that was read without rotation, and the optimal blur correction can be applied in each direction. .

Furthermore, in this example, the image data processed by the limiter 9 is subjected to the cuff enhancement processing, so that an excellent effect is obtained that does not emphasize spot-like noise data or originally unnecessary spot data in the document background. be.

(5) Contour Emphasizing Circuit (2) K, which digitally constitutes a single-path contour emphasizing circuit, requires many components as shown in FIG. Furthermore, when the reading device uses a plurality of CCDs as shown in FIG. 2, the number of components becomes extremely large. In this case, by taking advantage of the features of the digital system, one contour emphasizing circuit can be used in a time-division manner as shown in FIG. The method will be specifically explained below.

Figure @8 is a block diagram of an embodiment of a contour emphasizing circuit capable of time-division operation according to the present invention. h and 1 are digital signals obtained by converting input image signals from parallel-driven CODs into 1 kA-D, and are alternately selected by the multiplexer 120. The frequency of the switching clock of the multiplexer 120 is 2h, which is twice the frequency of the video signal transfer lock φ.

The nine video signals that become one signal line are returned to two signal lines by the demultiplexer 128 after the above-mentioned filtering.

129 and 130 are latches, and j and k are their latch outputs. The demultiplexer 128 operates with a clock of 2φT, and the latches 129 and 130 operate with a clock of φi.

All components from multiplexer 120 to demultiplexer 12B are operated with a clock of 2φi.

The same functional elements as in FIG. 7 are given the same numbers.

Since the shift registers 100 and 101 receive two video signals alternately, they can only delay the video signal for the number line.Therefore, delay line shift registers 121 and 122 are added to each of the shift registers 100 and 101, respectively. Similarly, 123 to 127 are added latch circuits. The reason why there are two latches is because, for example, the data in the latch 123 and the output pixel data of the shift register 121 at a certain time are data from the COD of the same channel.

Since the other components are the same as those in FIG. 7, the number of components can be significantly reduced compared to the case where two systems of independent digital contour enhancement circuits are provided.

Fig. 8 explains the case where there are two video signals, and Fig. 9 shows the case where there are two video signals.
Even if there are three or more video signals, by adding shift registers and latches according to the number of video signals,
It can be configured in the same way.

As described above, the present embodiment includes a plurality of image sensors that read one document, and an output image 11i of the image sensor.
1! An analog-to-digital converter for converting into a 1-image signal, a multiplexer as a selection circuit for time-divisionally selecting the digital signal for each converter, and delaying the output digital signal of the selection circuit and comparing it with an adjacent digital signal. By doing this, the contour emphasizing circuit adjusts the contour to R* and has a demultiplexer as a separation circuit that separates the output of the contour emphasizing circuit for each converter, so it is sufficient to provide one contour emphasizing circuit. , the number of parts can be reduced and costs can be lowered.

(6) Automatic equalization in the frequency a region of the video signal (image signal) The MTk''221 of the lens shown in FIG. There is a large variation in
Frequency characteristics are not constant. Also MTF&C of lens 2)
Even if the beat/beat adjustment is slightly off, it will have a big impact. For example, if the amount of light is controlled by the aperture value of the lens, the MTli'ij becomes weaker as the aperture is opened. Therefore, it is difficult to deal with these changes in frequency characteristics by manual adjustment.

Therefore, in this embodiment, the video signal is automatically equalized in the m wave number domain.

In order to automatically equalize a video signal in the frequency domain, the frequency characteristics of the video signal in the main scanning direction are measured in advance.

When the contour strength in the main scanning direction is high and the order (number of multipliers) of the digital filter constituting the S circuit is second order, the coefficients can be determined if the frequency characteristics at any three points are known. However, the 13th
When the coefficients are symmetrical around the pixel of interest as shown in the figure, it is sufficient to measure the wave number characteristics at two points.

In order to measure the video signal including the optical system, a test chart as shown in FIG. 14 is prepared.

The lower half of this test chart is a pattern with a low spatial frequency, and the upper half is a pattern with a spatial frequency at or near the Nyquist limit.

The lower half may be completely black. By reading and scanning this test chart and sampling and holding the peak black level value VLF in the lower half area and the peak black level value VHF in the upper half area, the transmission characteristics of the video signal can be determined. After that, the difference between VLF and VHF is determined, and the differential coefficient (multiplier of multiplier 131) of the emphasis circuit (digital filter) shown in FIG. 7 is increased or decreased until the difference becomes zero, thereby automatically equalizing the video signal with respect to frequency. can be done.

FIG. 17 compares the peak value VLF and Vat and multiplier 1
31 is an example of a peak detector circuit for controlling 31. tn (n=0.1.2...) is a video signal input terminal, and uQ is an output terminal for differential coefficient control. 201
and 202 are peak hold circuits, both of which use the peak hold circuit shown in FIG. The peak hold circuit 201 peak-holds Vl and F. Vhv'i
A N d The ninth enable signal has a timing as shown in Figure 11115. The peak hold circuit 202 peak-holds the liver. VgygNFi is an enable signal for this purpose. Peak hold circuit 2
01 output vLνPEAK and peak hold circuit 20
2 output V liver Pj! When SAK is schematically illustrated in analog form, it becomes as shown in Fig. 15. The magnitudes are compared in the vLrP iif A K to VHy P h A Kij v Kunifx-toco7 parator 203.

204#'i Up-down counter horizontal synchronizing signal φX
count. A preset switch 205 is used to set the initial value of the differential coefficient for the multiplier 131.

The data of the preset switch 205 is the vertical synchronization signal [
It is loaded into the up/down counter 204 by COP Y J.

206 is a latch. The peak detector circuit 11 in FIG. 17 is placed at position 11 in FIG. Further, in FIGS. 7 and 8, the multiplier 1310 is controlled by placing it at the position 11. The input of the peak detector 11 in FIG. 7 may be the output V of the latch 119.

The multiplier 131 changes the weighting (width) of the addition output of the differential coefficient in the main scanning direction and the differential coefficient in the sub-scanning direction. In other words, the frequency characteristic in the sub-scanning direction is corrected by sliding it to the control value in the main-scanning direction. A blur factor that commonly appears in the main scanning direction and the sub-scanning direction, such as the M'r of the lens? For example, this method can provide a practically sufficient blur correction effect. Of course, in FIG. 7, two systems of peak detectors 11 may be provided, one for the main scanning direction and one for the sub-scanning direction, and the multipliers 113 and 115 may be controlled independently.

In that case, for measuring the frequency characteristics in the sub-scanning direction, the 14th
Measurements are made using a test chart (not shown) that is rotated 90 times from the test chart shown in the figure.

In the automatic equalization time chart of Fig. 15, k ae be C* LC... is added to the video signal input.
The code for ... is #! This corresponds to the black line "t be 't LC..." on the test chart in FIG.

@In the scan of the lth line, the input waveform is output as the video signal output as it is, but in the second line/th line, the amplitude VmF of the high spatial frequency video signal matches the amplitude @vLy of the low spatial frequency video signal, This shows that equalization has been completed.

The time chart of FIG. 16 shows the timing chart of automatic equalization when two CCD image pickup elements are used as shown in FIGS. 2 and 3. After equalization is completed, sequence (not shown)
Stop the counting operation of up/down counter 2G4 using the controller. In this way, the transmission characteristics of the video signal including the optical system can be automatically equalized in the frequency domain. Although the description has been made using a second-order equalization filter (digital filter), it is also possible to perform more precise equalization using a third-order or higher-order filter. In addition, as shown in Fig. 14, the test chart used was a pattern in which a pattern with a low spatial frequency and a pattern with a high spatial frequency were placed separately and placed f. If possible, patterns with low spatial frequencies and patterns with high spatial frequencies may be arranged in a mixed manner. The same applies to the sub-scanning direction. In this case, the bandpass filter may be analog or digital, but a digital filter is suitable for measuring the frequency characteristics in the sub-scanning direction.

According to the above configuration, it is possible to automatically equalize the transmission characteristics of the image signal including the optical system in the spatial frequency domain.

The output of the peak detector circuit can also be used in the next example. Example 1 calculates the peak detection output as % and the CCl) output as 2
An example in which the CCD output is used as a standard reference for a comparator that is input for value conversion or dither processing, Example 2 An example in which Fi peak detection output is displayed, and Example 3 in which the peak output is used instead of the output of preset switches 114 and 116. There are examples of this. That K
It is possible to detect that the level of the background color is lower, and it is possible to increase the level of the background color.

Next, we will explain the example of shading correction.
This will be explained in detail with reference to FIG.

Figure @24 is a block diagram of the shading correction device. 3 is a COD, and when a synchronizing signal φ is input, the charge accumulated in each cell is transferred to a transfer gate, and is transferred one bit at a time according to a transfer pulse φ to obtain an output. 4 is a DC amplifier for video amplification, and may include the aforementioned ALC circuit for stabilizing the black level. This is the aforementioned gain control circuit that controls the amplification gain of the output signal vc of the 6#i DC amplifier 4 in a desired and stable manner. 104 is a reference voltage generation circuit which generates n reference voltages V, V, . . . Vn using a potentiometer. Vi (j=1
．． 2...n) as a selection means. 106 is an integrator that integrates s vl and outputs an output v1. However, when the ihJ period signal φo is input, the reference voltage Vi changes to vmF'i and is reset to zero.

107u70 2 generation circuits, 108#-i, color circuit. The counter circuit 108 consists of 10 binary counters when the total number of bits of the cells of the CCD 1 is, for example, l 024 (=2") bits. The reference voltage selection signal axis uses the upper few bits of the binary counter. Synchronization When the signal φ is input, the binary counter becomes (o, o
oo, ooo, ooo). 9 is an output terminal of the video signal V, and lO is an input terminal of the same gate signal φ mouse. It is appropriate to select the number of reference voltage generators 104 in the range of n=2 and (k=2 to 4) from the viewpoint of accuracy of polygonal line approximation and cost. In other words, the n-point polygonal line approximation uses bits in the upper part of the counter 108.

For example, to perform 4-point polygonal line approximation, count 1 of counter 8.
The highest two bits may be used as the reference voltage selection signal φ. It is assumed that the gain G of the gain control circuit wI6 is a linear function of the integral equation. That is, G = KV,
(1) However, K is a constant. Therefore the video output v
0 can be expressed in the following equation using the CCD output vc.

vo = K Vs Vc
(21Here, considering the case where the CCD output vc includes shading, if the shading characteristic is ξ and the actual uIi moral species information (), then the COD output vc is the formula vc = ξ・vc (3) There is no loss of generality even if the integral output v Hatake is represented by the inverse characteristic of shading, that is, V, = 1/ξ
If you give it as (4), you can remove the shading. That is, v,=Kv,-vc=Kl/ξ·ξ-We=Kvc(5), and the shading term in the video output V disappears.

In reality, it is not realistic to create a perfect inverse characteristic of shading, 1/ξ, so the polygonal line approximation of 4 to 16 points does not change the difference by 1 in practice.

Next, a specific example will be shown in which a four-point polygonal line approximation (n=4) is performed.

FIG. 2 shows a time chart in the case of VC four-point polygonal line approximation.

As an example, the number of pixels per line of the CCD 1 is 1024 bits.

The count value of the counter 108 is expressed in binary as CNT, and the upper two bits of CNT are used as a reference voltage selection signal -,
The decimal representation is also shown. If you do it like this,
Since the 1024-bit COD cell is equally divided into four, φM is applied to the multiplexer 5 to select the NI-order reference voltage V, .about.v4. COD scan Jung time 1J
tT, counter 10 at the true fall of Tonghu Xinchi II
8 is reset and scanning begins.

Let the eruption constant of the integrator 106 be n/l.

φ store +1 Now, any time t (however - 145 dings).

n n φM1jlO base number expression) is obtained.

9 For example, −, = 2, i.e., −1) 1≧−! At the time of 4, Vl= Σ v4 + Yl (t − t )1=1
! ' ” vo +vt +'Is (t-”)
(7)! For example, when t=y, do the same thing as Fi, and get V, =
v, -1-V, +v, +v,
(81. Therefore, an integral output vs as shown by the broken line in FIG. 2 is obtained.

Here again, the condition for the polygonal line approximation representative of equation (4) is to set the reference voltage V, ``''n, so that each corner point of the v factor coincides with l/ξ.■8 Since both N
nru. Therefore, by substituting equation (9) into equation (4) from equation (6), and then determining each reference voltage according to equation 01, shading can be corrected.

Figure 2 shows the image reading element (Fairchild C'D)
This is a block diagram of a CCD linear sensor.

1 is an exposure part that accumulates charges according to the light reception level kllc by exposure, b is a transfer part using a shift register to serially transfer the charges, C is a generation part that generates clock pulses for transfer, and d is a part that generates clock pulses for transfer. This is a circuit that sequentially numbers and holds transferred data.The process of data transfer will be explained with reference to the CCD signal timing diagram in Figure 11!3.

@2 The light accumulated in the exposure section of FIG. 1 for a certain period of time is simultaneously transferred to each cell of the exposure section of FIG. 1 to the shift register of FIG. 1 by the pulse shown in FIG. 3-X. FIG. 3 φi is the transfer lock of shift register b, and the transferred information ti
The signals are sequentially sent to the hold circuit d in FIG. 2 and output. In FIG. 3, l is the reset pulse of the hold circuit d.

3 is an image signal, and the image signal includes, in addition to the actual image signal, a reference black level signal BL4F and a reference white level signal WT4F. This reference signal is the pulse on the right side of the read signal MDI in FIG. 3, and is output by the CCO itself. Figure 3 Vlall...Ilevel (gos
) is an output/doofscan signal output every time a scan is completed. After 1217 minutes of transfer scan, the hold circuit d outputs a low level HL-RF signal, and then the read m
No. VDa is output, and then BL-kLF is output again.

Finally, the high level WT-F of the reference white signal is output as ■Japanese text. At the same time, the VgOl boat detects the high level and outputs an end signal '8oS for 1217 minutes.

Note that the output Vout is input to the Video input port of the control circuit shown in FIG.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the automatic equalization amount of a video signal in one wave number domain, Figure 2 is a block diagram of an embodiment using two CCDs, and Figure 3 is a block diagram of an example in which the contour enhancement circuit is used in a time-division manner. Figure 4 is an automatic level control circuit diagram, Figure 8g5 is an automatic gain control circuit diagram, Figure 6 is a limiter circuit diagram, Volume 7 is a contour enhancement circuit diagram for correcting blur, Figure 8 is a contour enhancement circuit diagram for blur correction for time-sharing use, Figure 9 is a subtracter circuit diagram, Figure 1θ is a multiplier circuit diagram, Figure 11 is a parallel multiplier - node circuit diagram, Figure 12 is an em la The figure shows the Lagradian, the first
Figure 4 is a plan view of a test chart, Figure 8815 is a diagram showing one example of an automatic equalization time chart, Figure 16 is a diagram showing another example of an automatic equalization time chart, Figure 17 is a peak detector circuit diagram, Figure 18 is a peak hold circuit diagram, Figure 19 is an input/output characteristic diagram of the limiter circuit, Stripe 20 is a diagram showing an example of the input and output waveforms of the limiter circuit, Figure 821 is a frequency characteristic diagram of the lens and CCD, #E22
The figure is a frequency characteristic diagram after equalization in the main scanning direction, and FIG. 23 is a frequency characteristic diagram after equalization in one scanning direction. FIG. 24 is a block diagram of an example of a shading correction circuit, I
Fig. jI25 is a diagram showing a time chart of 4-point polygonal line approximation. FIG. 26 is a plan view of C'CD, and FIG. 27 is a time chart of FIG. 26. Figure 28 is the 11il embedded waveform diagram of Figure 7, where 5 is 000, 5 is MULG, and 6 is AG.
It is O. ・ 1, Mu (4th (2M -41 direction Shun-t N・θ5 1 main Shigekatacho A-2 (M + ~) □ Input (A) Zr W Leopard (B) Z Yun Luck E

Claims (1)

[Scope of Claims] Anag image signal generating means, means for converting the analog image notes from the signal relaxing means into a digital image signal, means for comparing the image signal with a predetermined reference value, and a beater for the digital image signal. Detecting move R1 The above comparison move*. Image processing device 0 having means for outputting an image correction signal to the detection means