+

JPS58124266A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS58124266A
JPS58124266A JP57008151A JP815182A JPS58124266A JP S58124266 A JPS58124266 A JP S58124266A JP 57008151 A JP57008151 A JP 57008151A JP 815182 A JP815182 A JP 815182A JP S58124266 A JPS58124266 A JP S58124266A
Authority
JP
Japan
Prior art keywords
circuit
defect
blocks
probability
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57008151A
Other languages
Japanese (ja)
Inventor
Tojiro Takegawa
武川 藤次郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57008151A priority Critical patent/JPS58124266A/en
Publication of JPS58124266A publication Critical patent/JPS58124266A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/74Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Microcomputers (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To make it possible to utilize the circuit even though it has defects without discarding it, by preparing a plurality of circuit blocks with the same function comprising high density active element regions which tend to include serious defects, wiring the selected good circuit so as to contribute the operation, thereby improving the circuit design and the yield rate. CONSTITUTION:In a microcomputer chip in an example in the figure, two ROMs and two ALUs having the same functions, respectively, are prepared. In this constitution, e.g. in the ROMs (A) and (B), the probability of the even either of (A) or (B) does not have the defect is twice the probability of the event the ROM (A) does not have the defect. Then a plurality of the blocks (e.g. two), which are formed by the high density active elements and have a small occupying area, and whose probability of the event of including the defect is low, are intentionally prepared. A selecting circuit (e.g. a fuse circuit wherein polysilicon is used) is provided for each block. The characteristics of the blocks are checked by the selecting circuits, and the block which does not have the defect is selected. Then the yield rate is improved by twice or more by only increasing a pellet area by 1.5 times.

Description

【発明の詳細な説明】 本発明は半導体集積回路に関し、特に一チップ上におい
である機能を有する回路ブロックを配線で接続して構成
した集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly to an integrated circuit configured by connecting circuit blocks having a certain function on one chip with wiring.

従来、かかる集積回路の代表として第1図にブロック図
を示すマイクロ・コンピュータがある。
Conventionally, there is a microcomputer whose block diagram is shown in FIG. 1 as a typical example of such an integrated circuit.

このマイクロ・コンビエータは、プログラムメモリとし
てのROMIと、そのアドレス指定回路としてのプログ
ラム・カウンタ2、データメモリとしてのROM3とレ
ジスタ4やALU 5 、 Ilo 6等がデータ・バ
ス7を介して接続されている。このうち、能動素子で構
成されるROM、RAM、ALU。
This micro combinator has a ROMI as a program memory, a program counter 2 as its addressing circuit, a ROM 3 as a data memory, and a register 4, ALU 5, Ilo 6, etc. connected via a data bus 7. There is. Among these, ROM, RAM, and ALU are composed of active elements.

工10.プログラム・カウンタおよびレジスタ等の能動
領域と能動素子を含まないデータ・バス等の配線領域と
を比較すると、配線領域の占有面積がペレット面積の半
分以上を占めるという特徴がある。又、マイクロ・コン
ピュータを構成する各ブロックが欠陥を含まない確率は
集積密度の関数となり、同一面積で比較すると P(ROM、RAM)<P(ランダム回路)くP(配線
)となる。ここでランダム回路にはALU、Iρ。
Engineering 10. When comparing active areas such as program counters and registers with wiring areas such as data buses that do not include active elements, there is a characteristic that the area occupied by the wiring areas occupies more than half of the pellet area. Furthermore, the probability that each block constituting a microcomputer does not contain defects is a function of the integration density, and when comparing the same area, P (ROM, RAM) < P (random circuit) x P (wiring). Here, the random circuit includes an ALU and Iρ.

プログラム・カウンタ、レジスタ等を含めている。Contains program counter, registers, etc.

一般にブロックが致命的な欠陥金倉まない確率はNA P(NA)=e    で表わされる。In general, the probability that a block does not have a fatal defect is NA It is expressed as P(NA)=e.

ここで、Nは単位面積当りの致命的な欠陥の数であり、
AFiブpツクの占有面積である。
Here, N is the number of fatal defects per unit area,
This is the area occupied by the AFi book.

第2図にマイクロ・コンピュータを構成スるブロックの
欠陥を含まない確率を求めた。マイクロコンピュータが
欠陥を含まない確率P (RUM nFtAM nラン
ダムn配線)は各ブロックの占有面積が太きければ極め
て小さく、良品はほとんどとれない。そこで欠陥を含ま
ない確率を高める必要が生じる。
Figure 2 shows the probability that the blocks constituting the microcomputer are free of defects. The probability P (RUM nFtAM n random n wiring) that a microcomputer does not contain a defect is extremely small if the area occupied by each block is large, and it is almost impossible to obtain a good product. Therefore, it is necessary to increase the probability of not including defects.

一般にLSIやVLSIでは配線領域の占有面積が大部
分であり、能動素子で構成されるブロックの占有面積は
小さい。さらにR,OM、RAM等の高密度のブロック
とランダム回路の様に密度の低いブロックでは単位面積
当りの致命的欠陥数も違っており、ROM、RAMの方
が欠陥密度が極めて高い。このようにベレット面積は配
線領域が支配的であるため、チップ自体が歩留りよく製
造できるか否かはROM、RAMおよびランダム回路の
一部分で決まる事になる。
Generally, in an LSI or VLSI, the wiring area occupies most of the area, and the area occupied by a block composed of active elements is small. Furthermore, the number of fatal defects per unit area is different between high-density blocks such as R, OM, and RAM and low-density blocks such as random circuits, and ROM and RAM have extremely high defect density. As described above, since the bullet area is dominated by the wiring area, whether or not the chip itself can be manufactured with good yield is determined by the ROM, RAM, and random circuits.

このような観点に立脚して従来の集積回路をみると、チ
ップ上に形成される各回路ブロックは心安最小限、即ち
各1個ずつしか設けられていない。
Looking at conventional integrated circuits from this perspective, the number of circuit blocks formed on a chip is the safe minimum, that is, only one each.

これは半導体技術の進歩に伴ってパターンの微細化が可
能となり、lチップ上にできる限り多種類の回路や大容
量のメモIJ ’に設けて機能拡大金計ることに専念し
た結果といえる。このため、製造歩留りが悪く欠陥のあ
る製品は廃棄処分とせざるを得なかった。
This can be said to be the result of advances in semiconductor technology that have made it possible to miniaturize patterns, and to expand functionality by providing as many types of circuits and large-capacity memory IJ's as possible on a single chip. For this reason, defective products with poor manufacturing yields had no choice but to be disposed of.

本発明の目的は回路設計に改良を加えて歩留りを改善し
、かつ欠陥があっても廃棄することなく利用可能とした
半導体集積口M’に提供することを目的とする。
An object of the present invention is to improve the yield by improving the circuit design, and to provide a semiconductor integrated circuit M' that can be used without being discarded even if there are defects.

本発明は前記した観点に基づいて、致命的な欠陥全含み
やすい高密度能動素子細織からなる同一機能の回路ブロ
ックを複数個用意し、これらの特性検査を行なうことに
よって選ばれた良品回路ブロックを配線に接続して動作
に寄与させるようにしたことを特徴とする。
Based on the above-mentioned viewpoint, the present invention prepares a plurality of circuit blocks with the same function made of high-density active element fabrics that are likely to contain all fatal defects, and selects a good circuit block by conducting a characteristic test on these circuit blocks. It is characterized in that it is connected to the wiring to contribute to the operation.

以下に図面を参照して本発明の一実施例を説明する。第
3図はその実施例のブロック図で、マイクロコンピュー
タチップを例にとったものである。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of this embodiment, taking a microcomputer chip as an example.

ここでは同一機能をもったLOOMとALUとを夫々2
個用意している。こうすることによって、例えばROM
のと■において、いずれか一方が欠陥を含まない確率は
、ROM■が欠陥を含まない確率の2倍以上となる。従
って、高密度能動素子で形成され、占有面積が小さく、
欠陥を含まない確率が低いブロックを、敢えて複数個(
例えば2個)用意し、各ブロックに対してその選択回路
(例えばポリシリコンを用いたヒユーズ回路)を設け、
これを用いて特性検査後欠陥のないブロックを選ぶよう
にすれば、第2図に示す例では、ベレット面積を1.5
倍にするだけで歩留りを2倍以上にする事ができる。
Here, we will introduce two LOOMs and two ALUs each with the same function.
We have pieces available. By doing this, for example, the ROM
The probability that either one of (1) and (2) does not contain a defect is more than twice the probability that ROM (2) does not contain a defect. Therefore, it is formed with high-density active elements, occupies a small area,
We deliberately selected multiple blocks with a low probability of containing no defects (
For example, two blocks) are prepared, and a selection circuit (for example, a fuse circuit using polysilicon) is provided for each block.
If this is used to select blocks with no defects after characteristic inspection, the pellet area can be reduced to 1.5 in the example shown in Figure 2.
You can more than double the yield by simply doubling it.

第4図にポリシリコンヒユーズを用いてI’(OMをデ
ータバスから切り離す回路例を示す。ここでROM■に
欠陥がある場合、電源端子VDと書き込み端子Wの間に
15V程度の′屯田を回加し、ポリシリコンヒユーズ8
に数十mAの電流を流してこれを切断する。このように
して書き込み端子に接続してい尋電源を切り離した後、
電源端子VDに外部を源を接続すると、書き込み端子W
は接地電位となり、ROMへのt源供給スイッチPlは
非導通とがる。又、P’1. + P3 r口2.n3
から構成されるROMデータバス出力バッファは非導通
とな5− リ、P4 + ’4 + ’5から構成されるROM人
力バッファも非導通となるので、ROM■を構成する要
素は動作状態において電力を何等消費することなく、デ
ータバスより電気的に切離す事ができる。
Figure 4 shows an example of a circuit that uses a polysilicon fuse to separate I' (OM) from the data bus. If ROM ■ is defective, connect a voltage of about 15 V between the power supply terminal VD and the write terminal W. Polysilicon fuse 8
A current of several tens of mA is applied to the wire to cut it. After connecting to the write terminal in this way and disconnecting the power supply,
When an external source is connected to the power supply terminal VD, the write terminal W
becomes the ground potential, and the t source supply switch Pl to the ROM becomes non-conductive. Also, P'1. + P3 r mouth 2. n3
The ROM data bus output buffer consisting of P4 + '4 + '5 is non-conductive, and the ROM manual buffer consisting of P4 + '4 + '5 is also non-conductive, so the elements constituting the ROM It can be electrically separated from the data bus without consuming anything.

尚、この例で示したようにALUとROMとの両方に対
して本発明を適用する以外、そのうちいずれか一方(望
ましくはRO,M )のみに適用するようにしてもよい
。又、ポリシリコンヒユーズのかわりに、トランジスタ
スイッチやダイオードスイッチを用いてもよい。
In addition to applying the present invention to both the ALU and the ROM as shown in this example, the present invention may also be applied to only one of them (preferably RO or M). Further, a transistor switch or a diode switch may be used instead of the polysilicon fuse.

以上はデータ・バスに各種機能ブロックが接続されてい
るマイクロコンピュータを用いて説明したが、データ・
バスが無い集積回路(特にVLSI)においても同一機
能のブロックを2つ以上用意し、欠陥の無い機能ブロッ
クを選び出す事によりVLSIの歩留りを向上できる。
The above was explained using a microcomputer with various functional blocks connected to the data bus.
Even in integrated circuits without buses (particularly VLSIs), the yield of VLSIs can be improved by preparing two or more blocks with the same function and selecting functional blocks without defects.

【図面の簡単な説明】 第1図はデータ・バスに各種機能ブロックを接続し構成
した従来のマイクロ・コンピュータのプ6− ロック図、第2には第1図に示した各種機能ブロックの
占有面積と欠陥を含まない確率との特性図、第3図は欠
陥を含まない確率が低い機能ブロックを同一ブロックで
2つ以上用意し、ポリシリコンヒユーズで欠陥の無い方
を選ぶようにした、本発明の一実施例におけるVLSI
マイクロ・コンピュータのブロック図、第4図は本実施
例のスイッチ部分の回路図である。 ■・・・・・・ROM、2・・・・・・プログラムカウ
ンタ、3・・・・・・RAM、4・・・・・・レジスタ
、5・・・・・ALU、6・・−・・・Ilo、7・・
・・・・データバス、8・・・・・・ポリシリコンヒユ
ーズ。 7− 第 1 区 ランダム   どAFI   F?0/’I   デー
ク回路              ハースY5肩面積 第 ? 図 第 3 区
[Brief explanation of the drawings] Figure 1 is a block diagram of a conventional microcomputer configured by connecting various functional blocks to a data bus, and the second diagram shows the occupation of the various functional blocks shown in Figure 1. Figure 3 shows a characteristic diagram of the area and the probability of not containing a defect.This book shows a method in which two or more functional blocks with a low probability of not containing defects are prepared in the same block, and the one with no defects is selected using polysilicon fuses. VLSI in one embodiment of the invention
FIG. 4, a block diagram of the microcomputer, is a circuit diagram of the switch portion of this embodiment. ■...ROM, 2...Program counter, 3...RAM, 4...Register, 5...ALU, 6...・・Ilo, 7・・
...Data bus, 8...Polysilicon fuse. 7- Ward 1 Random Which AFI F? 0/'I Dake circuit Haas Y5 shoulder area ? Figure 3rd ward

Claims (1)

【特許請求の範囲】[Claims] 同一基板上に同一機能をもった回路ブロックを複数個有
し、このうち欠陥の無い方の回路ブロックを選択する手
段を備えたことを特徴とする半導体集積回路。
1. A semiconductor integrated circuit comprising a plurality of circuit blocks having the same function on the same substrate, and comprising means for selecting a defect-free circuit block from among the circuit blocks.
JP57008151A 1982-01-21 1982-01-21 Semiconductor integrated circuit Pending JPS58124266A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57008151A JPS58124266A (en) 1982-01-21 1982-01-21 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57008151A JPS58124266A (en) 1982-01-21 1982-01-21 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS58124266A true JPS58124266A (en) 1983-07-23

Family

ID=11685310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57008151A Pending JPS58124266A (en) 1982-01-21 1982-01-21 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS58124266A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6286743A (en) * 1985-10-02 1987-04-21 インタ−ナシヨナル・スタンダ−ド・エレクトリツク・コ−ポレイシヨン Array reshaping apparatus and method suitable for use in large scale integrated circuits
US6751138B2 (en) 1990-07-12 2004-06-15 Renesas Technology Corporation Semiconductor integrated circuit device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6286743A (en) * 1985-10-02 1987-04-21 インタ−ナシヨナル・スタンダ−ド・エレクトリツク・コ−ポレイシヨン Array reshaping apparatus and method suitable for use in large scale integrated circuits
US6751138B2 (en) 1990-07-12 2004-06-15 Renesas Technology Corporation Semiconductor integrated circuit device
US7002830B2 (en) 1990-07-12 2006-02-21 Renesas Technology Corp. Semiconductor integrated circuit device
US7212425B2 (en) 1990-07-12 2007-05-01 Renesas Technology Corp. Semiconductor integrated circuit device
US7336535B2 (en) 1990-07-12 2008-02-26 Renesas Technology Corp. Semiconductor integrated circuit device

Similar Documents

Publication Publication Date Title
US5675545A (en) Method of forming a database that defines an integrated circuit memory with built in test circuitry
KR100283030B1 (en) Layout structure of semiconductor device
US5285082A (en) Integrated test circuits having pads provided along scribe lines
KR900004888B1 (en) Integrated circuit system
EP0167365B1 (en) Standard cell lsis
US5539878A (en) Parallel testing of CPU cache and instruction units
KR970008363B1 (en) Trimming circuit
US6153450A (en) Method of utilizing fuses to select alternative modules in a semiconductor device
EP0454134A2 (en) Semiconductor device
US7131033B1 (en) Substrate configurable JTAG ID scheme
JPS58124266A (en) Semiconductor integrated circuit
EP0855742A1 (en) Semiconductor integrated circuit device produced from master slice and having operation mode easily changeable after selection on master slice
KR0134854B1 (en) Method and apparatus for designing semiconductor device
JP2003518773A (en) Integrated circuit with high reliability, metal programmable logic circuit
JPH1145600A (en) Semiconductor memory device with simplified complex data test circuit
JPH03180047A (en) Integrated circuit and manufacture thereof
US6406980B1 (en) Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets
JPS6158966B2 (en)
JPH0158662B2 (en)
US11721585B2 (en) Method for fabricating semiconductor memory and the semiconductor memory
JPH09506481A (en) Universal connection matrix array
JPH0529546A (en) Semiconductor integrated circuit
JPH0465859A (en) Wafer-scale integrated circuit and signal propagation path forming method in the circuit
JPH1082835A (en) Semiconductor device
KR100532391B1 (en) Test control circuit having minimum number of pad
点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载