JPS57111621A - Bus monitoring system - Google Patents
Bus monitoring systemInfo
- Publication number
- JPS57111621A JPS57111621A JP55188237A JP18823780A JPS57111621A JP S57111621 A JPS57111621 A JP S57111621A JP 55188237 A JP55188237 A JP 55188237A JP 18823780 A JP18823780 A JP 18823780A JP S57111621 A JPS57111621 A JP S57111621A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- faulty
- detected
- abnormality
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
- Debugging And Monitoring (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To deal with the generation of faults in the input devices connected to a bus effectively and improve the reliability of a communication system by disconnecting the respective input-output devices simultaneously from the bus in a monitoring circuit, disconnecting the abnormal input-output device and reconnecting others when abnormality is detected. CONSTITUTION:Each I/O connected via a driver D and a receiver R to a bus B. A monitoring circuit SVC checks the signal tranmitted to the bus, and when abnormality is detected, it sets the own flip-flop and transmits a driver simultaneous disconnection signal S1. This signal disconnects all the I/Os and the bus B is made normal. A processor MPR starts a fault processing program. The faulty I/O is most probably the I/O communicating at that time and therefore that I/O is disconnected and the other I/Os are reconnected. If this makes the bus normal, the faulty I/O is the above-mentioned I/O and this is displayed. If the abnormality is detected by the reconnection of the bus, this indicates that the other I/O is faulty, hence another I/O is set and the same processing is executed until the faulty I/O is detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55188237A JPS6037504B2 (en) | 1980-12-27 | 1980-12-27 | Bus monitoring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55188237A JPS6037504B2 (en) | 1980-12-27 | 1980-12-27 | Bus monitoring method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57111621A true JPS57111621A (en) | 1982-07-12 |
| JPS6037504B2 JPS6037504B2 (en) | 1985-08-27 |
Family
ID=16220184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55188237A Expired JPS6037504B2 (en) | 1980-12-27 | 1980-12-27 | Bus monitoring method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037504B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08307437A (en) * | 1995-04-28 | 1996-11-22 | Nec Corp | Faulty node elimination method and device for multi-branch bus type system |
| US6952746B2 (en) | 2001-06-14 | 2005-10-04 | International Business Machines Corporation | Method and system for system performance optimization via heuristically optimized buses |
-
1980
- 1980-12-27 JP JP55188237A patent/JPS6037504B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08307437A (en) * | 1995-04-28 | 1996-11-22 | Nec Corp | Faulty node elimination method and device for multi-branch bus type system |
| US6952746B2 (en) | 2001-06-14 | 2005-10-04 | International Business Machines Corporation | Method and system for system performance optimization via heuristically optimized buses |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6037504B2 (en) | 1985-08-27 |
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