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JPS55153181A - Counter circuit - Google Patents

Counter circuit

Info

Publication number
JPS55153181A
JPS55153181A JP5948679A JP5948679A JPS55153181A JP S55153181 A JPS55153181 A JP S55153181A JP 5948679 A JP5948679 A JP 5948679A JP 5948679 A JP5948679 A JP 5948679A JP S55153181 A JPS55153181 A JP S55153181A
Authority
JP
Japan
Prior art keywords
display
circuit
certain time
stop mode
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5948679A
Other languages
Japanese (ja)
Other versions
JPS6057147B2 (en
Inventor
Masanobu Sato
Kazuyasu Motoyama
Kenji Furuta
Katsumi Kanayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP5948679A priority Critical patent/JPS6057147B2/en
Publication of JPS55153181A publication Critical patent/JPS55153181A/en
Publication of JPS6057147B2 publication Critical patent/JPS6057147B2/en
Expired legal-status Critical Current

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Abstract

PURPOSE: To eliminate fruitless electric power consumption while making recording, etc., convenience by holding the display of count contents for a certain time by driving a display circuit for the certain time even when a tape recorder is placed in stop mode.
CONSTITUTION: The output of up/down counter 13 is displayed by display element 28 by way of latch circuit 27 and decoder-driver 26. When an operation mode change-over switch is switched to the stop mode, main switch 21 is switched off and the output of OR gate 17 falls. Synchronizing with this fall, trigger circuit 18 and monostable multivibrator 19 are driven to output pulses K of constant time width. In the continuation of pulses K, constant-voltage circuit 24 and boasting circuit 25 keep on driving decoder-driver 26 to hold the display of count contents for a certain time. Consequently, the display part is being driven continuously even in stop mode. Consequently, the electric power consumption of the display part can be reduced in comparison with that of a conventional way.
COPYRIGHT: (C)1980,JPO&Japio
JP5948679A 1979-05-15 1979-05-15 counter circuit Expired JPS6057147B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5948679A JPS6057147B2 (en) 1979-05-15 1979-05-15 counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5948679A JPS6057147B2 (en) 1979-05-15 1979-05-15 counter circuit

Publications (2)

Publication Number Publication Date
JPS55153181A true JPS55153181A (en) 1980-11-28
JPS6057147B2 JPS6057147B2 (en) 1985-12-13

Family

ID=13114671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5948679A Expired JPS6057147B2 (en) 1979-05-15 1979-05-15 counter circuit

Country Status (1)

Country Link
JP (1) JPS6057147B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6339284U (en) * 1986-08-30 1988-03-14

Also Published As

Publication number Publication date
JPS6057147B2 (en) 1985-12-13

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