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JPS54151339A - Exclusive logical sum array - Google Patents

Exclusive logical sum array

Info

Publication number
JPS54151339A
JPS54151339A JP6026278A JP6026278A JPS54151339A JP S54151339 A JPS54151339 A JP S54151339A JP 6026278 A JP6026278 A JP 6026278A JP 6026278 A JP6026278 A JP 6026278A JP S54151339 A JPS54151339 A JP S54151339A
Authority
JP
Japan
Prior art keywords
exclusive logical
logical sum
output
binary signal
take
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6026278A
Other languages
Japanese (ja)
Inventor
Takeo Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6026278A priority Critical patent/JPS54151339A/en
Priority to US06/015,841 priority patent/US4249246A/en
Publication of JPS54151339A publication Critical patent/JPS54151339A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To easily realize the high speed operation, by producing the exclusive logical sum for binary signal without duplicating the output terminals of the logical product array, obtaining exclusive logical sum similarly from the output group and outputting this repetitively. CONSTITUTION:The logical product array 1 provides a plurality of output terminals, the binary signal outputted to each output terminal with arbitrary programming, and the exclusive logical sum array 2 can take the exclusive logical sum with the output signals at the output terminals outputting arbitrarily binary signal as a program with arbitrary combination. The exclusive logical sums 111, 112, 114 take respectively input signal of 150, 21, 22, 24, 25, 26, the exlusive logical sums 113, 115 take input of 111, 112, and the exclusive logical sum 116 takes the output of 113, 115 as input and picked up from the output terminal 31. Thus, the area of Al wiring is provided transversally for several lines to reduce the number of steps of delay and to easily realize high speed operation.
JP6026278A 1978-02-27 1978-05-19 Exclusive logical sum array Pending JPS54151339A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP6026278A JPS54151339A (en) 1978-05-19 1978-05-19 Exclusive logical sum array
US06/015,841 US4249246A (en) 1978-02-27 1979-02-27 Programmable logic array for generating EOR sums of input signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6026278A JPS54151339A (en) 1978-05-19 1978-05-19 Exclusive logical sum array

Publications (1)

Publication Number Publication Date
JPS54151339A true JPS54151339A (en) 1979-11-28

Family

ID=13137054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6026278A Pending JPS54151339A (en) 1978-02-27 1978-05-19 Exclusive logical sum array

Country Status (1)

Country Link
JP (1) JPS54151339A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100547885B1 (en) * 1998-07-10 2006-04-20 삼성전자주식회사 Complex signal sensing circuit of communication terminal and its processing method
JP2011146052A (en) * 2001-11-30 2011-07-28 Analog Devices Inc Galois field multiply/multiply-add/multiply-accumulate operation device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100547885B1 (en) * 1998-07-10 2006-04-20 삼성전자주식회사 Complex signal sensing circuit of communication terminal and its processing method
JP2011146052A (en) * 2001-11-30 2011-07-28 Analog Devices Inc Galois field multiply/multiply-add/multiply-accumulate operation device

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