JPH10289305A - Image processing apparatus and image processing method - Google Patents

Abstract

(57) [Summary] To provide an image processing device capable of comparing and verifying two images at high speed. A first processor that divides an image in which a graphic element is represented by coordinates into a pixel area having a predetermined side length and intermediately processes the image data represented by coordinates to create intermediate data. , And a plurality of arithmetic units 107-0
To 107-7 and a control unit 106 for controlling the operation of the arithmetic unit
A SIMD-type processor 181 having
Using the intermediate data created by the processor 100, the coordinate-represented image data is converted into a pixel value representation, and an image processing apparatus is configured by a subsystem 180 that compares the first image and the second image.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for comparing two images and quickly verifying whether they are the same image.

[0002]

2. Description of the Related Art As a conventional technique of this kind, for example, there is a technique disclosed in a literature (Mitsubishi Electric Technical Report, vol. 68, No. 3, 1994, pp. 86-89). According to this conventional technique, data for producing a semiconductor mask is compared with layout data designed by a designer to detect a difference, and FIG. 20 shows an image processing method in such a conventional image processing apparatus. .
As shown in the drawing, a process of inputting mask data for creating a semiconductor mask in a coordinate expression and design data designed by a designer, and converting the input image data in the coordinate expression into a pixel value expression (S8-1). Execute That is, each of the input image data is divided into pixel regions having a predetermined side length, and each image data represented by coordinates is developed into a bitmap of 1, 0 according to the occupation ratio of the pattern in the pixel. Thus, the image data is converted into a pixel value expression. After executing the processing (S8-1), the processing of comparing and collating the image of the pixel value expression (S8-
2), and outputs the position of the different part (S8-
3). In the conventional technology, these processes are performed by one computer of a sequential processing type, or a plurality of computers are prepared, and one computer is assigned to each image data.
The bitmap development processing is performed in parallel for each image data, and after the development processing is completed, the collation processing of each image data is performed.

[0003]

As described above, in the prior art, the bitmap expansion processing and the collation processing of each image data are performed by using a sequential processing type computer. There is a problem in that the processing time increases in proportion to the number of graphics as the number increases. Also, 2
Although it was possible to perform the bitmap development processing of two images in parallel, the bitmap development processing itself of each image is sequentially processed, and the number of graphics included in the image increases as described above. Accordingly, the processing time increases in proportion to the number of figures, and the data parallelism of the image cannot be fully utilized.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and can perform parallel processing even when converting image data in a coordinate expression into a pixel value expression.
It is an object of the present invention to obtain an image processing apparatus capable of comparing and verifying two images.

[0005]

According to a first aspect of the present invention, there is provided an image processing apparatus which divides an image in which a graphic element is represented by coordinates into a pixel area having a predetermined side length, and A first processor that intermediately processes the expressed image data to create intermediate data, and a SIMD type processor that has a plurality of arithmetic units and a control unit that controls the arithmetic operation of the arithmetic units. It is provided with a subsystem that converts the coordinate-represented image data into a pixel value representation using the intermediate data thus obtained, and compares the first image with the second image.

According to a second aspect of the present invention, in the image processing apparatus, the intermediate processing performed by the first processor is performed by converting a graphic represented by coordinates of vertices into a pixel area including a boundary of the graphic,
This is a process of classifying into other pixel regions.

According to a third aspect of the present invention, in the image processing apparatus, the intermediate processing by the first processor scans a trapezoid represented by the coordinates of the vertices in the same direction as the base, and includes a pixel including the first hypotenuse. This is a process of classifying into a region, a pixel region including the second hypotenuse, and another pixel region.

In an image processing apparatus according to a fourth aspect of the present invention, the intermediate processing by the first processor scans a rectangle represented by coordinates of vertexes in one direction, and a pixel area including a boundary of the rectangle. This is a process of classifying into other pixel regions.

An image processing apparatus according to a fifth aspect of the present invention includes, in the subsystem, a second processor in addition to the SIMD type processor, and the second processor arranges the second processor regularly in the image. The processing for developing a plurality of repeated representations of the same figure is executed.

An image processing apparatus according to a sixth aspect of the present invention, in the subsystem, further comprises a second processor and a memory accessible by the second processor in addition to the SIMD type processor. The processor is
The whole or a part of the image is divided into a plurality of sections (sub-zones) by using the area division table configured on the memory, and the graphic elements in the plurality of divided sections are divided by the SIMD type processor for each section. This is assigned to each arithmetic unit.

The image processing apparatus according to a seventh aspect of the present invention is configured such that, when assigning the divided sections to the respective arithmetic units of the SIMD type processor, a section belonging to the first image and a second section corresponding to the first image. Blocks belonging to an image are assigned to a set of arithmetic units that exchange data at the highest speed.

An image processing apparatus according to an eighth aspect of the present invention uses a SIMD processor in which each arithmetic unit is connected in a ring as the SIMD processor, and uses a section belonging to the first image and a corresponding second section. Are assigned to adjacent computing units.

An image processing apparatus according to a ninth configuration of the present invention uses a plurality of the area division tables, and the second processor concurrently executes the other area division processing while executing the partition division processing using one of the area division tables. The data to be processed by the SIMD type processor is supplied by using the area division table.

In the image processing apparatus according to a tenth aspect of the present invention, in the SIMD type processor, each of the arithmetic units individually has a flag register whose state changes according to the operation result. At this time, on the condition that the value stored in the flag register is in an active state or an inactive state, it is possible to control whether or not to execute an instruction for each arithmetic unit, and By referring to the register values at a time, it is determined whether or not the values of all the flag registers have been updated, thereby determining whether or not all the arithmetic units have satisfied a predetermined condition.

In an image processing apparatus according to an eleventh aspect of the present invention, in the SIMD type processor, each arithmetic unit individually has at least one register and a flag register whose state changes according to the operation result. When executing the instruction, the value of the desired coordinate required for the pixel value expression is temporarily determined in advance, and the value stored in each flag register is in the active state or the inactive state. The desired coordinates are determined by updating the value of the coordinates under the condition of, and are converted to pixel value representation.

An image processing apparatus according to a twelfth aspect of the present invention calculates a pixel value by calculating an area of a shared area between a trapezoid included in image data represented by coordinates and a pixel area having a predetermined side length. When converting into a representation, the coordinates temporarily determined in advance based on the result of comparing the coordinate value of the intersection of the boundary line of the pixel area with one of the oblique sides of the trapezoid and the coordinate value of the vertex of the pixel area. Is updated.

An image processing method according to a first method of the present invention is a SIMD type processor having a plurality of arithmetic units and a control unit for controlling the arithmetic operation of the arithmetic units. Has a flag register that changes, and when an instruction is executed, an instruction is issued to each arithmetic unit on condition that a value stored in the flag register is in an active state or an inactive state. It is possible to control whether or not to execute, and refer to the values of all the flag registers at once, and determine whether or not the values of all the flag registers have been updated. This is to determine whether or not the condition is satisfied.

An image processing method according to a second method of the present invention is a SIMD type processor having a plurality of arithmetic units and a control unit for controlling the arithmetic operation of the arithmetic units, wherein each of the arithmetic units has at least one register and A flag register whose state changes according to the operation result is separately provided. At the time of an execution instruction, the value of a variable is temporarily determined in advance, and the value stored in each flag register is activated. The variable is determined by updating the value of the variable on condition that it is in a state or an inactive state, and a different operation is performed for each arithmetic unit.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. The image comparison system described in the present embodiment executes the processing disclosed in the conventional example at a high speed by combining and coordinating a conventional data processing processor and a SIMD type processor. FIG. 1 shows the overall configuration of the image processing apparatus according to the present embodiment. FIG.
In the figure, 100 is a first processor, 101 is a general-purpose bus, and 180 is a subsystem connected to the first processor 100 and the general-purpose bus 101. In the subsystem 180, 102 is an I / F unit for interfacing with the general-purpose bus 101, 103 is an internal bus in the subsystem 180, and 104, 105, and 181 are internal buses 10 respectively.
A second processor, memory, and S connected by
IMD (Single Instruction stream Multiple Data st
ream) type processor. SIMD type processor 18
1 denotes a control unit (CU) 106 and a computing unit (PU) 107-0.
To 107-7. In the SIMD type processor 181, the CU 106 has a memory,
The program, the first processor 100, and the PU ₀ 1
07-0 to PU ₇ 107-7 (hereinafter referred to as each PU)
Can be temporarily stored.
The CU 106 controls the execution of operations performed by each PU.
Each PU has a local memory (LM), and can store an operation result according to an instruction from the CU 106.

The operation will be described below. First, the image data to be compared will be described. FIG. 2 is an image diagram showing an example of the image data, and FIG. 3 is a data format of the image data. As shown in FIG. 2, the image data is divided into areas indicated by A to H (hereinafter, referred to as sections). Also, in the data format shown in FIG. 3, graphic data is described for each section. For example, section A describes five trapezoids and one rectangle. When the graphic straddles the boundary of the section, the figure is described in both sections. Further, in the present embodiment, the image data used is a rectangle (rectangle),
It has a trapezoidal shape. More specifically, a rectangle is a line segment (X
(1, Y1) (X2, Y2) are diagonal lines, each side is an x-axis,
The trapezoid has a base parallel to the x-axis and four vertices at (X1, Y1) (X2, Y1) (X
3, Y2) (X4, Y2).

A procedure for comparing two pieces of image data described as above will be described. FIG. 4 is a configuration diagram illustrating the image processing system according to the present embodiment. In the figure, reference numeral 301 denotes processing executed on the first processor 100;
302, a process to be executed on the second processor 104;
Numeral 3 denotes processing on the SIMD type processor 181. More specifically, the process 301 operates a file to read image data for one section from the file, and reads coordinate data for defining basic figures (rectangles and trapezoids) constituting the image data. A process 301-2 for converting the data into intermediate data based on the SIMD type processor 181 so as to facilitate the processing in the SIMD type processor 181 (bitmap pre-processing), and transferring the intermediate data to the memory 105 via the general-purpose bus 101. It comprises a process 301-3 for transferring, a process 301-4 for receiving image comparison data from the SIMD type processor 181, and a process 301-5 for displaying a comparison result. When the data transfer processing 301-3 completes the data transfer to the memory 105, the data read processing 303 is performed again.
-1 is executed, the data of the next section is read out, and the processing of the intermediate data generation processing 301-2 and the data transfer processing 301-3 is repeated until there is no more partition data in the file. At this time, data reception processing 301-4, display processing 3
The process of 01-5 may be performed sequentially or in parallel with the processes 301-1 to 301-3. Also,
A plurality of subsystems 180 are connected, and the memory 1 of the subsystem which has been alternately processed from the first processor or has been processed
05, the intermediate data may be transferred.

Reference numeral 302 denotes processing performed on the second processor 104, which further processes the intermediate data transferred from the first processor 100,
And processing for managing the operation of the SIMD type processor 181. 303 is SI
This shows processing executed on the MD-type processor 181. The processing 303-1 expands into bitmap data using the data transferred from the second processor 104, and the two types of bitmap data generated in the above processing are shown. Bit map comparison processing 303 for comparing
-2, and the data subjected to the comparison processing is
The process 303-3 is to send the data to 00. Note that the bitmap comparison process does not necessarily need to be performed for each pixel, and may be performed by another method.

Next, how the processes 301, 302, and 303 cooperate with each other on the first processor, the second processor, and the SIMD type processor will be described. Processing on the first processor, the second processor, and the SIMD type processor is performed in units of the above-described sections. In this system, the processed data is transferred to the next processor after the processing of the above three types of processors is completed, and the processing of the data of the next section is started. Such processing is generally called pipeline processing, and is applied in various fields as one method of parallel processing.

Now, the pipeline operation in the present system will be described. That is, the first processor 100
After converting the graphic data in the section A into the intermediate data according to, the second processor 104 starts processing the intermediate data. At this time, the first processor 100 simultaneously converts the graphic data in the next section, section B, into intermediate data. After the first processor 100 completes the processing of the section B and the second processor 104 completes the processing of the intermediate data of the section A, the intermediate data of the section A is transferred to the SIMD type processor 181. The SIMD type processor 181 executes a bitmap development process of the intermediate data and a comparison process for each pixel of the bitmap data.

Next, details of processing in each processor will be described. First, the processing 30 in the first processor 100
1 will be described. The data reading process 301-1 reads one section of the image data stored on the disk. As shown in FIG. 3, in the format of the image data used in the present embodiment, a basic figure is described for each section, so the data reading process 301-1 reads a flag indicating the start of the section. Thus, the start of the section can be recognized, and the end of the data in the section can be detected by reading the flag indicating the end of the section.

In the conversion process 301-2 to intermediate data,
Based on the data of each basic figure of a trapezoid and a rectangle represented by the coordinates of each vertex, intermediate data that can be efficiently developed into a bitmap by the SIMD processor is generated.

Hereinafter, a method of generating intermediate data will be described.
Note that the coordinates used hereinafter are expressed assuming that the side length of the pixel area is 1. FIG. 5 is a diagram describing the basic concept of generating intermediate data for a trapezoid. First, the concept of intermediate data generation will be described with reference to FIG. In the figure, 710
Is a trapezoid and is represented by the coordinates of vertices 711, 712, 713, and 714. Reference numeral 700 denotes a boundary line group that divides a plane into square regions each having a unit of a predetermined resolution. The above-mentioned square area is generally called a pixel (pixel) or a pixel area (pixel area). Reference numeral 701 denotes a coordinate position for specifying the position of the pixel area.

The definitions of the symbols used in FIG. 5 are shown below. (1) (X, Y) is a coordinate value indicating the position of the pixel area. Therefore, the pixel area is in the x-axis direction from X to X +
Up to 1, the y-axis direction is a square area from Y to Y + 1. (2) (X1, Y1) are the coordinates of the end point of the base of the trapezoid having a small x coordinate. (3) Y2 is the y coordinate of the upper side of the trapezoid. (4) IXL and IYL are inclinations of the left oblique side. That is, IX
L is an increment in the y-axis direction with respect to an increment 1 in the x-axis direction. IYL
Is the increment in the x-axis relative to the increment 1 in the y-axis, and I
XL and IYL are reciprocals of each other. However, when IYL is 0, it indicates that the hypotenuse is parallel to the y-axis regardless of the value of IXL. Similarly, IXR and IYR are inclinations of the right oblique side. That is, IXR is the increment in the y-axis direction with respect to the increment 1 in the x-axis direction. IYR is x for increment 1 in the y-axis direction.
IXR and IYR are axial reciprocals. However, when IYR is 0, it indicates that the hypotenuse is parallel to the y-axis regardless of the value of IXR. (5) AD1, L11, L12, L13, AD2, L2
1, L22, L23,... Are a set of four integers (hereinafter, simply referred to as “four sets”) (ADi, Li1, Li2, L
i3) NV columns {(AD1, L11, L12, L1
3), (AD2, L21, L22, L23),... These quads specify a collection of pixels containing the trapezoidal portion of interest. At this time, the quadruple (AD1, L11, L12, L13) represents the pixel row including the target trapezoidal portion having the smallest y coordinate. Here, the pixel row is a row of pixels arranged in the x-axis direction. AD1 indicates the position on the pixel array of the pixel having the smallest x coordinate in this pixel row. ADi (i = 1,
2,3. . . ) Is conceptually an index of a two-dimensional array, so it is originally a two-dimensional value. However, for convenience in the program, a value mapped to a one-dimensional memory address is used. Next, the quad (AD1, L11, L12, L
The meaning of the remaining three elements of 13) will be described. That is, from the pixel at the address specified by AD1, the left oblique side of the trapezoid passes through L11 pixels arranged in the positive direction of the x axis, the next L12 is inside the trapezoid, and the next L13
This indicates that the right oblique side of the trapezoid passes through the individual. Similarly, AD2 indicates the position of the pixel having the smallest x-coordinate among the pixel rows having the second smallest y-coordinate, and the number of pixel rows passing from the pixel to the left oblique side of the trapezoid arranged in the x-axis direction is L21, The number of internal pixel rows is L22
The number of pixel rows through which the right oblique side of the trapezoid passes is L23. In the present embodiment, the quadruple is defined in the positive direction of the x-axis. However, the same effect can be obtained by defining the group in the negative direction of the x-axis.

The generation of the intermediate data is based on the coordinate data defining the trapezoid, the above four sets, IXL, IYL, IXR,
This corresponds to generating IYR and the like. Next, a procedure for generating a quadruple of the intermediate data will be described. FIG. 6 shows a flowchart thereof. A procedure for generating the above-mentioned quadruple will be described with reference to the drawings. (1) Initialization is performed (S1). That is, Y is the smallest y coordinate in the pixel area including this trapezoid in Y, and the variable xh
X1 is substituted for 1 and X2 is substituted for the variable xhr. (2) The x coordinates xll and xlr of the pixel area including the intersection of y = Y with the left oblique side and the right oblique side are obtained (S
2). (3) The i-th quadruple ADi, Li1, Li2, Li3 is calculated using the variables xhl, xhr, xll, xlr (S3). (4) Update the variable (S4). That is, Y ← Y + 1, x
hl ← xll, xhr ← xlr, i ← i + 1. (5) Thereafter, by repeating (2), (3), and (4), it is possible to generate a possible four-tuple for i.

Next, the intermediate data for the rectangle will be described. FIG. 7 is a diagram showing a relationship between a numerical value obtained as intermediate data and a given rectangle. As shown in the figure, the intermediate data for the rectangle is X, Y, N, NBvector,
arg1, large2, large3, large4. The meaning of each element of the intermediate data will be described below. Numeric values large1, large2, large3,
“large4” indicates a ratio of the rectangular area to pixels including the periphery of the rectangular area among pixels including the rectangular area. More specifically, it can be obtained by the following equation. large1 = 1-fr (X1) large2 = fr (Y2) large3 = fr (X2) large4 = 1-fr (Y1) where α is a real number and fr (α) represents a fractional part of α. The variable NBvector is the number of pixels including the rectangular area in the y-axis direction. The variable N indicates the number in the x-axis direction. The coordinates (X, Y) are the coordinates of the pixel having the smallest x-coordinate and y-coordinate among the pixels including the rectangular area.

The intermediate data conversion processing 301-2 is thus performed in the first processor 100, and the obtained intermediate data is transferred to the second processor by the transfer processing 301-3. The second processor 104 in the present embodiment further processes the intermediate data to create data to be sent to the SIMD type processor 181 when there are a plurality of repeated representations of the same figure regularly arranged in the image.

The repetition expression includes the number of repetitions Nx of the basic graphic in the x-axis direction, the number of repetitions Ny in the y-axis direction, and the interval of repetition in the x direction, in addition to the coordinate values for expressing the basic graphic described above. dx and the repetition interval dy in the y direction. Here, Nx and Ny are integers, and dx and dy are real numbers. That is, the trapezoids belonging to the repetitive arrangement are represented by moving the basic figure as a base in parallel as follows. (X1 + i · dx, Y1 + j · dy), (X2 +
i · dx, Y1 + j · dy), (X3 + i · dx, Y2)
+ J · dy), (X4 + i · dx, Y2 + j · dy) where i and j are integers and satisfy 1 ≦ i ≦ Nx and 1 ≦ j ≦ Ny. In this case, most elements such as a quadruple, IXL, IYL, IXR, and IYR, which constitute the intermediate data, depend only on the shape of the figure, and are independent of the position of the figure. For example, IXL, IYL, IXR, IYR
Represents the inclination of the hypotenuse of the trapezoid or the reciprocal of the inclination, and is irrelevant to the position of the figure. In addition, four sets (AD
i, Li1, Li2, Li3), the first element A
Only Di depends only on the position of the figure, and the remaining elements Li1, Li2, and Li3 depend only on the shape of the figure. Therefore, as for the intermediate data for the repetitive figure, the parallel movement is added to the quadruple of the first elements ADi in accordance with the generation of the intermediate data when the repetition is not considered and the values of Nx, Ny, dx, and dy described above. It can be generated only by: In the following, a figure constituting a repetitive arrangement is referred to as an array figure.
When rasterizing the intermediate data into bitmap data, it is necessary to rasterize the array graphic. In the present embodiment, this rasterization processing is executed by the second processor 104.

The second processor 104 further executes the following processing in addition to the above-described array graphic development processing. This processing will be described. In the present embodiment, as shown in FIG. 8, the section is divided into partial areas, and the image data is compared for each partial area. Hereinafter, this partial area is referred to as a subzone. Note that, in the format of the image data file shown in FIG. 3, the description order of the graphic data in the section is arbitrary, and the description is particularly made assuming that the graphic data is not described collectively for each subzone.
Of course, it is needless to say that the present method is applicable even when graphic data is described collectively for each subzone.

The second processor 104 performs the above-described processing for grouping graphic data in a section into sub-zones. FIG. 9 is a diagram for explaining a procedure for collecting graphic data in a section. An area division table 401, on the memory 105 accessible by the second processor,
And an area 402 for storing intermediate data from the first processor 100. The table 401 has an entry for storing a pointer (address) to intermediate data for each subzone, an integer value necessary for determining a position of the figure when the figure forms an array figure, Nx,
It has an area for storing Ny. If the figure is not an array figure, -1 is stored in Nx and Ny. At the head of the sub-zone of the table 401, there is an entry for storing the number of graphics stored in the sub-zone. In addition,
In the memory area 402 for storing the intermediate data of the figure,
The flag includes a flag indicating the type of the graphic and an array flag indicating whether the graphic forms an array graphic.

Hereinafter, a method of grouping figures by sub-zone by the second processor will be described. The second processor reads the memory area 402 in which the intermediate data for one section is stored from the beginning, and acquires the coordinate values of the corresponding figure. From this coordinate value, the sub-zone occupied by the figure is calculated, and the head address of the area where the intermediate data of the figure is stored is written in the entry storing the pointer of the table 401 corresponding to the sub-zone. , The number of graphics stored in the sub-zone is increased by one. At this time, if the graphic constitutes an array graphic, coordinate values are obtained, coordinate conversion is performed in advance using offset values Nx and Ny, and the coordinate values after coordinate conversion are calculated in subsequent calculations. use. The offset values Nx and Ny are written in the table 401.

The second processor 104 reads each entry of the table 401, and can read the graphic data based on the address of the memory area where the intermediate data stored in the entry is actually stored. Further, the second processor 104 converts the figure compiled for each sub-zone into an S
It has a function of transferring to a local memory accessed by each arithmetic unit (PU) of the IMD type processor.

Next, a method of transferring the read intermediate data to the local memory will be described. In the present embodiment, a SIMD processor 181 having eight arithmetic units (PUs) connected in a ring is used. In the present embodiment, the image data to be compared with the local memory that can be locally accessed by the four PUs having even numbers are stored in the local memory that can be locally accessed by the remaining PUs having odd numbers. Transfer the data of the reference image. That is, along the ring network, each PU is numbered PU ₀ , PU ₁ , PU ₂ , P
U ₃ ,. . . , PU ₇ with an even number
U ₀ , PU ₂ , PU ₄ ,. . Store the intermediate data of one image in the local memory of PU ₁ , PU ₃ , PU ₅ . . Put in. As described above, in the SIMD type processor according to the present embodiment, the network connecting each PU is on a ring, and the time required for data transfer between adjacent PUs is minimized.

In the SIMD type processor 181 used in the present embodiment, it is assumed that each PU has a structure in which each PU is connected in a ring shape. However, according to the form of a network connecting PUs, a path for connecting PUs is used. It is apparent that the same effect can be obtained if the data comparison is performed between PUs having a short data transfer time between PUs, that is, the shortest data transfer time between PUs.

It should be noted that while the second processor uses a plurality of area division tables and the second processor executes partition division processing using one of the area division tables, the second processor concurrently uses the other area division table to execute the SIMD type processor. Data to be processed may be supplied.

Next, the processing in the SIMD type processor 181 will be described. In the SIMD type processor 181 according to the present embodiment, the first processor 100
Based on the intermediate data, which are converted into intermediate data, are grouped for each sub-zone by the second processor, and are stored in the local memory of the appropriate PU of the SIMD type processor, a bitmap expansion process and a bitmap comparison process are performed. I do.

First, the bitmap expansion process for trapezoidal intermediate data will be described. In the present embodiment, a method of determining a pixel value in accordance with the ratio of the figure occupying the pixel area is employed in the bitmap development process. FIGS. 10, 11, and 12 are flowcharts showing a procedure for developing trapezoidal intermediate data into a bitmap. In this flowchart, S5-1 to S5-1
5-6 is a portion for calculating a pixel value included in the left oblique side of the trapezoid, and S5-15 to S5-17 are a portion for calculating a pixel value included in the right oblique side of the trapezoid.
7 to S5-12 are portions for calculating the pixel values of the portions other than the above.

The details of each part will be described below. (S5-1) Extract ADi from the quadruple of the intermediate data,
The product Y · W of the address Y of the pixel at the lower left corner of the subzone and the width W of the subzone is added to ADi to obtain a variable AD, which is substituted for ADx. (S5-2) The procedure of calculating the area of the pixel including the left oblique side of the trapezoid by a method described later and writing the calculated result to the local memory indicated by the contents of the register AR0 local to each PU is called. (S5-3) One is added to the value of ADx, and it is assigned to ADx and assigned to the register AR0. (S5-4) After executing the subtraction "AD + Li1-ADx", refer to the zero flag register locally arranged in each PU, and if the zero flag is set, that is, if the target pixel is the left oblique side of the trapezoid, This means that it is no longer included, but only for PUs that satisfy this condition, -1 is written to a predetermined address of the local memory (S5-5). On the other hand, the PU that does not satisfy the above conditions does nothing. This processing uses conditional instructions employed in the SIMD type processor used in the present embodiment. The contents of this conditional instruction will be described later. (S5-6) It is checked whether or not the zero flag or the negative flag is set for all PUs.
If U does not satisfy the above condition, S5-2 to S5-6 are repeated until all the PUs satisfy the above condition.
Note that the above flag test is performed for all PUs under the condition “ADx ≧
This is equivalent to testing whether AD + Li1 ″ is satisfied.

Hereinafter, the above-mentioned conditional instruction will be described. Due to the characteristics of the SIMD type processor, different instructions cannot be given to each PU. S used in the present embodiment
The IMD type processor has a local flag register in each PU whose state changes according to the operation result. It also has an instruction for referring to the value of the flag register at a time. After performing the subtraction in the procedure (S5-4), the content of the flag register is updated according to the result of the operation. By testing the zero flag, it is possible to determine whether ADx has become equal to AD + Li1 in each PU. Further, the SIMD type processor includes a conditional instruction for executing the next instruction on condition that the flag is set by referring to a flag register located in each PU. The conditional instruction executes the instruction if the specified flag is set, and does not execute the instruction if the flag is not set. In the case of the procedure (S5-4), the procedure (S5-5) is executed only for the PU for which the zero flag register is set. The procedure (S5-5)
Thus, in the PU in which -1 has been written to the address PU of the local memory, the procedure (S5-
2) is not performed. That is, the procedure (S5-2) refers to the address PU address of the local memory, and the PU in which -1 is written does not execute the memory write operation. Also, in the following description, it is assumed that when -1 is written to the address PU of the local memory, the bitmap expansion processing to the local memory is not executed.

(S5-7) Local register A of each PU
Substitute 1 for R1. (S5-8) The content of the local register AR1, that is, 1 is written to the address of the local memory indicated by each local register AR0. (S5-9) At the same time as increasing the value of ADx by 1, the latest value of ADx is substituted into the local register AR0. (S5-10) Subtraction "AD + Li1 + Li2-ADx"
Is executed, the zero flag register located in each PU is referred to, and if the zero flag is set, that is, the target pixel is in the area including the right hypotenuse of the trapezoid, PU that satisfies
-1 only at a predetermined address in the local memory
Is written (S5-11). On the other hand, the PU that does not satisfy the above conditions does nothing. This processing uses the same method as the above-mentioned conditional instruction. (S5-12) It is checked whether or not the zero flag or the negative flag of all PUs is set.
Do not satisfy the above conditions, S5-7 to S5-12 are repeated until all the PUs satisfy the above conditions.
It should be noted that the above flag test is performed on all PUs under the condition “AD”.
This is equivalent to checking whether x> AD + Li1 + Li2 ″ is satisfied. (S5-13) Include the right oblique side of the trapezoid by the same method as the below-described method of calculating the area of the pixel including the left oblique side of the trapezoid. Call the procedure of calculating the area of the pixel and writing the calculated result to the local memory indicated by the contents of the register AR0 which is local to each PU (S5-14) Add 1 to the value of ADx, substitute it into ADx, and register AD0 (S5-15) Subtraction "AD + Li1 + Li2 + Li3-
After executing ADx ", reference is made to the zero flag register located locally on each PU, and if the zero flag is set, meaning that the pixel of interest no longer contains the right hypotenuse of the trapezoid, Only for PUs that satisfy this condition, -1 is written to a predetermined address of the local memory (S5-16), whereas on the other hand, PUs that do not satisfy the above condition do nothing. (S5-17) Check whether the zero flag or negative flag of all PUs is set, and if all PUs
Do not satisfy the above conditions, S5-13 to S5-17 are repeated until all the PUs satisfy the above conditions. It should be noted that the test of the above flag is conditional on all PUs.
This is equivalent to checking whether ADx> AD + Li1 + Li2 + Li3 ″ is satisfied.

After the above procedure is completed, return to S5-1,
The processing of the next quadruple is started, and the processing is continued until there is no quadruple in the trapezoidal intermediate data.

Hereinafter, the above-described procedures S5-2 and S5-13 will be described.
The method for calculating the value of the pixel including the left oblique side or the right oblique side of the trapezoid in FIG. The instruction sequence is executed simultaneously by a plurality of PUs. However, although each PU handles different data, execution branches also occur in all PUs in the same manner, so that a conditional branch instruction cannot perform a process according to the condition satisfied by the data on each PU. SIMD used here
In the type computer, branch processing according to data on each PU is realized by “conditional instructions”. As described above, the “conditional instruction” means that, when each PU executes the “conditional instruction”, only the PU satisfying the condition is determined by the result of the comparison instruction, that is, the content of the flag provided for each PU. The instruction is executed, and the other PUs do nothing until the execution of the next instruction.

Hereinafter, a method of realizing a procedure for calculating a plurality of figures in parallel by a SIMD type computer will be described, taking the values of pixels including the left oblique side of a trapezoid as an example. This procedure is used to represent a trapezoid represented by several two-dimensional vectors as a two-dimensional array of pixels whose elements are real values from 0 to 1. The real values from 0 to 1 are used as pixel values. Call. The two-dimensional array of pixels will be referred to as a pixel array. A pixel occupies a square area on a two-dimensional coordinate plane, and this area will be referred to as the pixel area of that pixel. This procedure calculates the ratio of the area of a certain pixel area on a two-dimensional coordinate plane and the area of a part included in the trapezoid to the area of the area occupied by the pixel on the two-dimensional coordinate plane when a certain trapezoid is specified. Is calculated. The ratio is one component of the pixel value. If another graphic exists in the area, it is handled by a predetermined method. For example, pixel value components for them are added to determine a pixel value. There is also a method of taking the largest pixel value.

This procedure uses variables Xc and Y for calculation.
T, YB, H, IXL, IYL, Ly, Ry, Bx, T
Use x. FIG. 13 shows a flowchart of the above procedure. (S11) The initial values of YB and YT are set to the lower and upper limits of the pixel area in the y-axis direction. That is, the value of YB is Y,
Let the value of YT be Y + 1. (S12) When the upper side of the trapezoid passes through the pixel area, YT
Is the Y coordinate. That is, the value of YT is set to Y2 on condition that Y2 <YT. Similarly, when the lower side passes through the pixel area, the value of YB is set to its Y coordinate. That is, YB <
The value of YB is set to Y1 on condition of Y1. (S13) y at the intersection of the left oblique side of the trapezoid and the straight line x = X1
The coordinates Ly are determined. That is, the value of Ly is set to (IXL · (X−
X1) + Y1). Similarly, the left oblique side of the trapezoid and the straight line x
= X1 + 1 is determined at the y coordinate Ry. That is, Ry
Is (IXL · (X + 1−X1) + Y1). However, when IYL = 0, it indicates that the hypotenuse is parallel to the y-axis, and both the value of Ly and the value of Ry are set to 0 on the condition that IYL = 0. (S14) FIG. 14 shows a square representing a pixel area, which is denoted by reference numeral 709. There is a trapezoid T representing a figure in which the target trapezoid intersects the pixel area,
The reference numeral 708 is attached to this. A straight line y = YT and a triangle C representing a non-trapezoidal portion separated by the left oblique side from the area of the rectangle formed by the straight line y = YB in the pixel area are denoted by reference numeral 707. YT and YB are adjusted to obtain the height H of the figure T shown in FIG. 14 in the y-axis direction. On the condition that (Ly>Ry> YB), the value of YB is Ry. And (Ly <Ry <
YT), and the value of YT is Ry. Then, the value of H is determined by YT-YB. (S15) Next, YT and YB are adjusted to obtain the height of the figure C in the y-axis direction in FIG. (YB <Ly <Ry)
, And the value of YB is set to Ly. And (Ly <R
Under the condition that y <YT), the value of YT is set to Ly. (S16) Next, the x-coordinates Bx and Tx of the two end points of the line segment existing in the pixel area in the left oblique side are obtained. The value of Bx is determined as X1− (YB−Y1) · IYL, and the value of Tx is determined as Bx−IYL · (YT−YB). Then, as the x coordinate of the midpoint of the line segment, the value of Xc is given by (Tx + B
x) / 2. Then, the area of the graphic C in FIG.
−X) · (YT−YB). (S17) H- (Xc-X) · (YT-YB) is FIG.
Is the area of the figure T, which is the result obtained by this procedure.

The area obtained in the above procedures (S11) to (S17) is written to the address of the local memory indicated by the contents of the local register AR0, and the processing is terminated.
Executes the next instruction that calls this procedure. At this time, the writing to the local memory is controlled using the above-mentioned conditional instruction so that only the arithmetic unit whose contents of the PU address of the local memory of each arithmetic unit are not -1 is executed.

FIGS. 15 and 16 show cases where the above procedure can be applied for reference. It can be seen that the above procedure applies to all 13 cases in the figure.

The process of calculating the area of the pixel including the right oblique side of the trapezoid in the above-mentioned step S5-13 and writing the value of the area to the address of the local memory indicated by the contents of the local register AR0 is the same as the above-mentioned procedure (S11). ~
This is the same as (S17).

Next, a method of expanding a rectangular bitmap will be described. FIG. 17, FIG. 18, and FIG. 19 show the procedure of rectangular bitmap development. Intermediate data (X, Y, N, N
Bvector, large1, large2, large3, l
arg4) has already been described as being stored in the local memory of each PU.

(S6-1) The variable count is initialized to 1. (S6-2) The address of the pixel area is calculated from the starting coordinates (X, Y) of the rectangle. (S6-3) The variable in is initialized to 1. (S6-4) The subtraction "count-1" is executed, and only the PU for which the zero flag is set has the la in the variable in.
rg2 is substituted (S6-5). (S6-5) The subtraction "NBvector-count" is executed, and only for PUs for which the zero flag is set, large4 is substituted for the variable in (S6-7). (S6-8) Variables left and right are each large
Substitute 1 · in and large3 · in. (S6-9) Left is assigned to the local register AR1. (S6-10) The contents of AR1 are written to the address of the local memory indicated by the local register AR0. At this time, the PU in which -1 is written at the address PU of the local memory does not execute writing to the local memory. (S6-11) Set the value of the local register AR0 to AR0 +
Update to N, substitute the value of AR0 for variable STOP, and substitute the contents of variable right for local register AR1. (S6-12) The contents of AR1 are written to the address of the local memory indicated by the local register AR0. (S6-13) Set the value of the local register AR0 to AR0-
Update to N. The variable i is stored in the local register AR1.
Substitute the contents of n. (S6-14) The contents of AR1 are written to the address of the local memory indicated by the local register AR0. (S6-15) Add 1 to the local register AR0,
Substitute AR0. (S6-16) Execute the subtraction "STOP-AR0",
Only the PU for which the zero flag is set is -1 to the variable PU.
Is substituted (S6-17). (S6-18) It is tested whether the zero flag or the negative flag of all PUs is set. If all P
When the zero flag or the negative flag of U is not set, the process returns to S6-14, and when it is set, the following processing is executed. (S6-19) After executing the subtraction "NBvector-count", the zero flag is tested, and only the PU for which the zero flag is set is substituted with -1 for the variable PU (S6).
-20). (S6-21) It is tested whether the zero flag or the negative flag of all PUs is set. If the zero flag or the negative flag has not been set for all PUs, the value of the variable count is increased by 1 (S6-2).
2) Returning to S6-3, if set, execute bitmap expansion processing for the next rectangle.

As described above, the bitmap is formed from the rectangular intermediate data on the local memory of each PU by the above procedure.

The bitmap data obtained by the bitmap expansion processing is transferred between the PUs as described above, and the bitmap comparison processing is executed.

[0056]

As described above, according to the first configuration of the present invention, an image in which a graphic element is represented by coordinates is divided into pixel regions having predetermined side lengths, and is represented by coordinates. A first processor that intermediately processes the image data to generate intermediate data, and a SIMD type processor that has a plurality of arithmetic units and a control unit that controls the operation of the arithmetic units. By using the intermediate data, the image data represented by coordinates is converted into a pixel value representation, and a subsystem for comparing the first image with the second image is provided.
When converting the image data in the coordinate expression into the pixel value expression, parallel processing can be performed, and an image processing apparatus capable of comparing and verifying two images at high speed can be obtained.

According to the second configuration of the invention, the intermediate processing by the first processor classifies the graphic represented by the coordinates of the vertices into a pixel area including a boundary of the graphic and another pixel area. Therefore, branch processing can be reduced in processing in the subsequent SIMD type processor, and processing efficiency is improved.

Further, according to the third configuration of the present invention, the intermediate processing by the first processor scans the trapezoid expressed by the coordinates of the vertices in the same direction as the base, and scans the pixel area including the first hypotenuse. And the pixel area including the second hypotenuse, and the other pixel areas. Therefore, the same effect as the second configuration can be obtained for trapezoidal figures.

Further, according to the fourth configuration of the present invention, the intermediate processing by the first processor scans the rectangle represented by the coordinates of the vertexes in one direction, and scans the pixel area including the boundary line of the rectangle. , And other pixel areas, the same effect as the second configuration can be obtained for a rectangular figure.

According to the fifth configuration of the present invention, the subsystem includes a second processor in addition to the SIMD type processor, and the second processor uses the second processor to arrange a plurality of regularly arranged images in the image. Since the repeated representation of the same figure is expanded, the load on the first processor is reduced, and the computational resources of the system can be more effectively utilized.

According to the sixth configuration of the present invention, the subsystem includes, in addition to the SIMD type processor, a second processor and a memory accessible by the second processor. Uses an area division table configured on the memory to divide all or a part of an image into a plurality of sections (sub-zones), and divides graphic elements in the plurality of divided sections into SIMs for each section.
Since the assignment is made to each operation unit of the D-type processor, there is an effect that the process of putting together the figures according to the coordinates of the figures can be performed in a short time.

According to the seventh aspect of the present invention, when the divided sections are assigned to the respective arithmetic units of the SIMD type processor, the sections belonging to the first image and the second images corresponding thereto are assigned. Are assigned to a set of arithmetic units that transmit and receive data at the highest speed, so that comparison of pixel values for each image can be performed at high speed.

Further, according to the eighth configuration of the present invention, a SIMD type processor in which each operation unit is connected in a ring is used as the SIMD type processor, and a section belonging to the first image and a second section corresponding to the section belong to the first image. Since the sections belonging to the image are assigned to the adjacent computing units, the same effect as in the seventh configuration is obtained.

Further, according to the ninth configuration of the present invention, a plurality of area division tables are used, and while the second processor is executing the division processing using one of the area division tables, the second processor concurrently executes the other area division table. Using the area division table, the SI
Since the data to be processed by the MD processor is supplied, the division processing and the conversion processing to the pixel value executed by the SIMD processor can be performed in parallel in a pipeline, so that the processing efficiency can be improved.

According to the tenth structure of the present invention,
In the SIMD type processor, each operation unit has a flag register whose state changes according to the operation result. When an instruction is executed, the value stored in the flag register is set to an active state or a non-active state. It is possible to control whether or not to execute an instruction for each arithmetic unit on condition that it is in the active state, and to update the values of all flag registers by referring to the values of all flag registers at once. Since it is determined whether or not all the arithmetic units have satisfied a predetermined condition by determining whether or not the operation has been performed, the H / W cost can be reduced.

According to the eleventh structure of the present invention,
In the SIMD type processor, each operation unit has at least one register and a flag register whose state changes according to the operation result. The value of the desired coordinate is temporarily determined, and the value of the coordinate is updated on condition that the value stored in each flag register is in the active state or the inactive state. Since the coordinates are determined and converted into the pixel value representation, the H / W cost can be reduced.

According to the twelfth structure of the present invention,
When converting to a pixel value representation by calculating the area of a shared area between a trapezoid included in image data represented by coordinates and a pixel area having a predetermined side length, a boundary between the pixel area and the trapezoid On the condition that the coordinate value of the intersection with one of the hypotenuses and the coordinate value of the vertex of the pixel area are compared, the provisionally determined coordinate value is updated.
There is an effect similar to that of the configuration described above.

Further, according to the first image processing method of the present invention, in a SIMD type processor having a plurality of operation units and a control unit for controlling the operation of the operation units, each operation unit operates in accordance with the operation result. It has a separate flag register that changes its state. When executing an instruction, the instruction is issued to each arithmetic unit on condition that the value stored in the flag register is active or inactive. Can be controlled or not, and all arithmetic units are determined in advance by referring to the values of all flag registers at once and determining whether or not the values of all flag registers have been updated. It is determined whether or not the above condition is satisfied.
There is an effect that W cost can be reduced.

Further, according to the second image processing method of the present invention, in a SIMD type processor having a plurality of operation units and a control unit for controlling the operation of the operation units, each operation unit has at least one register. And a flag register whose state changes in accordance with the operation result. When an execution instruction is issued, the value of a variable is temporarily determined in advance, and the value stored in each of the flag registers is determined. By updating the value of the variable under the condition of being in the active state or the inactive state, the variable is determined and a different operation is performed for each arithmetic unit, so that the H / W cost is reduced. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram illustrating an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of image data according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a data format of image data according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram illustrating an image processing system according to Embodiment 1 of the present invention;

FIG. 5 is an explanatory diagram illustrating trapezoidal intermediate data according to the first embodiment of the present invention.

FIG. 6 is a flowchart showing a procedure for generating intermediate data according to the first embodiment of the present invention.

FIG. 7 is an explanatory diagram illustrating rectangular intermediate data according to the first embodiment of the present invention;

FIG. 8 is an explanatory diagram illustrating a subzone according to the first embodiment of the present invention.

FIG. 9 is an explanatory diagram illustrating an operation of the second processor according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a SIMD according to the first embodiment of the present invention.
9 is a flowchart showing a procedure for expanding trapezoidal intermediate data into a bitmap in the type processor.

FIG. 11 is a SIMD according to the first embodiment of the present invention.
9 is a flowchart showing a procedure for expanding trapezoidal intermediate data into a bitmap in the type processor.

FIG. 12 is a diagram showing a SIMD according to the first embodiment of the present invention;
9 is a flowchart showing a procedure for expanding trapezoidal intermediate data into a bitmap in the type processor.

FIG. 13 is a SIMD according to the first embodiment of the present invention.
It is a flowchart which shows the procedure which calculates the value of the pixel containing a left oblique side in a type processor.

FIG. 14 is a diagram showing a SIMD according to the first embodiment of the present invention.
FIG. 8 is an explanatory diagram illustrating a procedure for calculating a value of a pixel including a left oblique side in the type processor.

FIG. 15 is a diagram showing a SIMD according to the first embodiment of the present invention.
FIG. 8 is an explanatory diagram illustrating a procedure for calculating a value of a pixel including a left oblique side in the type processor.

FIG. 16 is a diagram showing a SIMD according to the first embodiment of the present invention.
FIG. 8 is an explanatory diagram illustrating a procedure for calculating a value of a pixel including a left oblique side in the type processor.

FIG. 17 is a SIMD according to the first embodiment of the present invention.
9 is a flowchart showing a procedure for expanding rectangular intermediate data into a bitmap in the type processor.

FIG. 18 is a diagram showing a SIMD according to the first embodiment of the present invention.
9 is a flowchart showing a procedure for expanding rectangular intermediate data into a bitmap in the type processor.

FIG. 19 is a SIMD according to the first embodiment of the present invention.
9 is a flowchart showing a procedure for expanding rectangular intermediate data into a bitmap in the type processor.

FIG. 20 is an explanatory diagram illustrating an image processing method in a conventional image processing apparatus.

[Explanation of symbols]

100 first processor, 101 general-purpose bus, 102
I / F unit, 103 internal bus, 104 second processor, 105 memory, 106 control unit, 107-0 to 1
07-7 arithmetic unit, 180 subsystem, 181 S
IMD type processor.

Claims (14)

[Claims] 1. A first processor that divides an image in which a graphic element is represented by coordinates into pixel regions having predetermined side lengths, and intermediately processes the image data represented by coordinates to create intermediate data. And a SIMD-type processor having a plurality of operation units and a control unit for controlling the operation of the operation units, and using the intermediate data created by the first processor to represent image data represented by coordinates in pixel values. To
An image processing apparatus comprising: a subsystem for comparing a first image and a second image. 2. The intermediate processing by the first processor,
2. The image processing apparatus according to claim 1, wherein the graphic processing is performed to classify the graphic represented by the coordinates of the vertices into a pixel area including a boundary line of the graphic and another pixel area. 3. The intermediate processing by the first processor,
The trapezoid represented by the coordinates of the vertices is scanned in the same direction as the base, and is classified into a pixel area including the first hypotenuse, a pixel area including the second hypotenuse, and another pixel area. 3. The image processing apparatus according to claim 2, wherein: 4. The intermediate processing by the first processor,
3. The image processing apparatus according to claim 2, wherein a rectangle represented by the coordinates of the vertices is scanned in one direction, and the pixel is divided into a pixel region including a boundary of the rectangle and another pixel region. 5. The subsystem includes a second processor in addition to the SIMD type processor, and the second processor develops a repeated representation of a plurality of the same graphics regularly arranged in the image. The image processing apparatus according to claim 1, wherein the image processing is performed. 6. The subsystem includes, in addition to the SIMD type processor, a second processor and a memory accessible by the second processor, wherein the second processor has an area division table configured on the memory. And dividing the whole or a part of the image into a plurality of sections (sub-zones), and assigning a graphic element in the plurality of divided sections to each computing unit of the SIMD type processor for each section. The image processing device according to claim 1. 7. When allocating the divided sections to the respective arithmetic units of the SIMD type processor, the sections belonging to the first image and the corresponding sections belonging to the second image are set to the highest data transfer speed. 7. The image processing apparatus according to claim 6, wherein the image processing apparatus is assigned to a group of arithmetic units. 8. A SIMD-type processor in which each arithmetic unit is connected in a ring as said SIMD-type processor, and a section belonging to a first image and a corresponding section belonging to a second image are assigned to adjacent arithmetic units. 8. The image processing apparatus according to claim 6, wherein: 9. The method according to claim 2, wherein a plurality of area division tables are used.
7. The processor according to claim 6, wherein the processor supplies data to be processed by the SIMD processor using the other area division table while the processor is executing the division processing using one area division table. 9. The image processing apparatus according to any one of 8. 10. The SIMD-type processor,
Each arithmetic unit has a flag register whose state changes according to the operation result, and determines that the value stored in the flag register is an active state or an inactive state when executing an instruction. As a condition, it is possible to control whether or not to execute an instruction for each arithmetic unit, and refer to the values of all flag registers at once to determine whether or not the values of all flag registers have been updated 2. The image processing apparatus according to claim 1, wherein the determination is made as to whether or not all the arithmetic units satisfy a predetermined condition. 11. The SIMD-type processor,
Each operation unit has at least one register and a flag register whose state changes according to the operation result. When executing an instruction, a value of a desired coordinate required for pixel value expression is previously determined. Is temporarily determined, and on condition that the value stored in each of the flag registers is in the active state or the inactive state, the value of the coordinates is updated to determine the desired coordinates, and the pixel is determined. 2. The image processing apparatus according to claim 1, wherein the image is converted into a value expression. 12. When converting into a pixel value expression by calculating an area of a shared region between a trapezoid included in image data represented by coordinates and a pixel region having a predetermined side length, a boundary of the pixel region is obtained. The method according to claim 1, further comprising the step of: updating a provisionally determined coordinate value on condition that a result of comparing a coordinate value of an intersection of the line and one oblique side of the trapezoid with a coordinate value of a vertex of the pixel area is used. 12. The image processing device according to item 11. 13. An SIMD type processor having a plurality of operation units and a control unit for controlling the operation of the operation units, each operation unit individually has a flag register whose state changes according to the operation result. When executing an instruction, it is possible to control whether or not to execute an instruction for each arithmetic unit, on condition that the value stored in the flag register is in an active state or an inactive state, In addition, by referring to the values of all the flag registers at a time and determining whether or not the values of all the flag registers have been updated, it is determined whether or not all of the arithmetic units have satisfied a predetermined condition. An image processing method characterized by the following. 14. An SIMD type processor having a plurality of operation units and a control unit for controlling the operation of the operation units, each operation unit includes at least one register and a flag register whose state changes according to the operation result. Are individually provided, and at the time of an execution instruction, the values of the variables are temporarily determined in advance, and on the condition that the values stored in the respective flag registers are in an active state or an inactive state, An image processing method, characterized in that the variable is determined by updating the value of the variable, and a different operation is performed for each arithmetic unit.