JPH10276100A - Error correction method in digital communication - Google Patents

Abstract

(57) [Summary] [Purpose] In various transmission devices having an error correction circuit that performs a puncturing process when transmitting digital data, a puncturing process capable of easily changing a puncturing rate is realized. It is an object of the present invention to provide an error correction method that simultaneously realizes (depuncture) processing, interleave (deinterleave) processing, and synchronous word insertion (deletion) processing. To realize a puncturing process at an arbitrary rate, a puncturing pattern generator capable of easily generating bit deletion / passing information is provided for both transmission and reception. Based on the generated puncture pattern, an address generation unit and a control signal generation unit for the storage device are controlled, and the storage device implements puncturing processing. According to the present invention, processing at an arbitrary puncture rate becomes possible, and dummy bit addition (deletion) processing for adjusting the transmission bit length can be eliminated. Further, by using the storage device, the error correction processing can be simultaneously realized, and the hardware scale can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method for an error correction circuit in digital communication.

[0002]

2. Description of the Related Art In digital transmission, an encoding process is generally performed to detect and correct an error in an information sequence obtained from an information source. In addition, in this encoding process, as a method of the encoding process, from page 261, line 16 to page 261 of “Coding Theory {Issued by the Institute of Electronics, Information and Communication Engineers} published in March 1990.
As described partially on page 262, line 16, instead of outputting all the data from the encoder, the digital signal at a specific bit position is removed to improve the error correction / detection ability by encoding. A method of performing processing that does not perform transfer (puncturing processing) is widely known. The puncturing process is for detecting and correcting several errors in a specific bit length of encoded digital data,
Although it is effective for random errors, it cannot correct for burst-like errors (burst errors) in which errors occur with a length equal to or greater than a specific bit length. Therefore, in order to correct the burst error, the transmission order of the coded data is changed, and a process (interleave process) for dispersing the burst error to such an extent that the burst error can be regarded as a random error is performed. An example of the error correction method using the puncturing process will be described below.

First, an example of the configuration and operation on the transmission side will be described with reference to FIGS. 3, 5, and 7. FIG. FIG. 3 is a block diagram showing a conventional process on the transmission side.

First, the configuration and operation of the transmitting side will be described. In FIG. 3, 1 is a digital data input terminal, 2 is an encoding processing unit, 3 and 4 are storage devices, 20 is a dummy bit addition processing unit, 21
Is a synchronous word insertion processing unit, 6 is a digital data output terminal, 7
Is an address switch, 8 is a write address generator, 9 is a read address generator, 16 is a control signal generator, and 17 is a timing generator. The digital data input terminal 1 is connected to the storage device 3 and the storage device 4 via the encoding processing section 2. Outputs of the storage devices 3 and 4 are connected to a digital data output terminal 6 via a dummy bit addition processing unit 20 and a synchronization word insertion processing unit 21. The output of the timing generator 17 is connected to the encoding processing unit 2, the dummy bit processing unit 20, the synchronization word insertion processing unit 21, the write address generator 8, the read address generator 9, and the control signal generator 16. The output of the control signal generator 16 is connected to the storage devices 3 and 4, and the address switch 7. Outputs of the write address generator 8 and the read address generator 9 are connected to the storage devices 3 and 4 via the address switch 7.

In FIG. 3, a digital data input terminal is shown.
The digital data input from 1 is input to the encoding processing unit 2. In the encoding unit 2, N (integer) bits of digital data are encoded with respect to 1-bit input. The encoded data (encoded data) is subjected to a process of deleting data at a specific bit position (puncturing process), and the punctured encoded data is transmitted to the storage device 3 or the storage device 4. Can be The storage device 3 and the storage device 4 are composed of a control signal generator 16 and an address switch.
By the output of 7, one is controlled to write and the other is read. Immediately after the start of the operation, a description will be given assuming that the storage device 3 performs writing and the storage device 4 performs reading. The process of writing the punctured encoded data to the storage device 3 includes:
According to the output of the write address generator 8 via the address switch 7 and the output of the control signal generator 16, the processing is performed up to the data length (interleave size) for performing interleaving. Meanwhile, the storage device 4 stores the encoded data already stored,
According to the output of the read address generator 9 via the address switch 7 and the output of the control signal generator 16, the data is sent to the dummy bit addition processing section 20. When the writing to the storage device 3 and the data output from the storage device 4 are completed, the control signal generator 16 performs control for switching the operation of the storage device 3 to read data and the operation of the storage device 4 to perform data writing, and The switch 7 performs control to switch the data output destination of the write address generator 8 and the read address generator 9. Thereafter, the operation is alternately switched. At this time, the output pattern of the write address generator 8 and the output pattern of the read address generator 9 are made different to rearrange the order of the input data and the output data (interleave processing).
Is performed. The encoded data output from the storage device 3 is
In order to adjust the transmission speed (adjust the number of transmission bits) in the dummy bit insertion processing unit 20, meaningless dummy bits are added to the data sequence and output to the synchronization word insertion processing unit. The synchronization word is a data sequence determined in advance between the transmission side and the reception side, and generates timing by detecting the position of the determined data sequence (synchronization word) from the data transferred to the reception side. It is for synchronization. The synchronizing word insertion processing section 21 inserts a synchronizing word for synchronizing the operation timing on the receiving side with the transmitting side into the input data sequence, and outputs it from the digital data output terminal 6. Further, the timing generator 17 outputs control information and outputs a timing output for controlling each timing of each processing on the transmission side in performing the above operation.

FIG. 5 is a diagram showing an example of a transmission data pattern output from the digital data output terminal 6. One transmission data size is coded data, dummy bits, and a synchronization word after puncturing, which have been subjected to interleave processing. It is composed of

FIG. 7 is a view for explaining an example of a method of puncturing processing in the encoding processing section 2. 31 is an encoding processing unit
2, encoded data encoded by the encoding unit 2, 32 is a puncture pattern preset in the encoding unit 2, and 33 is a punctured image that has been punctured and output to the encoding unit 2. Is encoded data. The digital data input to the encoding processing unit 2 is encoded with N (integer) bits for one bit, and a data sequence (d0, 0, d0, 1, d1, 0, d
1, 1, d2, 0,..., DN, 0, dN, 1).
When the data (1, 1, 0, 1, 1,..., 1, 0) of the puncture pattern 32 is overlaid on the encoded data 31, the encoded data corresponding to “1” of the data sequence of the puncture pattern 32 is obtained. , The encoded data corresponding to '0' is deleted, and the punctured data 33 (d0, 0, d
0,1, X, d1,1, d2,0, ..., dN, 0, X)
(X indicates a deleted data bit). This coded data is deleted from the portion of X, and becomes coded data of the transmission pattern shown in FIG.

Next, referring to FIG. 3, the change of the transmission bit length at each stage on the transmission side will be described with reference to the following example. Assume now that the coding rate is 1/2 (encoding 1 bit of data into 2 bits) and the puncture rate is 3/4 (outputting 3 bits for 4 bit input). The digital data input to input terminal 1 is 1.
When the transmission speed is 5 Mbps, the digital data becomes 2 bits in the encoding processing unit 2 because one bit becomes 2 bits, and the transmission speed is inevitably increased to 2.25 Mbps. Thereafter, the transmission speed of the data output from the output terminal 6 is as described in 2.
If the transmission speed is not higher than 25 Mbps, data may be missed. Therefore, the transmission speed is usually higher than 2.25 Mbps, for example, 2.5 Mbps. Therefore, in order to transmit data having a bit length longer than the data bit length, a difference between the transmission speed of 2.5 Mbps at the output terminal 6 and the transmission speed of 2.25 Mbps at the output side of the encoding processing unit 2 is equal to 0.
It is necessary to add 25 bits (0.25 Mbps) as dummy bits and transmit the data with a bit length that can be synchronized with the transmission speed.

Next, the configuration and operation of the receiving side will be described. FIG. 4 is a block diagram showing processing on the receiving side. In FIG. 4, 1
′ Is a digital data input terminal, 13 is a synchronization word detection processing unit, 17 ′ is a timing generator, 22 is a synchronization word removal processing unit,
23 is a dummy bit removal processing unit, 7 is an address switch, and 3 and
4 is a storage device, 14 is a decoding processor, 8 is a write address generator, 9 is a read address generator, 16 'is a control signal generator, and 6' is a digital data output terminal.

The digital data input terminal 1 'is connected to the synchronous word detection processing unit 13 and the synchronous word removal processing unit 22. The output of the synchronous word removal processing unit 22 is a dummy bit removal processing unit.
The storage device 3 and the storage device 4 are connected via 23. Storage device
3 and the output of the storage device 4 are connected to a digital data output terminal 6 'via the decoding processing unit 14. The output of the synchronous word detection processing unit 13 is connected to a timing generator 17 '. The output of the timing generator 17 'is connected to the synchronizing word removal processing unit 22, the dummy bit removal processing unit 23, the write address generator 8, the read address generator 9, the control signal generator 16', and the decoding processing unit 14. The output of the control signal generator 16 'is connected to the address switch 7, the storage device 3, and the storage device 4. Outputs of the write address generator 8 and the read address generator 9 are connected to the storage devices 3 and 4 via the address switch 7.

In FIG. 4, a digital data input terminal 1
'Inputs data, and inputs the data to the synchronous word detection processing unit 13 and the synchronous word removal processing unit 22. The synchronization word detection processing unit 13 detects the synchronization word inserted on the transmission side from the input data, and outputs the detection information to the timing generator 17 '. The timing generator 17 ′ generates the timing of the receiving-side processing from the input data, and generates a synchronizing word removal processing unit 22, a dummy bit removal processing unit 23, a write address generator 8, a read address generator 9, a control signal generation And outputs a timing output for controlling each timing of each processing on the transmission side in performing the subsequent operations. The synchronization word removal processing unit 22 removes the synchronization word from the input data according to the control information of the timing generator 17 ′, and outputs the result to the dummy bit removal processing unit 23. The dummy bit removal processing unit 23
Removes transmission bit adjustment dummy bits added on the transmission side from the input data sequence, and outputs the result to storage device 3 or storage device 4. The control signal generator 16 ′ operates the storage device 3 and the storage device 4 based on the control information of the timing generator 17 ′.
And the address switch 7 switches between the write address generator 8 and the read address generator 9 to switch the data destination. The storage device 3 and the storage device 4 perform an alternate operation in which one is a write and the other is a read similarly to the transmission side. Immediately after the operation starts, storage device 3
The following description will be made on the assumption that the storage device 4 is writing and the storage device 4 is reading. The storage device 3 writes data in accordance with the output of the write address generator 8 via the address switch 7 and the signal of the control signal generator 16 '. When the storage device 3 finishes writing the data of the interleave size and the storage device 4 finishes reading the data of the interleave size, the storage device 3 starts outputting data, and the storage device 4 starts inputting data. . At this time, the address pattern generated by the write address generator 8 is the same as the address pattern generated by the read address generator 9 on the transmission side, and the address pattern generated from the read address generator 9 is the write address generator generated on the transmission side. This is the same as the address pattern generated in 8. By this address operation, a process (deinterleaving process) for restoring the order of data by the interleaving process performed on the transmission side is realized. The coded data that has been subjected to the deinterleave processing is output to the decoding processing unit 14. The decoding processing unit 14 performs a depuncturing process of inserting a null symbol into a punctured (deleted) portion. The null symbol is data necessary for performing Viterbi decoding added by the depuncturing process. Further decryption processing unit
14, after decoding the depunctured data,
The decoded data is output to the digital data output terminal 6 '.

[0012]

In the above-mentioned prior art,
There is a disadvantage that the puncturing process can be performed only at a specific puncture rate predetermined by a product or the like. In addition, there is a drawback that additional processing of dummy bits for adjusting the transmission bit length must be performed depending on the transmission speed. An object of the present invention is to eliminate these drawbacks, realize a puncturing process capable of easily changing the puncturing rate, and provide an error correction method that does not require the addition of dummy bits.

[0013]

In order to achieve the above object, the present invention provides a puncture pattern generator for providing data deletion / pass information to both a transmitting side and a receiving side. And when the control signal generation unit writes the data to the storage device, based on the puncture pattern generated by the puncture pattern generator, compares the puncture pattern with the puncture pattern and deletes the data (data for performing the puncture process). And pass data (data without puncturing)
In this case, a puncture process is performed by generating a write address, and a null symbol previously written in the storage device is transmitted on the receiving side based on the puncture pattern of the puncture pattern generator when reading from the storage device. By doing so, a depuncturing process is performed. The puncture pattern is a puncture rate that does not require the addition of dummy bits in consideration of the transmission speed in advance. Furthermore, since the transmission rate is a constant puncture rate determined by the transmitting side, synchronization is also achieved at the receiving side, so the synchronization word insertion processing for determining the operation timing of the receiving side is performed in the storage device when the apparatus is started up. This can be realized by writing the synchronization word only once and sending it out.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 6. FIG. FIG. 1 is a block diagram illustrating an example of processing on the transmission side, FIG. 2 is a block diagram illustrating an example of processing on the reception side, and FIG. 6 is an example of a transmission data pattern.

First, an example of the configuration and operation of the transmitting side will be described. In FIG. 1, 1 is a digital data input terminal, 2 'is an encoder, 3 and 4 are storage devices, 5 is a synchronous word generator, 6 is a digital data output terminal, 7 is an address switch, and 8' is a write address generator. , 9 'is a read address generator, 10 is a control signal generator, 11 is a puncture pattern generator, and 12 is a timing generator. The digital signal input terminal 1 is connected to the digital data output terminal 6 via the encoder 2 ′, the storage device 3 and the storage device 4. The output of the timing generator 12 includes an encoder 2 ′, a synchronizing word generator 5, a control signal generator 10,
Write address generator 8 ', read address generator 9
'And a puncture pattern generator 11. The output of the control signal generator 10 is connected to the storage devices 3 and 4, and the address switch 7. The output of the synchronous word generator 5 is
Connect to storage device 3 and storage device 4. The output of the puncture pattern generator 11 is output to the write address generator 8 'and the control signal generator 10. Write address generator 8
And the output of the read address generator 9 ′
Is connected to the storage device 3 and the storage device 4 via.

In FIG. 1, when the apparatus is started up, the synchronization word generator 5 is driven by the timing generator 12 and the storage device 3 is activated.
And the synchronization word is written to the storage device 4. By making the write location of the synchronization word different from the data storage location and performing it only once at the time of device startup, the information is retained during the device startup thereafter. After the synchronization word has been written, input digital data from digital data input terminal 1 and
´. The encoder 2 'encodes one bit of the input digital data and outputs N (integer) bits. The storage device 3 and the storage device 4 follow the control of the control signal generator 10 as in the prior art, and one of them performs writing of data and the other performs reading, and the operation alternates for each interleave size as in the conventional technology. Switch.
Immediately after the operation starts, it is assumed that the storage device 3 is performing a write operation and the storage device 4 is performing a read operation. The encoded data output from the encoder 2 'is stored in the storage device 3 in accordance with the output of the write address generator 8' via the address switch 7 and the output of the control signal generator 10. At this time, the write address generator 8 ′ performs collation with the puncture pattern from the puncture pattern generator 11 and deletes data (data for performing puncture processing).
In the case of, a write address is not generated, and in the case of passing data (data not subjected to puncturing processing), a write address is generated. Further, the control signal generator 10 also checks the puncture pattern from the puncture pattern generator 11 and controls the write permission signal when data (deletion data) for performing puncturing processing is input to the storage device 3, Perform the process of interrupting the data writing. By these processes, the data to be punctured (deleted) is not written to the storage device 3, and the stored data is obtained by performing the puncturing process and sequentially storing the data. The storage of data in the storage device 3 is performed up to the data length for performing interleaving. Next, the storage device 3 outputs the stored data in accordance with the output of the read address generator 9 ′ and the output of the signal generator 10. At the same time, the synchronization word stored at the time of device startup is output after the data string. In performing the above operation, the timing of each process on the transmission side is determined by the timing generator 12.
Follow the output from As a result, the transmission data has a configuration as shown in FIG. FIG. 6 shows transmission data output from the digital data output terminal 6. The transmission data size is composed of encoded data subjected to interleaving and a synchronizing word. The punctured encoded data shown in FIG. 7 is a part of the interlib-size encoded data as shown in FIG.

An example of the configuration and operation of the receiving side will now be described. In FIG. 2, 1 'is a digital data input terminal, 13 is a synchronous word detection processing unit, 12' is a timing generator, 3 and 4 are storage devices, 14 'is a decoder, 6' is a digital data output terminal, 7 '
Is an address switch, 8 'is a write address generator, 9'
Is a read address generator, 10 'is a control signal generator, 11
Denotes a puncture pattern generator, and 18 denotes a synchronous word storage address generator. Digital data input terminal 1 '
The synchronous word detection processing unit 13 is connected to the storage devices 3 and 4. Outputs of the storage devices 3 and 4 are connected to a digital data output terminal 6 'via a decoder 14'. The output of the synchronous word detection processing unit 13 is connected to the timing generator 12 '. The output of the timing generator 12 'is connected to a decoder 14', a write address generator 8 ', a read address generator 9', a control signal generator 10 ', and a null symbol generator 19. The output of the puncture pattern generator 11 is a control signal generator
10 'and the read address generator 9'. The output of the control signal generator 10 'is a decoder 14', an address switch 7,
Connect to storage device 3 and storage device 4. The outputs of the write address generator 8 'and the read address generator 9' are connected to the storage devices 3 and 4 via the address switch 7.
The output of the null symbol generator 19 is stored in the storage devices 3 and 4
Connect to

In FIG. 2, when the apparatus is started, a null symbol generator 19 outputs a null symbol by a timing generator 12 ′ and writes the null symbol into the storage devices 3 and 4. The writing of a null symbol is performed only once at the time of startup, and the information is retained while the apparatus is being started, as in the case of writing the synchronization word on the transmission side, where the writing location is different from the data storage location. After the writing of the null symbol is completed, digital data is input from the digital data input terminal 1 '. The input data is input to the synchronous word detection processing unit 13 and is also input to either the storage device 3 or the storage device 4 under the control of the control signal generator 10 '. The synchronization word processing detection unit 13 detects a synchronization word from the input data and outputs detection information to the timing generator 12 '. The timing generator 12 'generates a processing timing on the receiving side from the input information, and outputs the processing timing to the write address generator 8', the read address generator 9 ', the control signal generator 10', and the decoder 14 '. As in the prior art, the output pattern of the write address generator 8 'is the same as the output pattern of the transmission side read address generator 9', and the output pattern of the read address generator 9 'is the same as that of the transmission side write address generator 8'. 'Is the same as the output pattern. The data stored up to the interleave size is read from the storage device 4 in accordance with the output from the read address generator 9 'via the address switch 7 and the output of the control signal generator 10'. At this time, the read address generator 9 ′ checks with the puncture pattern of the puncture pattern generator 11,
The data of the portion not subjected to the puncturing process is output as it is, and a null symbol is transmitted in the portion subjected to the puncturing process. By this depuncturing process, data in which a null symbol is inserted in the data portion punctured on the transmission side is output to the decoder 14 '. Further, the read address generator 9 'checks the output of the synchronous word storage address generator 18 and does not output the data corresponding to the synchronous word. This processing deletes the synchronization word. The data from which the null symbol has been inserted and the synchronization word has been deleted as described above is input to the decoder 14 '. The decoder 14 'performs decoding by determining the position where the null symbol is inserted from the outputs of the timing generator 12' and the control signal generator 10 '. The decoded data is output from the digital data output terminal 6 '. In performing the above operation, the timing of each process on the receiving side follows the output from the timing generator 12 '.

In the above-described embodiment, two storage devices are used for each of the transmission side and the reception side. However, one storage device is used for each of the transmission side and the reception side.
It is obvious that one or three or more storage devices may be used, and the number and functions of storage devices used on the transmission side and the reception side may be different.

As described above, according to the puncture pattern of the present invention, it is not necessary to add a dummy bit, which was conventionally required due to the difference in transmission speed, and the encoding processing unit uses the puncture pattern to reduce the transmission speed. Adjustment is possible. For example, in the case of the transmission rate shown in FIG. 3 in the description of the prior art, the transmission rate of the output of the encoding processing unit can be set to 2.5 Mbps by setting the puncture rate to 5/6. In the case of such a puncture rate represented by a simple integer ratio, the puncture rate prepared in the semiconductor integrated circuit device may be realized, but a normal semiconductor such as 303/400 may be used. In some cases, processing at a puncture rate that is not provided in an integrated circuit device is necessary, but the present invention can easily realize such processing. The change of the puncture pattern can be easily realized by, for example, replacing or rewriting the ROM by forming the puncture pattern generator with an element such as a ROM or the like whose internal data can be easily changed.

Further, the error correction system of the present invention may be used alone in the transmitter, or may be used alone in the receiver.

Further, the error correction method of the present invention can be applied not only to communication equipment for transmitting digital data, but also to audio equipment, mobile radio equipment, broadcasting equipment, transmission equipment or those equipment using digital data communication. Can be used in a system device constructed by combining.

[0023]

According to the present invention, the puncture rate can be easily changed by changing the puncture pattern generated by the puncture pattern generator at any time. Further, since the bit length adjustment for adjusting the transmission bit can be realized by the puncture pattern, the dummy bit processing can be eliminated. Further, by using a storage device, puncturing, interleaving, and synchronizing word insertion can be realized on the transmitting side, and depuncturing, deinterleaving, and synchronizing word removing can be realized on the receiving side. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a transmitting side configuration of the present invention.

FIG. 2 is a block diagram showing one embodiment of a receiving side configuration of the present invention.

FIG. 3 is a block diagram showing a configuration of a transmission side according to the related art.

FIG. 4 is a block diagram showing a configuration of a receiving side according to a conventional technique.

FIG. 5 is a diagram showing a data transmission pattern according to the related art.

FIG. 6 is a diagram showing an embodiment of a data transmission pattern according to the present invention.

FIG. 7 is a view for explaining a method of puncturing processing.

[Explanation of symbols]

1, 1 ': Digital data input terminal, 2: Encoding processing unit, 2': Encoder, 3, 4: Storage device, 5: Synchronous word generator, 6, 6 ': Digital data output terminal, 7: Address Switch, 8, 8 ': Write address generator, 9, 9
': Read address switch, 10, 10', 16, 16 ': control signal generator, 11: puncture pattern generator,
12, 12 ', 17, 17': timing generator, 13: synchronous word detection processing unit, 14: decoding processing unit, 14 ': decoder, 1
6, 16 ': control signal generator, 18: synchronization word storage address generator, 19: null symbol generator, 20: dummy bit addition processing unit, 21: synchronization word insertion processing unit, 22: synchronization word removal processing unit, 23: Dummy bit removal processing section, 31: Encoded data, 32: Puncture pattern, 33: Data after puncture processing.

Claims (6)

[Claims] In an error correction method for performing puncturing processing when transmitting digital data, a puncturing pattern generator for generating a puncturing pattern is provided on both a transmitting side and a receiving side. An error correction method in digital communication, wherein error correction is performed using a puncture pattern generated by a puncture pattern. 2. The error correction method according to claim 1, wherein
An error correction method in digital communication, wherein transmission data transmitted by a transmission side is transmission data to which a dummy bit for adjusting a transmission rate is not added. 3. The error correction method according to claim 1, wherein the puncturing process and the interleaving process on the transmitting side are performed by a write operation and a reading operation of the storage device on the transmitting side, and the depuncturing process on the receiving side is performed. An error correction method in digital communication, wherein a deinterleave process is performed by a write operation and a read operation of the receiving storage device. 4. The method according to claim 1, 2 or 3.
In the error correction method described above, a synchronizing word insertion process on the transmitting side is performed together with an interleave process by a write operation or a reading operation of the transmitting side storage device, and a synchronizing word deleting process on the receiving side is performed on the receiving side. An error correction method in digital communication, wherein the error correction method is performed together with a depuncturing process by a write operation or a read operation of a storage device. 5. A transmitter using an error correction method for performing puncturing processing when transmitting digital data, comprising: an input terminal; an encoder for encoding the digital data input from the input terminal; A storage device that performs writing and reading on the converted data, a synchronization word generator that writes a synchronization word to the storage device when the transmitter starts up, a puncture pattern generator that generates a puncture pattern, A write address generator for collating with a puncture pattern and not generating a write address for deleted data (data for which puncture processing is performed), and for generating a write address for passed data (data for which puncture processing is not performed). For interleaving data already stored in the storage device. A read address generator for generating an address, an address switch for switching either the signal of the write address generator or the signal of the read address generator to an input to the storage device by the control signal generator, and A control signal generator for controlling the device and controlling the address switch, a timing generator for generating a timing and transmitting a signal for controlling the timing of the transmitter to each processing unit of the transmitter, and a timing generator output from the storage device. An output terminal for transmitting data; punctured when encoded digital data (encoded data) is stored in the storage device; and the punctured encoded data is read from the storage device. Error correction in digital communications characterized by interleaving and addition of synchronizing words when interleaved Transmitter using a formula. 6. An input terminal for inputting digital data sent from a transmitter, and a digital data transmitted from the input terminal, wherein the receiver uses an error correction method for performing puncturing when transmitting digital data. A storage device that performs writing and reading, a null symbol generator that generates a null symbol when the receiver starts and writes a null symbol to the storage device, and a synchronization device that detects a synchronization word from digital data at the input terminal. A word detection processing unit, a timing generator for generating a timing of a receiver from the synchronization word and transmitting a signal for controlling the timing of the receiver to each processing unit of the receiver, and a puncture pattern generator for generating a puncture pattern A control signal generator for controlling the storage device; and a synchronizing word storage for generating an address of the synchronizing word. An address generator, a write address generator for generating an address for deinterleaving data to be input to the storage device, and inserting the null symbol into a data portion that has been subjected to puncturing by comparing with the puncturing pattern A read address generator for generating an address for the storage device and a signal from the control signal generator for determining whether a signal to be input to the storage device is a signal of the write address generator or a signal of the read address generator. An address switch for switching, a decoder for determining and decoding the position of a null symbol of data output from the storage device based on outputs from the timing generator and the control signal generator, and a signal from the decoder Has an output terminal for outputting digital data from the transmitter. A deinterleaving process is performed when the digital data is stored in the storage device, and a null symbol is inserted and a synchronization word is deleted when the deinterleaved digital data is read from the storage device to the decoder. A receiver using an error correction method in digital communication.