JPH03126320A - Serial/parallel type analog/digital converter - Google Patents

Abstract

PURPOSE:To reduce a conversion error and to improve the accuracy by providing an extraposition circuit discriminating the level of an analog signal based on a threshold level set at the outside of an input voltage range in an interpolation circuit. CONSTITUTION:A threshold level at the outside of an input voltage range of an interpolation circuit 127 is set to an extraposition circuit 999 and the level of an analog input voltage is discriminated based on the threshold level. Thus, even when an analog input voltage subject to sample and hold processing stays at the outside of the input voltage range of the interpolation circuit 127 with a drift while A/D conversion is implemented, the drifted analog input voltage is converted into a digital signal while keeping the linearity in an excellent way. That is, the dynamic range in the conversion after 2nd and succeeding stages is expanded, resulting in enabling the conversion with excellent linearity. Thus, the accuracy of A/D conversion is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a series-parallel type analog/digital converter.

[Conventional technology]

Conventionally, various analog/digital converters (hereinafter referred to as "A/D converters") have been used to perform digital signal processing. Among them, the analog human input signal is sampled using a sample-and-hold circuit, the analog voltage is held, and the analog signal is converted into a multi-bit digital signal by performing multi-step conversion within this holding period. The series-parallel type A/D converter is characterized by its small size and low power consumption.

FIG. 7 is a block diagram showing the basic configuration of a conventionally used serial-parallel type A/D converter.

In this A/D converter, an analog input signal from an input voltage 105 is subjected to two-stage conversion, and a 4-bit digital signal is derived as an output voltage 106.

The analog input signal from the input voltage 105 is compared in the comparator Co-C4 with each voltage at the voltage division points lOO to 104 in the reference resistor group R□, which is made up of resistors 1 to 4 having the same resistance value. Ru. In this example, the partial pressure point 1
04 is at ground potential, and voltage dividing points 103 to 100 are at negative potential □.

In each comparator Co-C4, each voltage dividing point 100-104 is connected to a non-inverting input voltage, and an analog input signal is provided to each inverting input voltage. That is, each comparator C0-
C4 outputs an L level signal if the analog input signal is higher than the potential of each voltage dividing point lOO-104, and outputs an H level signal in the opposite case.

The output signals of comparators 01 to C4 are each output to AND gate A.
The input voltage is applied to each one of N1 to AN4. A
The output signals of the comparators C0-C5 are inverted and input to the other input voltages of the ND gates ANI-AN4, respectively.

The outputs of the AND gates ANI to AN4 are given to the first code assignment circuit 135, and the first code assignment circuit 135
The code of the upper 2 bits of the analog input signal is assigned at , and the code of the upper 2 bits is input to a third encoding circuit 123 to be described later. Said AND game) AN
The first encoding circuit 121 includes the 1-AN 4 and the first code assignment circuit 135.

An analog input signal from input voltage 105 is applied to voltage divider point 10
Together with the voltages derived from 0 to 104, they are applied to differential current generators OPO to OP4. This differential current generator OP
O~OP4 each output a differential current corresponding to the difference between the signal applied to the non-inverting input voltage and the signal applied to the inverting input voltage, and the positive phase differential current is connected to each output voltage opo'~
At the same time, currents of opposite phases are derived to each output voltage 0PO- to 0P4-.

The currents drawn to the output voltage OP4'0P4- of the differential current generator OP4 are respectively connected to lines Lll through transistors 41 and 42 which are controlled on/off by an AND gate AN4.

It is applied to the i current/voltage conversion circuit 126 via this line Lll and L12.

Further, the current from the differential current generator OP4 is controlled on/off by the AND gate AN3.
32 to lines Lll, L12 and via transistors 33.34 controlled by AND gate AN4 to lines L13. It is also given to L14. Line L13. The current led to L14 is applied to the current/im pressure conversion circuit 126. Similarly, the current from the differential current generator OP2 is applied to lines Lll and L12 via transistors 21 and 22, which are controlled by the signal from the AND gate AN2, and are also controlled by the signal from the AND gate AN3. transistor 23
．． 24 to line L13°L14. Furthermore, the same applies to the differential current generator OPI, whose current is applied to lines Lll and L12 via transistors 11 and 12 based on the signal from the AND gate ANI, and based on the signal from the AND gate AN2. Line L13. via transistors 13.14. Given to L14. Also, the current from the differential current generator OPO is AN
It is applied to lines L13 through L14 via transistors 5 and 6 which are controlled by a signal from the D gate ANI.

Each differential current output voltage of the differential current generators 0PO-OF2 is also connected to the transistors Ta, 7b; 10a, lOb, respectively.
;20a, 20b;30a, 30b;40a.

It is connected to ground line LIO via 40b.

These transistors are controlled by signals from logic circuit group 145, for example transistors 7a, 7b associated with differential current generator OPO are controlled by AND gate AN1.
It is controlled by a signal obtained by inverting the output signal of . Transistor 10a associated with differential current generator OPI.

10b is controlled by a signal from a NOR gate 141 to which the outputs of AND gates ANI and AN2 are applied, and transistors 20a and 20b are controlled by AND gates AN2. AN
Transistors 30a, 30b are controlled by a signal from a NOR gate 142 to which the output of AND gate AN3. NOR gate 1 to which the output of ANA is given
43 is controlled by j21. The transistors 40a and 4Ql) are controlled by a signal obtained by inverting the output of the AND gate AN4 by an inverting circuit 144.

With this configuration, five differential current generators OPO~
The differential current generated from OP4 is switched by a current switching circuit 125 composed of a group of transistors connected to these output terminals and is applied to a current/voltage conversion circuit 126. The current switching circuit 125 is, for example, an AND game) A
When the output of N4 is at H level, two differential current generators OP4. Only the output current of OP3 is on the line Lll~L
14 to the current/voltage conversion circuit 126, and the output currents of the differential current generators OPO to OP2 are connected to the ground line LIO.
Each differential current generator OPO~
Switch the output current of OP4 (details will be described later).

In this way, line Lll-L14 has partial pressure point 1
00 to 104, a voltage at two adjacent voltage dividing points uniquely determined by the analog input voltage and a current generated depending on the analog input voltage flow.

The current given to the current/voltage conversion circuit 126 from the lines Lit to L14 is linearly converted to voltage, and
It is applied to the interpolation circuit 127 from L4. Based on the signal from this interpolation circuit 127, the second encoding circuit 1
22, the code of the lower two bits is assigned. The code of the lower 2 bits from the second encoding circuit 122 and the code of the first
The code of the upper two bits from the encoding circuit 121 is the third
This third encoding circuit 123 arbitrates the codes of the upper 2 bits and lower 2 bits, and outputs a 4-bit digital signal as the digital signal output voltage 106. 4-bit analog/digital conversion is completed.

FIG. 8 is a characteristic diagram showing the dependence of the differential currents output by the differential current generators OPO to OP4 on the analog input voltage. In this Fig. 8, the curves fO”, !!, l
", 12"", !!, 3°, 14" are differential current generator O
Each differential current output voltage OPO” of PI to OP4, OP1
”, OP2”, OP3°, and OP4°, and curves 10-, lII! ,2-,ff1
3-. 14- is the differential current output voltage 0PO-.

OP l-,0P2-. 0P3-. It shows the differential current derived from 0P4-. In addition, FIG. 8 shows the partial pressure point 100.
Voltage at ~104■1°. 〜■1°4 are shown at the same time, and the voltage at the voltage dividing point 104 is ■,. 4 is the ground potential, and the voltage vies + v+@l + Vllll
＋■、. . The voltage is the lowest (negative voltage) in this order.

The complementary differential currents derived by each of the differential current generators OP4 to OPO are the voltages of the analog input voltages ■1°4. ■１゜１． ■１゜８． ■The magnitude relationship is reversed at 1°l and VI6°.

FIG. 9 is a diagram for explaining the operation, and shows the output signals of the comparators CO to C4 and the AND
Changes in the output signals of gates ANI-AN4 are shown, respectively. In FIG. 9, the voltages mentioned above are shown. . ~■1゜4
are shown at the same time.

As shown in FIGS. 9(1) to (5), as the analog input voltage decreases, the comparators 04 to CO sequentially invert their outputs from L level to H level. Along with this, the outputs of the AND gates ANI to AN4 are as shown in FIG. 9 (6) to
As shown in (9), one of them becomes H level, and the outputs of the remaining AND gates become L level. For example, the analog input voltage is voltage V. When the value is between 3 and ■1°, the outputs of comparators C3 and C4 become H level, and the outputs of comparators CO to C2 become L level, so an L level signal is applied to the inverted input voltage. Since only the AND gate AN3 receives an H level signal as a non-inverted input voltage, only the output of this AND gate AN3 becomes H level. In this way, the voltage v1°4 to v1°. AND gates AN1 to A for analog input voltages between
Four types of signals are given from N4 to the first code assignment circuit 135, and therefore a 2-bit code "00" is assigned to this signal.
”, “01°“10”, and “11”, the upper two bits can be encoded.

FIG. 10 shows the interpolation circuit 127 and the second encoding circuit 12.
FIG. 2 is an electric circuit diagram showing the internal configuration of No. 2.

The voltage between lines Ll and L3 is divided by a first interpolation voltage generating resistor group R□ consisting of a plurality of resistors 251 to 254 having the same resistance value, and the potentials appearing at the voltage dividing points 171 to 175 are compared respectively. It is applied to each non-inverting input voltage of the circuits CI1 to C15.

Also, line L2. Similarly, the voltage between L4 is divided by the second interpolation voltage generation resistor group R12, which is composed of resistors 261 to 264 having the same resistance value, and the voltage between voltage dividing points 181 to 264 is divided by the second interpolation voltage generation resistor group R12.
The potentials appearing at 185 are respectively the comparators C11-Cl.
3 are given to each inverting input voltage.

The output of the comparator C1l is applied to the AND gate ANII and also to the inversion circuit 111, and these outputs are applied to the second code assignment circuit 129. In addition, each output signal of the comparators CI2 to C14 is AND
It is applied to gates AN12 to AN14, and AN
The signals are inverted and input to D gates ANII-AN13, respectively. The output signal of the comparator C15 is inverted and input to the AND gate AN14. AND gate ANII
- Each output of AN14 and the output of comparator C15 are also input to the second code allocation circuit 129. The second encoding circuit 12 includes the second code assignment circuit 129, the inversion circuit Ill, and the AND gates ANII-AN14.
2 are configured.

FIG. 11 shows the interpolation circuit 127 and the second encoding circuit 12.
2 is an explanatory diagram for explaining the operation of No. 2, in which changes in voltage at voltage dividing points 171 to 175 degrees and 181 to 185 with respect to analog input voltage are respectively curved! 71~ff175. 18
1 to ff185. However, in FIG. 11, VR and Vfi- are the adjacent two points of the voltage dividing point group 100 to 104 of the reference resistor group R□ in FIG.
It represents the voltage at two voltage dividing points, and furthermore, V, (
1), V, (2), V, and (3) are the voltages at the four-ring voltage division point between voltage 7 and VR-+, respectively. In this way, between lines Ll, , L3, L2 . An interpolation voltage is generated to interpolate the voltage between L4, and this interpolation voltage is used to encode the lower two bits of the analog input voltage between voltages V, , V□-6.

FIG. 12 is an explanatory diagram for explaining the interpolation operation, and shows output signals of each section in FIG. 10 in response to an analog input signal. FIG. 12 (1) shows the output signal of the inversion circuit Tll, and FIG. 12 (2) to (5) show the AND gate AN.
II to AN14 output signals are shown, and FIG. 12 (6) to O
I indicates the output signal of comparators C11-Cl3. As shown in FIG. 11, voltage division points 171.181; 172°182; 173.183;
The potentials appearing at 74, 184; 175, 185 show complementary changes, and the voltage v taken by the analog input voltage,
.

V, (1), V, (2), V,, (3), v
, -, and D, the respective magnitude relationships are reversed. Therefore, the comparators C11 to Cl3 each have a voltage value V, which the analog input voltage takes.

The output is changed between H level and L level with V, (1), V, (2), V, (3), and V, - as boundaries.

Upon receiving the outputs of such comparators CIl to C15, AN
At most one of the output signals of the D gates ANII to AN14 becomes H level at the same time. Therefore AN gate ANI
Corresponding to the case where each output signal of the I-AN14 goes to H level, the codes of the lower 2 bits are "00", "0 bit, '10", and 'l bit (however, among the 2 bit codes, ,
The left side is the higher-order code. ), and further borro the output of the inversion circuit 111 by 1 to the upper order.
w and assigns "11", and carries only 1 bit to the higher order with respect to the output of comparator C15, and carries L/and "00".
Encoding is done by assigning ``.

The state of this encoding is shown in Figure 13, where θ ~
A discrete value of 3 is assigned, and for analog input voltages lower than this range -1 (borro by 1 from the top)
Assign the code "11" to w L/. ) is assigned, and for an analog input voltage higher than the above range, 4 (carry 1 to the higher order and assign the code "00") is assigned. In this way, the dynamic range of the encoding in the second stage is extended by 2 LSBs compared to the minimum unit of transformation (V-""V, , -1) in the first stage.

By expanding the dynamic range of encoding in the second stage conversion, for example, the sample and hold circuit inserted before the A/D converter (
Even if the analog input voltage held by the A/D (not shown) drifts in a certain direction by a certain amount less than ILSB between the first-stage conversion period and the second-stage conversion period, the A/D
Since linearity of conversion can be maintained, digital correction of the above-mentioned drift becomes possible. This will be explained in more detail using FIG. 14.

In FIG. 14, the first reference axis xl indicating the analog input voltage indicates the true analog input voltage, and the second reference axis
shows the analog input voltage after drift. Also,
V! TEP indicates l LSB.

In the example shown in FIG. 14, the analog input voltage is I L
It drifts toward the ground potential by an amount corresponding to SB, and as a result, the sign is assigned to be shifted by one with respect to the true value of the analog input signal. However, the width of each quantization step is equal, so linearity is maintained. In the second stage of conversion, there are four dynamic ranges (V+.4
~V,. 1. vl. .

~v1゜2. ■,. 8～■1゜1. ■,. , ~v1゜,
), but the above-mentioned drift occurs in a fixed direction over all this dynamic range, and the width of the quantization step can be made equal in each case, so that the above-mentioned borro- from the lower two bits to the upper two bits and ( By digital correction using the signal of arry, it is possible to prevent deterioration of linearity of A/D conversion.

[Problem to be solved by the invention]

However, in the prior art as mentioned above, the said drift)
When I exceeds ILSB, digital correction cannot be performed by borrowing from the lower 2 bits to the upper 2 bits (, arry alone, and deterioration of the linearity of A/D conversion is unavoidable. Fig. 15 is an explanatory diagram showing an example of a case where linearity deterioration occurs, and the illustration is similar to Fig. 14. In the case of Fig. 15, 2LSB is applied to the analog input voltage. There is a drift of (v11+Vstip) in such a case.
(!l” (V, l+2・■, .P) cannot be assigned a different sign, which results in a difference in the width of the quantization step, which deteriorates the linearity of A/D conversion. It turns out.

An object of the present invention is to provide a series-parallel type analog/digital converter that solves the above-mentioned technical problems, reduces conversion errors, and improves accuracy.

[Means to solve the problem]

The series-parallel analog/digital converter of the present invention performs analog/digital conversion operation in multiple stages,
In a series/parallel analog/digital converter in which at least one stage of analog/digital conversion after the second stage is performed using an interpolation circuit that discriminates the level of an analog input voltage based on a plurality of threshold values, the input to the interpolation circuit is The present invention is characterized in that it includes an extrapolation circuit that sets a threshold value outside the voltage range and performs level discrimination of an analog input signal based on this threshold value.

[Effect]

According to the configuration of the present invention, in the extrapolation circuit, a threshold value outside the input voltage range of the interpolation circuit is set, and level discrimination of the analog input voltage is performed based on this threshold value, so that, for example, analog/digital conversion is performed. Even if the sampled and held analog input voltage drifts outside the input voltage range of the interpolation circuit during the period, the drifted analog input voltage can be converted into a digital signal while maintaining good linearity. You will be able to do this.

That is, as a result of expanding the dynamic range in the conversion operations from the second stage onwards, it becomes possible to perform conversion operations with good linearity, thereby making it possible to improve the accuracy of analog/digital conversion.

〔Example〕

FIG. 1 is a block diagram showing the basic configuration of a serial/parallel type A/D converter according to an embodiment of the present invention. In FIG. 1, parts corresponding to those shown in FIG. 7 described above are given the same reference numerals.

In this example, the current drawn into lines L1-L4 /
The output of voltage conversion circuit 126 is applied to interpolation circuit 127 and also to extrapolation circuit 999 for expanding the range of quantization regarding the lower two bits. and the second
The encoding circuit 1122 receives the outputs of the interpolation circuit 127 and the extrapolation circuit 999 and generates a code for the lower two bits.

FIG. 2 shows an extrapolation circuit 999 and a second encoding circuit 112.
FIG. In FIG. 2, parts corresponding to those shown in FIG. 10 described above are designated by the same reference numerals. The configuration of interpolation circuit 127 is similar to that shown in FIG.

The extrapolation circuit 999 connects the first
The extrapolated voltage generating resistor group R1, and the line L2. A second extrapolation voltage generation resistor group R2 is connected between L3 and L3. That is, two extrapolation voltage generating resistor groups R1 and R2 are provided which respectively connect the non-complementary and asymmetrical voltage output terminals of the output terminal group of the current/voltage conversion circuit 126. The extrapolated voltage generation resistor groups R1 and R2 are resistors 271 to 276°28 each having the same resistance value.
Consists of 1 to 286, 151 to 155°161
~165 is a partial pressure point.

The potential at the voltage dividing point 151 to which the voltage from the line L1 is applied via the resistor 271 is applied to the non-inverting input voltage of the comparator CIO, and the voltage from the line L2 is applied via the resistor 281. The potential appearing at the voltage dividing point 161 on the side of the second extrapolated voltage generating resistor group R2 is applied to the inverted input voltage of the comparator CIO. Further, in the first extrapolated voltage generating resistor group R1, the potential appearing at the voltage dividing point 155 to which the voltage of the line L4 is applied via the resistor 276 is applied to the inverting input voltage of the comparator C16, and the second In the extrapolated voltage generating resistor group R2, the potential appearing at the voltage dividing point 165 to which the voltage of the line L3 is applied via the resistor 286 is applied to the non-inverting input voltage of the comparator C16.

The output of comparator CZ is applied to AND gate ANII, and is also inverted and input to AND gate ANIO. This AND game 1-ANIO has the extrapolation circuit 999.
The output of comparator CIO is given, and this comparator C
The output of 1O is further provided to an inverting circuit 110. Also, in the interpolation circuit 127, line L2. The output of comparator C15 connected to L4 side is AND gate AN
15 is input. And this AND gate AN1
5 is also provided with an inverted output signal of the comparator C16 of the extrapolation circuit 999. The output of this comparator C16 is also given directly to the second code assignment circuit 129.

FIG. 3 is an explanatory diagram showing changes in the voltages derived to each part of FIG. 2 with respect to the analog input voltage.

Curves 111 to 275 indicate the voltages at the voltage dividing points 171 to 175 on the first interpolation voltage generation resistor group R1 side of the interpolation circuit 127, and curves 1B1 to ff185 indicate the voltages at the second interpolation voltage generation resistors. Partial pressure point 181-1 on body Rag side
85, respectively. That is, curves that are the same as those shown in FIG. 11 described above are given the same reference numerals. FIG. 3 shows the first extrapolation voltage generating resistor group R in the extrapolation circuit 999.
The voltage changes at the voltage dividing points 151 and 155 on the 1 side are shown by curves 151 and ff155, and the voltage at the voltage dividing points 161 and 165 on the second extrapolated voltage generating resistor group R2 side is shown by the curve 161. ．． Tail indicated by ff165. Also, in the figure, V,, V-+, V, (1), and V, 1 (2).

V,1 (3) respectively indicate voltages similar to those shown in FIG. This is the voltage determined by the external component.

As shown in FIG. 3, the curve 151°ff161
intersect when the analog input voltage becomes the voltage ■1llll, and the curve 155. For ff165, the analog input voltage is voltage ■. Intersect when . This result comparator CIO,
The outputs of C16 are each inverted when the respective analog input voltages are at voltages V n1ar VRb, thus creating the signals necessary for dynamic range expansion.

FIG. 4 is an explanatory diagram showing changes in signals derived to each section shown in FIG. 2 with respect to an analog input signal. FIG. 4(1) shows the output signal of the inverting circuit 110, and FIG.
) to (7) are AND games respectively) ANIO to AN15
Fig. 4 (8) to 04) shows the output signal of comparator 01.
The output signals of 0 to C16 are shown respectively. In addition, in FIG. 4, the voltage V +'+avll V shown in FIG.
R(1), Vll(2), Vll(3), Vl
1-1 and Vnb are shown simultaneously.

The outputs of the comparators CIO to C16 are analog input voltages Vh, , V, , V, (1), V, (2), V, , respectively.
(3).

Since the voltage changes between H level and L level with vn-+ + vnb as the border, the inverting circuit 110 corresponds to this.
The output signal of is voltage V. , becomes H level for an analog input voltage higher than . and AND gate ANIO-
The output of AN15 is that the analog input voltage is voltage V,
, ~V,; V, ~V, (1); V, (1) ~
V, (2) iV, (2)-v, (3);
V, (3)~V11-1; Vllll-1~V
When it is nb, it becomes H level. That is, at most one of the eight signals applied to the second code assignment circuit 129 becomes H level in response to the analog input signal. Therefore, eight codes can be assigned depending on which signal is at H level.

For example, for each output of AND gates ANII to AN14, the code of the lower two bits of A/D conversion is "00".
”, ’0bi, ’10”, and ’1bi are assigned, and the output of the inverting circuit 110 is borred by 1 to the upper bit.
ow l, and °′10”, AND gate A
borro by 1 to the upper bit for the output of N 10
Assign w Lt and "11", AND game) AN
Carry 1 to the upper bit for the output of 15 j
, and "OO", and by assigning only 1 carry L/ and "01" to the upper bit of the output of the comparator C16, encoding is performed.

The state of this code assignment is shown in Fig. 5, in which discrete values from -2 to 5 vary with the same quantization step width between the voltage 71 and the voltages v, , b with respect to the analog input voltage. is assigned. In this way, the dynamic range in the second stage conversion is the smallest unit of the first stage conversion (
V, ~■, -2) is extended by 4 LSBs.

The outputs of the first encoding circuit 121 and the second encoding circuit 1122 are determined as described above, and the output signals of these circuits are transmitted to the third encoding circuit 1123 (see FIG. 1,
) is given to This third encoding circuit 1123 inputs the code of the upper 2 bits, lower 2 bits, and bor.
By arbitrating the ro- or carry signal, a 4-bit signal is output as the digital signal output voltage 106. In this way, 4-bit A/D conversion is completed.

As described above, according to this embodiment, the voltage generated as an input to the interpolation circuit 127 is also given to the extrapolation circuit 999, so that new threshold values (V, , V, , ) can be set to the interpolation circuit 127.
By adding a small number of elements, the range of analog input voltages that can be converted in the second stage can be expanded more than before. This allows, for example, conventional A
Even if a conversion error as shown in FIG. 15 occurs in the A/D converter, the A/D converter of this example
The same illustration as in FIG. 5 is made. ), conversion errors can be corrected. In other words, by expanding the analog input voltage range that can be converted in the second stage,
A sample-and-hold circuit in the front stage of the A/D converter applies I to the analog input voltage during the A/D conversion period.
Even if a drift exceeding the LSB occurs, it becomes possible to equalize the width of the quantization steps and realize A/D conversion with good linearity. As a result, A/D
It is possible to reduce errors in the conversion and improve its accuracy.

〔Effect of the invention〕

As described above, according to the series/parallel type analog/digital converter of the present invention, a threshold value outside the input voltage range of the interpolation circuit is set, and level discrimination of the analog input voltage is performed based on this threshold value. /During the digital conversion operation, even if the sampled and held analog input voltage drifts outside the input voltage range of the interpolation circuit, this drifted analog input voltage can be processed while maintaining good linearity. It becomes possible to convert it into a digital signal. In other words, the dynamic range of the conversion operation from the second stage onwards is expanded, making it possible to perform conversion operations with good linearity.
It becomes possible to improve the precision of digital conversion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of an analog/digital converter according to an embodiment of the present invention, FIG. 2 is an electric circuit diagram showing the detailed configuration of a part of the converter, and FIG. 3 is a block diagram showing the basic configuration of an analog/digital converter according to an embodiment of the invention. FIG. 4 is an explanatory diagram showing the operation of each part in FIG. 2 in response to changes in analog input voltage. FIG. FIG. 6 is an explanatory diagram showing code assignment when the analog input voltage drifts. FIG. 7 is a block diagram showing the basic configuration of a conventional serial-parallel analog/digital converter. 8 is a characteristic diagram showing the output characteristics of the differential current generators OPO to OP4 shown in FIG. 7, FIG. 9 is an explanatory diagram showing the operation of each part in FIG. 7, and FIG. An electric circuit diagram showing a part of the detailed configuration; FIG. 11 is an explanatory diagram showing changes in voltage of each part in Fig. 1θ with respect to analog input voltage; FIG. 13 is an explanatory diagram showing the state of code assignment in the second stage conversion, and FIGS. 14 and 15 are explanatory diagrams showing the state of code assignment when a drift of the analog input voltage occurs.121...・First encoding circuit, 1122...Second encoding circuit, 1123・
...Third encoding circuit, 127...Interpolation circuit, 999
... Extrapolation circuit ↑ Figure 1゜Figure

Claims (1)

[Claims] An interpolation circuit that performs an analog/digital conversion operation in multiple stages, and in which at least one stage of analog/digital conversion after the second stage discriminates the level of an analog input voltage based on a plurality of threshold values. In the series-parallel analog/digital converter that is used, an extrapolation circuit is provided that sets a threshold outside the input voltage range of the interpolation circuit and discriminates the level of the analog input voltage based on this threshold. Characteristic series-parallel analog/digital converter.