JPH02272970A - Data processing circuit - Google Patents

Abstract

PURPOSE:To reduce a transmission data quantity by dividing a block for conversion encoding into small blocks and executing a sorting in the unit of the small block. CONSTITUTION:The circuit is equipped with a circuit 3 to divide plural coefficient data into plural second blocks smaller than first blocks, level detecting circuits 10 and 11 to detect level signals for second blocks, a block sorting circuit 14 to rearrange plural second blocks in the order of the magnitude of the level signal, a selecting circuit to select the coefficient data of the prescribed number of the second blocks among the coefficient data to belong to the rearranged second blocks, and an encoding circuit 24 to encode a selecting circuit output data. The coefficient data generated by the conversion encoding are divided into plural blocks smaller than the former blocks, the sorting is executed in the unit of the divided block, and the sorting is executed by a sample unit. Thus, a efficient data compression can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention applies two-dimensional cosine transform (discrete cosine transform) to a digital image signal.
The present invention relates to a data processing circuit that compresses the amount of data by encoding using two-dimensional transform encoding such as +w).

(Summary of the Invention) In the present invention, in a data processing circuit that processes a plurality of coefficient data obtained by orthogonally transforming a first block consisting of a plurality of pixels,
divided into a plurality of second blocks smaller than the block of
Detecting a level signal for each second block, rearranging the plurality of second blocks in the order of the magnitude of the level signal, and detecting a predetermined number of second blocks among the coefficient data belonging to the rearranged second blocks. By selecting the coefficient data of , and encoding the selected data, it is possible to increase the compression rate of transmission data with a simple configuration.

[Conventional technology]

In order to suppress the redundancy of image signals, transform coding is known in which the screen is divided into blocks each consisting of a predetermined number of pixels, and each block is linearly transformed using a transform axis that matches the characteristics of the original image signal. . Hadamard transform, cosine transform, etc. are known as transform encoding. A conventional cosine transform encoding device has a configuration as shown in FIG. 15, for example.

In FIG. 15, a sampled discrete image signal f (j, k) is supplied to an input terminal indicated by 81,
This input signal is supplied to a cosine transform (DCT transform) circuit 82. The cosine transform circuit 82 performs two-dimensional cosine transform. In the two-dimensional cosine transformation, processing shown by the following equation is performed. However, the original data is two-dimensional data f(j, lc) of (nXn) samples in one block.
(j+=0, 1+ 1.-9n-1).

n & J −v u+ y:Q+ L 01. The coefficient values F (u, v) from the +n-1 cosine transform circuit 82 are supplied to the block scanning circuit 83, and the coefficient data within the block is zigzag from the DC component toward the high frequency component, as shown in FIG. Output by scanning.

In FIG. 16, 0.1, 2.3. The numerical values written as ... are considered to be addresses associated with each data.

Coefficient data from block scanning circuit 83 is supplied to requantization circuit 84 . In the requantization circuit 84, the coefficient data is quantized in the quantization step from the buffer control circuit 88. The output signal of the requantization circuit 84 is supplied to a sorting circuit 85. In the sorting circuit 85, after the coefficient data is sorted in the order of the absolute value of the amplitude, both the amplitude and the address are differentiated. The difference signal from the sorting circuit 85 is supplied to a variable length encoding circuit 86. The variable length encoding circuit 86 converts the signal into a code signal of a predetermined number of bits by run length encoding and Huffman encoding.

A code signal from variable length encoding circuit 86 is supplied to buffer memory 87 . Buffer memory 87 is provided to convert the transmission rate of the code signal from variable length encoding circuit 86 to a rate within a range that does not exceed the rate of the transmission path. Although the data rate on the input side of the buffer memory 87 is variable, the data rate on the output side of the buffer memory 87 is approximately constant. buffer memory 87
Output data from is taken out to terminal 89. In the buffer memory 87, a fluctuation in the amount of transmitted data is detected,
The detection signal is supplied to buffer control circuit 88.

The buffer control circuit 88 controls the quantization step of the requantization circuit 64 and also controls the sorting circuit 85.
The coefficient data to be transmitted is controlled to have a predetermined amount of data by thresholding. Thresholding is a process of subtracting a threshold value from coefficient data whose absolute value is greater than the threshold value. However, the DC component coefficient data F(0,0) is excluded from the thresholding.

Feedback type buffering as described above reduces the rate of input data to the buffer memory 87 when the buffer memory 87 is about to overflow.
Conversely, when the buffer memory 87 is about to underflow, the buffer control circuit 88 feedback-controls the quantization step and threshold so as to increase the rate of input data to the buffer memory 87.

[Problem to be solved by the invention]

In conventional data processing circuits, there is only one method for outputting coefficient data obtained by DCT transformation: the zigzag method. Therefore, depending on the location where the two-dimensional DCT spectrum is concentrated, the difference value of the address sorted by amplitude may be output. has a large value, and even when this difference value is variable-length encoded, there is a problem in that the amount of information is not sufficiently reduced.

Therefore, an object of the present invention is to provide a data processing circuit that can reduce the amount of transmitted data by dividing a block for transform encoding into small blocks and sorting in units of small blocks. be.

[Means to solve the problem]

In this invention, in a data processing circuit that processes a plurality of coefficient data obtained by orthogonally transforming a first block consisting of a plurality of pixels, the plurality of coefficient data is
A circuit 3 that divides the plurality of second blocks into a plurality of second blocks smaller than the block, a level detection circuit 10.11 that detects the level signal of each second block, and a level detection circuit 10.11 that detects the level signal of each second block; A block sorting circuit 14 for rearranging into @, a selection circuit for selecting a predetermined number of coefficient data of the second block from among the coefficient data belonging to the second block rearranged by the block sorting circuit 14, and an output of the selection circuit. An encoding circuit 24 for encoding data is provided.

[Operation] Coefficient data of AC components that have been subjected to orthogonal transformation, for example, DCT, are divided into divided blocks obtained by dividing the block for DCT. The cumulative sum of coefficient data is detected for each divided block, and the divided blocks are sorted according to the size of this cumulative sum.The coefficient data rearranged in the order of 0 divided blocks is sorted in units of samples. By processing the zero-division block sorting in which the difference values of the sorted data are encoded using variable length coding, the position where the spectral energy is concentrated can be determined, and the difference value of the address can be prevented from becoming large.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This explanation is made according to the following items.

a. One embodiment Sorting circuit C1 Other embodiments d5 Still other embodiments a.-Embodiment FIG. 1 shows an embodiment of the present invention. In FIG. A digital image signal is supplied to a cosine transform (DCT transform) circuit 2. In the DCT conversion circuit 2, OCT conversion is performed for each (8×8) two-dimensional block of 8 pixels in the horizontal direction and 8 lines in the vertical direction, for example. An (8×8) coefficient table corresponding to the block size is obtained from the cosine transform circuit 2. This coefficient table is supplied to the array conversion memory 3.

A counter 5 is stored in the array conversion memory 3 via a selector 4.
A write address that changes sequentially from ROM 6 and a read address from ROM 6 are selectively supplied. counter 5
The address signal generated in is supplied to ROM6, and the ROM
At the read address from 6, from array conversion memory 3,
Coefficient data is output in the order of divided blocks obtained by dividing the original DCT block.

Figure 2 shows a divided block formed from (8x8) blocks for DCT. The enclosed numbers indicate the divided block numbers. The DC component indicated by * is outputted first from the array conversion memory 3. Next, coefficient data is outputted in order from 0 of the divided block number. Within each divided block, coefficient data is arranged in the array conversion memo I73 in the order of addresses within the block.
is output from.

The coefficient data from the array conversion memory 3 is supplied to the weighting circuit 7. The weighting coefficient data from the ROM 8 is supplied to the weighting circuit 7. The read address generated in the ROM 6 and the information amount control signal from the buffer controller 40 are supplied to the ROMB as addresses. R.O.
For the weighting read from the MB, each coefficient data is multiplied by a coefficient, and the number of transmission bits of the coefficient data is controlled so that the amount of transmitted information does not exceed the capacity of the transmission path.
In addition to multiplication, nonlinear requantization may be performed for weighting.

For weighting, the output signal of the circuit 7 is supplied to the absolute value conversion circuit 9 and the array conversion memory 20. The coefficient data converted into absolute values by the absolute value conversion circuit 9 is supplied to the addition circuit 10. The output signal of the adder circuit 10 is supplied to the register 11, the output signal of the register 11 is supplied to the register 12, and is also fed back to the adder circuit 10. 13 indicates a block number counter that generates the divided block number (0 to 7), and the output signal of this counter 13 is sent to register 1.
1, both of which are supplied as a clear signal are supplied to the register 12 as a clock. Therefore,
The adder circuit 10 and registers 11 and 12 constitute an accumulation circuit, and the register 12 stores the cumulative sum of coefficient data for each divided block.

The cumulative sum of each of the eight divided blocks is obtained from the register 12, and the series of this cumulative sum and the block number from the counter 13 are respectively sent to the sorting circuits 15 and 16 of the block sorting circuit 14 shown surrounded by broken lines. Supplied. In the sorting circuit 15, the cumulative sums of the eight divided blocks are sorted in descending order, and the numbers of the divided blocks are sorted in the order of increasing cumulative sums.
The sorted divided block numbers rearranged by 6 are supplied to the ROM 23 and the variable length encoding circuit 24.

For weighting, an address is supplied via a selector 21 to an array conversion memory 20 to which the output signal of the circuit 7 is supplied. The selector 21 is supplied with the write address from the address counter 22 and the read address from the ROM 23. The sorting circuit 16 supplies the ROM 23 with data of sorted divided block numbers. Coefficient data is written into the array conversion memory 20 in sequence, and read out in the order of the blocks with the largest cumulative sum. Further, from the array conversion memory 20, among the eight divided blocks included in the DCT block, only the coefficient data of five blocks with large cumulative sums are read out, and the coefficient data of three blocks with small cumulative sums are read out. The coefficient data of is excluded from the transmission data. This thresholding process compresses the amount of information.

The DC component in the coefficient data read from the array conversion memory 20 is supplied to the variable length encoding circuit 24, and the AC component is supplied to the absolute value conversion circuit 25.

The AC component of the coefficient data converted into an absolute value is supplied to a sorting circuit 27 of a sample sorting circuit 26 shown surrounded by a broken line. An address generation circuit 29 is provided, and generated addresses are supplied to a sorting circuit 28. This address corresponds to all coefficient data included in the five divided blocks. In the sample sorting circuit 26, the coefficient data of the five divided blocks to be transmitted are arranged in ascending order, and the addresses are also rearranged according to this coefficient data.

Coefficient data from the sample sorting circuit 26 is supplied to the register 31 via the register 30, and
2, from the output data of register 31 to register 3
Output data of 0 is subtracted. Therefore, the subtraction circuit 32 generates a difference value between the current value and the previous value. Similarly, the difference value of the addresses from the sorting circuit 28 is formed by the registers 33, 34 and the subtraction circuit 35. The difference values from the subtraction circuits 32 and 35 are sent to the variable length encoding circuit 2.
4.

The variable length encoding circuit 24 performs variable length encoding and information addition. The difference values from the subtraction circuits 32 and 35 are encoded by the variable length encoding circuit 24, thereby compressing the amount of information. The compressed AC component coefficient data, DC component data, and additional code are converted into a format as shown in FIG. 3 and supplied to the buffer memory 36.

FIG. 3 shows transmission data corresponding to one DCT block. A DC component 51 is placed at the beginning, followed by a flag 52 (3 bits x 5) indicating the order of divided blocks after sorting from the block sorting circuit 14, and then an initial value 53 of the address and a coefficient. Data initial values 54 are located, and following these initial values, variable length encoded address and coefficient data 55 are located,
A code EOB56 indicating a data delimiter is added at the end.

A write address formed by an address counter 38 or a read address formed by a read address counter 39 is supplied to the buffer memory 36 via a selector 37 . The write address and read address are supplied to the buffer controller 40, and an information amount control signal is generated by the buffer controller 40 so that the two values do not become too close. This information amount control signal is supplied to the ROMB, and weighting coefficients for the weighting circuit 7 are generated from the ROMB. buffer memory 3
The read data is transmitted from the terminal 6 to the output terminal 41.

b. Sorting Circuit Block An example of a sorting circuit that can be applied to the sorting circuit 14 or the sample sorting circuit 26 will be described below. For ease of understanding, the basic flow of sorting will be explained with reference to FIG. In Figure 4, if the input data is manually inputted with five numerical values having a magnitude relationship of (A>B>C>D>E), for example, in the order of (D, B, C, E, A). The input case is shown. Also, DI, D2. D3. D
4, D5 indicates five registers connected in cascade.

*Step O The contents of all registers are cleared to 0 before input data is supplied.

In this step 1, the contents of the first stage register D1 and the input data D are compared. The register is cleared in step 0, and D is input to register D1 because (D≧0).

This step 2 Contents of register D1 (D) and contents of register D2 (0)
and input data B are compared.

(B2O,, B2O), the contents of register D1 are shifted to register D2, and input data B is input to register D1.

This step 3 Contents of register D1 (B), contents of register D2 (D)
, the contents (0) of register D3 and input data C are compared, respectively.

(CAB), the contents of register D1 are not updated.

Since (B>C≧D) (second determination), input data C is input to register D2.

Since (C≧D, C20) (first determination), the contents of register D2 are shifted to the next stage.

This step 4 Contents of register D1 (B), contents of register D2 (C)
, the contents of register D3 (D), the contents of register D4 (0
) and input data E are compared.

Since (E<B), the contents of register D1 are not updated.

(Etc) (third determination), the contents of register D2 are not updated.

(END), the contents of register D3 are not updated.

(DIR≧0), so input data E is in register D
4 is input.

This step 5 Contents of register D1 (B), contents of register D2 (C)
, the contents of register D3 (D), the contents of register D4 (E
), the contents (0) of register D5 and input data A are compared, respectively.

Since (A≧B), A is input to the register D1.

Since (A≧B, , A≧C), the content B of register D1 is shifted to register D2.

(A≧CSA≧D), so the contents of register D2 C
is shifted into register D3.

Since (A≧DSA≧E), the contents of register D3 are shifted to register D4.

(A2B, A≧0), so the content of register D4 is E
is shifted into register D5.

Through the above processing, five numerical values are stored in the register DI-D5 in order of size.

FIG. 5 shows an example of a sorting circuit for performing the above sorting, and FIG. 6 is a timing chart thereof. 8-bit parallel input data Bi (AC component of coefficient data) is supplied to register D1 via register D6. The register D6 contains the timing pulse LD.
O is supplied, and the human power data Bi is the timing pulse LD.
Same as O, 3t, 11.

Register D2 . D3. D4, D5
are connected in cascade. These registers D1 to D5 are cleared at time to by a clear pulse MR generated by the delay circuit DL and the inverter I from the pulse BLKP. The contents of registers D1 to D5 are all set to O by the clear pulse MR.

A multiplexer M2 is inserted between the output side of register D1 and the input side of D2. Similarly, registers D2 and D
3, between registers D3 and D4, between registers D4 and D5
Multiplexers M3, M4, and M5 are inserted between them, respectively. These multiplexers selectively output either the output signal of the register at the previous stage or the input data Bi.

Multiplexer M2 is controlled by the output signal of comparison circuit C1, and similarly multiplexers M3, M4, M5 are controlled by the output signals of comparison circuits C2, C3, C4. Input data BL is supplied as a human input signal P to one of these comparison circuits C1 to C4 and C5, and contents of registers D1 to D5 are supplied as an input signal Q to the other comparator circuit. Comparison circuit 01
~The output signal of C5 is “0′” (low level) when (p≧Q) (P<Q
) becomes “1” (high level).

Also, a register F is set at the same time by pulse MR and is supplied with timing pulse LDO as an enable signal.
1 to F5 are provided. Pulse signals LDENI-LDEN5 are generated from registers F1-F5, respectively. Furthermore, the timing pulse LDO is connected to the D flip-flop D1.
7, the timing pulse LD is delayed by one clock period.
I is formed.

The pulse signal LDEN1 and the output signal of the comparator circuit C1 are ORed.
It is supplied to gate 011. The output signal of OR gate 011 and timing pulse LDI are supplied to OR gate 012, and the output signal of OR gate 012 is supplied to register D1 as an enable signal. When the enable signal is at a low level, the register D1 is enabled. The enable signal of register D2 is OR game)021
Similarly, the respective enable signals of registers D3, D4 and D5 are connected to OR gate 031.03.
2,041.042,051,052.

In this example, 3-bit parallel input data At is supplied together with input data Bt. In the block sorting circuit 14, this input data At indicates the divided block number. In other words, (Al, Bl) (A2.B2
) ... Two pieces of data are input in pairs, such as (A5.B5).

Regarding input data Ai, registers DIl to D15 and multiplexers M12 to M15 are also provided. Registers D11-015 and multiplexers M12-M15 are the registers D1-D5 and multiplexers M2-M
5, and therefore, sorting is performed while maintaining the pairwise relationship. The output signals of registers Dll to D15 are supplied to the parallel input terminals of shift register SR, and data (3 bits x 5) indicating the order of the rearranged divided blocks is read from shift register SR.

In the case of the sample sorting circuit 26, it is necessary to output sorted coefficient data, and the contents of registers D1 to D5 are taken out via shift registers.

The two registers constituting the above-mentioned sorting circuit and their peripheral circuits are extracted and shown in FIG.

The input value will be represented by X, and what value will be loaded into the register Dk will be explained.

Output signal CMPk-1 of first judgment comparison circuit Ck-1 and comparison circuit C
When the output signals CMPk of k are both “0”, (X≧D
k-1>Dk) (7) There is a size relationship. (X≧Dk-1
), it is necessary to shift the values of all upper registers at least in the registers after Dk, so multiplexer Mk selectively outputs the contents of register Dk-1 and transfers the contents of multiplexer Mk to register Dk. The output is loaded.

The output signal CMPk-1 of the second judgment comparison circuit Ck-1 is "1",
When the output signal CMPk of the comparison circuit Ck is "0",
There is a magnitude relationship of (Dk-1>X≧Dk). In this case, multiplexer Mk selectively outputs input data X, and X is loaded into register Dk. Further, after Dk, the value of the register is shifted in the first determination.

Output signal CMPk-1 of third judgment comparison circuit Ck-1 and comparison circuit C
When the output signals CMPk of k are both "1', (Dk>
X), there is no need to change the contents of the register Dk, and it is set in a hold state.

In this case the output of multiplexer Mk is irrelevant.

Note that the output signal CMPk-1 of the comparison circuit Ck-1 is "0".
Then, the state in which the output signal CMPk of the comparison circuit Ck is 1'' is as follows.
It can't happen.

The above-described sorting circuit can perform sorting in real time, and can simultaneously sort addresses by sorting coefficient data.

C6 Other Embodiment FIG. 9 shows another embodiment of the present invention. As shown in FIG. 10A, the DCT block, excluding the DC component,
It is divided into six divided blocks from the 0th block to the 5th block. As shown in FIG. 10B, the fourth block may not be provided and five divided blocks may be formed.
In Figure 0, the numbers surrounded by squares indicate the numbers of divided blocks, and the numbers appended to the data indicated by .. indicate the order of scanning within each block.

In the embodiment described above, all eight divided blocks were sorted, but in another embodiment, only the divided blocks (0 to 4) in FIG. 10A are sorted by the block sorting circuit 14. The order of the five divided blocks is (5!=120 ways), and this order is
It is expressed in 7 bits. A ROM 18 to which the output of the sorting circuit 16 is supplied generates 7-bit data indicating the order of divided blocks. Data indicating the order of generation from the ROM 1B is added to the transmission data by the variable length encoding circuit 24.

Moreover, weighting is performed so that the output signal of the circuit 7 is the maximum value detection circuit 17
supplied to The maximum value detection circuit 17 detects the maximum value among the coefficient data of five divided blocks having block numbers (0 to 4), and also detects the maximum value detected among the data of the fifth block. A larger number of data is detected. The detected maximum value is supplied to a sorting circuit 27 that performs amplitude sorting in a sample sorting circuit 26, and data indicating the number of pieces of data larger than the maximum value is added to the transmission data by a variable length encoding circuit 24.

After making the above preparations, first read the data of the fifth block from the array conversion memory 20, sort the data with the detected maximum value or more together with the address, and encode it in the variable length encoding circuit 24. The data of the 0th to 4th blocks are supplied to the sample sorting circuit 26 in the block sorted order. Then, the difference values between the address and the data are detected, and the difference values are encoded by the variable length encoding circuit 24.

The variable length encoding circuit 24 outputs data in the transmission format shown in FIG. Figure 11 shows one D
A DC component 61 is located at the beginning indicating the transmission data corresponding to the CT block, and then a 1-bit flag 62 is added indicating whether the fifth block has data larger than the maximum value. . If the flag 62 is "1", it means that there is a component larger than the maximum value, and if the flag 62 is "0", it means that there is no component larger than the maximum value. A 7-bit code 63 indicating the order of the divided blocks is located, followed by a code 64 indicating the number of data in the fifth block that is larger than the maximum value.
is located. 65 indicates variable length coded data of the fifth block which is larger than the maximum value, and 66 indicates variable length coded data of the Oth to fourth blocks. As in the previous embodiment, at the end, code 6 indicating the delimitation of the data is added.
7 is added.

d. Still another embodiment FIG. 12 shows still another embodiment of the present invention, and FIG.
As shown in FIG. 13, the figure shows block division (8
The DCT block of x8) is divided into (2×2) blocks. In FIG. 13, the numbers surrounded by squares indicate the numbers of divided blocks, and each divided block is scanned in the order indicated by the numbers. Block sorting is performed in units of this divided block. However, since the Oth block contains only 3 pieces of data because it includes a DC component, the cumulative value of the Oth block is multiplied by (4/3) during block sorting, and the cumulative value of other blocks is multiplied by (4/3). compared to

The result of block sorting by the block sorting circuit 14 is supplied to the ROM 23 and address generation circuit 29. The address generation circuit 29 generates addresses of divided blocks indicating the sorted order. R
Data is read from the array conversion memory 20 according to the read address generated from the OM 23. The output data of the array conversion memory 20 is converted into absolute values and then supplied to the variable length encoding circuit 45 and the comparison circuit 46.

The comparison circuit 46 is supplied with a threshold level from the buffer controller 40 . The comparator circuit 46 generates a transmission data determination flag that becomes "1" when the absolute value of the coefficient data is greater than the threshold level, and becomes "0" when the opposite occurs. A flag of "1" means that transmission is necessary, and a flag of "0" means that transmission is unnecessary. The flag from comparison circuit 46 is held in register 4T. Among the output signals of the variable length encoding circuit 45, only data whose flag is "1" is transmitted.

The information addition circuit 44 receives the address of the divided block from the address generation circuit 29, the output signal of the variable length encoding circuit 45, the flag from the register 47, and the delay circuit 4.
The DC component from 3 is supplied. The direct current component is DCT
The signal is separated by a separation circuit 42 connected to the conversion circuit 2, and taken out from a delay circuit 43 for time adjustment. The information addition circuit 44 forms the transmission data shown in FIG.

FIG. 14 shows transmission data corresponding to one DCT block. DC component 71 is located at the beginning, then 1
Block numbers 72a and 72 of each of the six divided blocks
b... and transmission data determination flags 73a, 73b...
and variable-length encoded data 74a, 74b, . . . are located therein, and as in the previous embodiment, a code 75 indicating a data delimiter is added at the end. In Figure 14, the first
A specific example of data when the data at addresses 0 and 3 of the block is greater than the threshold value is shown. In this still other embodiment, the transmission data determination flag can distinguish between data to be transmitted and data not to be transmitted using one bit, and since no difference value is formed, the configuration on the decoding side is simple.

〔Effect of the invention〕

In this invention, coefficient data generated by transform encoding is divided into a plurality of blocks smaller than the original block, sorted in units of divided blocks, and then sorted in units of samples.

Therefore, compared to the conventional method which uses only a zigzag scanning order, the difference value of addresses can be made small, and data can be compressed efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of this invention, FIG. 2 is a route map showing block division of an embodiment of this invention, and FIG. 3 is a route map showing a transmission format of an embodiment of this invention. Figure 4 is a route map used to explain sorting, Figures 5 and 6 are a block diagram and timing chart of an example of a sorting circuit that can be used in this invention, and Figures 7 and 8 are used to explain the sorting circuit. Block diagram and route map, FIG. 9 is a block diagram of another embodiment of this invention, FIG. 10 is a route diagram showing block division of another embodiment of this invention, and FIG. 11 is another embodiment of this invention. A route map showing an example transmission format, FIG. 12 is a block diagram of still another embodiment of the present invention, FIG. 13 is a route map showing block division of still another embodiment of this invention, and FIG. 14 is a route map of this embodiment. FIGS. 15 and 16 are a block diagram and a route diagram used to explain a conventional data processing circuit. 2: 3° DCT conversion circuit, 20: Array conversion memory, block sorting circuit, variable length encoding circuit, sample sorting circuit, buffer memory, information addition circuit.

Claims (1)

[Claims] In a data processing circuit that processes a plurality of coefficient data obtained by orthogonally transforming a first block consisting of a plurality of pixels, the plurality of coefficient data is smaller than the first block. means for dividing the plurality of second blocks into a plurality of second blocks; level detection means for detecting a level signal for each of the second blocks; and block sorting means for rearranging the plurality of second blocks in the order of the magnitude of the level signal. and a selection means for selecting a predetermined number of coefficient data of the second block from among the coefficient data belonging to the second block rearranged by the block sorting means, and encoding for encoding the output data of the selection means. A data processing circuit comprising a circuit.