JPH02171023A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction and to obtain a high speed level conversion circuit by using a signal level transit detection circuit so as to detect a change in an input signal, thereby varying the current capability ratio of a PMOS transistor(TR) and an NMOS TR. CONSTITUTION:When a level of an input signal IN changes from L to an H level in a TTL level, an input signal transition detection circuit C detects the change. Then an output signal VA11 from the circuit C goes to H level at a time T2 with a prescribed time delay, and an NMOS TR Q3 is turned on. The relation between the current capability ratio RbetaI of a PMOSTR Q11 and an NMOS TR Q12 being components of an input inverter and a current capability ratio Rbeta3 of MOS TRs Q11, Q12, Q13 is expressed in equation 1, where betaQ11, betaQ12, betaQ13 are current capabilities of the TRs, respectively. That is, since the capability ratio RbetaII when the NMOS TR Q13 is set smaller than the capability ratio Rbeta1, even if the source level of the NMOS TR is fluctuated due to the change in the operating current of a CMOS LSI, the level of the output voltage VOUT keeps the L level of the CMOS level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level conversion circuit, and particularly to a level conversion circuit that converts between TTL level and C
This invention relates to a level conversion circuit between MOS levels.

[Conventional technology]

Conventionally, this type of level conversion circuit has used an inverter circuit that receives a TTL level input signal as a gate input and is configured and operated between the highest and lowest CMOS level potentials.

The prior art will be described below with reference to the drawings. Fourth
In the figure, the highest potential of CMOS level v1. P between D (usually 5.0V) and the lowest potential VGND (usually OV)
Channel type insulated gate field effect transistor (PM
Q41 (abbreviated as O8T) and N-channel type insulated gate field effect transistor (abbreviated as NMO3T below)
An inverter circuit consisting of Q4□ is configured, and PMO8T
The input terminal IN is commonly connected to the gates of Q41 and NMO8T Q, □, and the output terminal OUT is connected to the connection node of these MO8T. In such a configuration, the input terminal IN has a TTL level (usually 0.8 to 2
．． When an input signal of 2V) is input, a CMOS level output signal is output to the output terminal OUT.

Normally the threshold voltage of PMO8T is -0.4 to -1.0v
The threshold voltage of NMO8T is set to about 0.4~
1. It is set to about Ov.

When a high TTL level “High” level is input to the input terminal IN, the voltage applied to the input terminal IN is 2,
Since the voltage between the gate and source of PMO8TQ41 does not fall below its threshold voltage, it does not become completely non-conductive. Furthermore, N M OS
Although the gate-source voltage of T Q s 2 exceeds the threshold voltage, it is 'High' at the CMOS level.
Since it is lower than the current level, it does not reach the saturation region of its current characteristics.

At this time, the CMOS level low 'L o' is applied to the output terminal OUT.
In order to output the w' level, conventional level conversion circuits TEkt, PMOSTQs I and NMO3 are used.
T Q4!17) Change the current capacity ratio to PMO8T Q4. The NMOS TQ41 is set to be larger than that. Based on the static characteristics of PMO8T and NMO8T, the current capacity ratio is determined to be β, :β, = about 1:4 to 10.

[Problem to be solved by the invention]

In recent years, MO3LSI chips have become smaller and their operation speeds have increased, and as the chips have become smaller, the wiring within the chip has become smaller, and the wiring for power supply and GND within the chip has also become smaller, leading to an increase in self-inductance. .

In addition, in input/output, LSIs with TTL level and CMOS level compatible functions use MOS transistors with large current capacity for output buffers, so the MOS
) Current gradient d i / due to transistor on/off
dt becomes larger as the access speed of MO3LSI becomes faster.

Due to the increase in self-inductance due to the miniaturization of wiring and the increase in di/dt due to faster access, for example, when the input level changes, the internal circuit operates, causing the power supply and ground potential inside the chip to decrease. tremors tend to increase.

In the above situation, the operating level of the conventional level converter circuit is determined by the static characteristics of the PMO3T and NMO8T that make up the circuit, so the power supply is limited.

This had the disadvantage of causing malfunctions due to fluctuations in ground potential.

The malfunction will be explained in detail below using FIGS. 4 and 5.

When an input voltage VIN of a TTL level Low' level is applied to the input terminal IN, an output voltage V of a CMOS level High' level is applied to the output terminal OUT. tlT is given.・Next, at time T1, the input voltage v
The process changes from “Low” level of TTL level to High’ level.
When the level changes, the source of NMOS TQ4□
The voltage between the gates is vl, and P M O S T Q
The current capacity ratio of 41 and NMOS T Q4□ is NMO3
Since TQ41 is set higher, the output voltage V. tlT becomes the "Low" level of the CMOS level. This output signal is transmitted to the internal circuit, and the internal circuit starts operating. Therefore, due to charging and discharging of the wiring capacitance, through current in the CMOS inverter circuit, etc., this level The operating current of CMO5LSI including the conversion circuit increases, and di
/ d At time T2 when t peaks, the ground potential fluctuates, so the source potential of NMO3T Q4□ rises, its gate-source voltage decreases to v2, and P M set by the static characteristics OS TQ 4
The current capacity ratio of NMO8TQ42 of 1 cannot be maintained. Therefore, the input voltage V□ appears to be “High”.
The level has changed to “Low” level, and the output voltage Vour is “Low” of CMOS level.
'It becomes impossible to maintain the condition, Figure 5 V. . As shown in 7', a phenomenon of transition to High' level occurs.

In addition, considering the fluctuation of ground potential, PMO8T and NMO3
When setting the current capacity ratio of T, compared to when it is set based on static characteristics, it is necessary to make the current capacity of NMO3T even larger than that of PMO8T, and therefore,
The size of NMO8T increases. Furthermore, PMO8T
Since the current capabilities of NMOS T and NMOS T are significantly different, the rising waveform of the output signal is slower than the falling waveform, and the response time due to input changes is significantly different between rising and falling, which is a disadvantage that it is not suitable for high-speed operation. There is.

〔the purpose〕

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a level converter circuit that does not malfunction even with changes in ground potential and has high-speed circuit operation.

[Means to solve the problem]

The level conversion circuit of the present invention includes a first means for receiving first and second power supply potentials and inverting and outputting a signal supplied to an input terminal to an output terminal; a logic circuit whose input is a delay 1 inverter signal of a signal supplied to the output terminal; and a second logic circuit which supplies the second power supply potential to the output terminal according to the output signal of the logic circuit. means.

Its detailed configuration includes a PMO8T whose gate is connected to an input terminal, whose source is connected to a first power supply terminal, and whose drain is connected to an output terminal; and a PMO8T whose gate is connected to the input terminal and whose source is connected to a second power supply terminal. C consisting of a first NMO3T connected to the output terminal and having its drain connected to the output terminal.
a MOS inverter; a signal level transition detection circuit having a NOR gate having one input connected to the output terminal and the other input connected to the output terminal via a delay circuit and an inverter; A second NMO3T is connected to the output terminal of the transition detection circuit, has a source connected to the second power supply terminal, and has a drain connected to the output terminal of the CMOS inverter.

With this configuration, the signal level transition detection circuit generates a pulse signal in response to a change in the signal input to the input terminal of the CMOS inverter, activates the second ONMO8T, and connects the second power supply terminal to the output terminal of the CMOS inverter. It supplies the potential of

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. In FIG. 1, the highest potential vDD and the lowest potential v of the CMOS level.

E P M O S T Q r between NDs, and NMO
An inverter circuit consisting of 3TQ+z is constructed, and P M
The input terminal IN is commonly connected to the gates of OS T Q + + and NMO8T Q, □, and these MO
An output terminal OUT is connected to the connection node of ST. Further, this output terminal OUT is connected to one input of the NOR gate 1, and is also connected to the other input of the NOR gate 1 via the delay circuit 2 and the inverter 3. These N
OR gate 1. The delay circuit 2 and the inverter 3 constitute an input signal transition detection circuit C, and the output of the input signal transition detection circuit C, that is, the output A++ of the NOR gate 1 is as follows.
Output terminal OUT and lowest potential V. NM connected between ND
It is input to the gate of OS TQ 13. PM here
OS T Q ++ and NMOS T Q 12 output the output terminal O when a TTL level is input to the input terminal.
Its size is set by static characteristics so that the UT can provide CMOS level output.

Now, when the TTL level "Low" level is being input to the input terminal IN, the output terminal OUT is a CMOS
Since the “High” level is applied, the output A1 of the input signal transition detection circuit C is “Low”.
level, N M O S T Q l 3 is O
It is in the FF state, and the output terminal OUT is “High”.
Levels are P M O S T Q 11 and NMO 8
It is determined by the static characteristics of T Q,2. Also, input terminal I
When the 'High' level of the TTL level is input to the output terminal OUT, the 'High' level of the CMOS level is input to the output terminal OUT.
Since the Low' level is given, the output A1 of the input signal transition detection circuit C becomes the Low level, and NM
O8T Q, 3 becomes OFF state, output terminal OUT
“Low” level of PMOS TQ++ and NM
Determined by static characteristics of OS TQ12.

Next, the operation when the input of the level conversion circuit shown in FIG. 1 changes from TTL Low' level to 'High' level will be explained using FIG. 2. Now time T
1, when the input signal IN changes from TTL Low' level to High' level, the change is detected by the input transition detection circuit C, and at time T2 delayed by a predetermined time, the input signal IN changes from the TTL level Low' level to High' level. The output signal VA11 becomes High' level, and the NMO
STQl is turned on. PM of input inverter
M OS T Q lr, Q for the current capacity ratio Ra+ of O8TQu and N M OS T Q l 2
Current capacity ratio RI of 1□, Ql.

The relationship between β and the current capacity of each is β. 11. βQ1□
.

If βQI3, then R2,=β. 1, /(βQ12+β.+3) <Ra+
=βQ1, /βQ1□. That is, NMO3T
The current capacity ratio Rβ1 when Q, , is ON is Rβ1
Since it is set smaller than V, even if the source potential (ground potential) of NMO3T fluctuates due to changes in the operating current of 0MO8LSI, the output voltage V. LIT level is CMOS
level can be maintained at “Low” level.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

P M O S T Q 21 and N M O S T
An input terminal IN is commonly connected to the gates of the CMOS inverter circuits consisting of Q2m, and an output terminal OUT is connected to these connection nodes. P M O S T Q 2 of this CMOS inverter circuit! is a PMO whose gate receives an internal control signal φ1 such as a chip selection signal.
It is connected to the power supply potential VD via S T QH. Also, the output terminal OUT and the ground potential V. NMO3 between ND
TQ2. and Q25 are connected in parallel, NMOS
The internal control signal φ1 is input to the gate of T Q 24, and the output All of the input signal transition detection circuit C is connected to the gate of NMOS T Q 25. In this example, PMO8T Q2+, Q2□ and NMOSTQ23
1 A NOR circuit is formed by Q24, and this NOR
Since the circuit is controlled by the internal control signal φ1, there is an advantage that no steady current flows when the level conversion circuit is not selected.

〔Effect of the invention〕

As explained above, the present invention detects a change in an input signal using a signal level transition detection circuit, thereby temporarily converting a level conversion circuit only during the period when the power supply and ground potential of the 0MO8LSI changes immediately after the change in the input signal. Constituent PMO
By changing the current capability ratio of 8T and NMO8T, it is possible to prevent malfunctions and realize a level conversion circuit in which the output response time due to input changes does not differ greatly between rise and fall.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
The operating waveform diagram of the level conversion circuit shown in the figure, Figure 3 is
FIG. 4 is a circuit diagram of the conventional example, and FIG. 5 is an operating waveform diagram of the conventional example. IN...Input terminal, OUT...Output terminal, C...Input signal transition detection circuit, Q r r
* Q 21 # Q i 2 # Q 41...
...PMO8T, Ql□eQzsaQzspQzs*
Q*z...NMO8T, φ1...Internal control signal, 1...NOR gate, 2...
・Delay circuit, 3...Inverter. Agent Patent Attorney Uchihara Otoshin IWJ Sou 2 DD VDD Temen Mein

Claims (1)

[Claims] a first means that receives first and second power supply potentials and inverts and outputs a signal supplied to the input terminal to an output terminal; and a signal supplied to the output terminal is used as one input, and is supplied to the output terminal. a logic circuit whose other input is a delayed or inverted signal of a signal to be output, and a second means for supplying the second power supply potential to the output terminal according to an output signal of the logic circuit; 2. A level conversion circuit, characterized in that said second means is activated for a predetermined time by a change in a signal supplied to an input terminal of said means from a first potential to a second potential.