JPH02100358A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory having a degree of integration which matches that of the next generation by forming walls of insulator layers, thereby forming element regions on the side faces and upper faces of these walls. CONSTITUTION:Word lines 11 are formed as gate electrodes around walls of 4 of insulator layers through gate insulating films 10. These word lines are insulated from the word lines 11 as electrode around the walls of adjacent insulator layers by insulating layers 14. Bit lines 15 are formed on the upper parts of these layers and N-type diffusion layers 7' are formed on the upper face of the insulating layer walls 4 in regions where these bit lines 15 and the word lines 11 as the gate electrodes formed on both sides of the insulator layer walls 4 intersect each other. Then, P-type diffusion layers 13 and N-type diffusion layers 7 are formed. A degree of integration which matches that of the next generation is thus obtained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device and a method for manufacturing the same, and particularly relates to a DRAM (Dynamic Random
The present invention relates to a semiconductor memory device with an improved cell structure (Access Memory) and a method for manufacturing the same.

(Prior art) With reference to FIGS. 5 and 6, DR according to the prior art
AM cells will be explained.

FIGS. 5(a) and 5(b) are a plan view and a cross-sectional view of a DRAM cell according to the prior art, particularly a cell called a cross-point cell.

In the plan view of FIG. 5(a), a cell for one bit is formed at the intersection of the word line 101 and bit line 102 of the DRAM cell. The memory element of this DRAM cell uses a capacitor having a so-called trench structure.
A trench groove 103 is formed in the semiconductor substrate 100 .

FIG. 5(b) is a cross-sectional view taken along the cross-section B-8 in FIG. 5(a), and as shown in this cross-sectional view, the semiconductor substrate 10
A P-type diffusion layer 104 is formed in the P-type diffusion layer 1.
04 is a P medium-sized diffusion layer 105 with high impurity concentration.
is formed, and a trench groove 1 is formed through these two diffusion layers.
03 is formed as an opening, and a capacitor electrode 107 and a word line 101 are formed in this trench groove 103. Further, the semiconductor substrate 100 is insulated from the semiconductor substrate 100 by a gate oxide film 106 and a capacitor insulating film 109, except for the buried contact portion 108.

The operation of this DRAM cell is such that when the potential applied to the bit line 102 increases the potential of the word line 101, the P-type diffusion layer 104 near the gate oxide film 106 is inverted, and the buried contact 108 is inverted. communicated. On the other hand, since this buried contact 108 is connected to the capacitor electrode 107, this buried contact 108 is connected to the capacitor electrode 107.
7 and P facing each other with the capacitor insulating film 109 in between.
M I S formed between the medium-sized diffusion layer 105
(Metal I n5ulator S e
mlcondoctor) type capacitor to store and store charge.

According to the conventional semiconductor memory device having such a configuration, not only the capacitor but also the transfer gate region is buried inside the trench groove 103, so that the degree of integration of the semiconductor memory device can be considerably improved in the planar direction. However, there is a limit to this improvement in the degree of integration, that is, the miniaturization of devices. The limits of this miniaturization will be explained with reference to FIG.

As shown in FIG. 6, if we are to manufacture the smallest semiconductor memory device that can be manufactured, let F be the minimum dimension determined by the photo-etching process, etc., and let the alignment margin between different photo-etch processes be 0.2F. , the trench groove-side length is F, which is the minimum dimension described above, and the line widths of the word line and bit line are each 1.4F.

The interval between each word line and each bit line is 1. Since it is OF, the length of one side of the cell area is 0.5 F +0.2
F+1. OF +0.2 F +0.5 F-2,
It will be 4F. Therefore, the minimum area of a cell for one bit is 2.
4F X2.4F -5,76F 2 .

If we were to try to reduce the cell area for one bit even further, we would have to significantly improve and advance photoetching technology, and the resolution would increase.
There is no other way than to improve the alignment accuracy.

(Problems to be Solved by the Invention) This invention has been made in view of the above points, and it is possible to develop a semiconductor memory with an integration level comparable to that of the next four generations without relying on significant improvements in photolithographic technology. The purpose of the present invention is to provide a device and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems and Their Effects) In the semiconductor memory device according to the present invention, a wall of an insulating layer is formed, and a semiconductor layer is formed on the top and side surfaces of the wall of the insulating layer. established,
This semiconductor layer is divided in a planar direction to form semiconductor layers of a first conductivity type and a second conductivity type. According to a cell structure with such a configuration, the element region for the cell is formed on the top and side surfaces of the wall of the insulating layer, and the width of this wall and the width of the groove between the walls can be adjusted using current photolithography technology. If the minimum dimension is F, then a 2-bit cell can be manufactured in the area of the minimum surface V45.76F2 of a 1-bit cell, and without relying on significant improvements in photolithographic technology, It becomes possible to create a semiconductor memory device and its manufacturing method that has twice the degree of integration of a semiconductor memory device having a conventional cell structure manufactured using the best photolithography technology, that is, the degree of integration comparable to that of the next generation.

(Embodiment) Hereinafter, a semiconductor memory device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.

FIGS. 1(a) to 1(f) are cross-sectional views showing the steps of a method for manufacturing a DRAM cell according to an embodiment of the present invention.

In FIG. 1(a), a first single crystal silicon layer 2 is grown on an insulator layer 1 using, for example, a vapor phase growth method.

Next, a photoresist 3 is deposited on the entire surface and patterned into a predetermined shape. Using the photoresist 3 in the predetermined shape as a mask, the insulator layer 1 and the single crystal silicon layer 2 are etched, and the walls 4 of the insulator layer are etched. Form. At this time, the distance between the walls 4 is approximately equal to the thickness of the walls 4.

In FIG. 1(b), after removing the photoresist 3,
A second silicon layer 2 is formed on the entire surface using, for example, a vapor phase growth method.
′ to grow. At this time, single crystal silicon 2' is grown using the first single crystal silicon 2 as a seed crystal. Next, for example, B (boron), which is a P-type impurity, is ion-implanted into the silicon layer 2'' and thermally diffused to form a second single-crystal silicon layer 2''.
'' is doped to P type. Next, RI E (React
This P-type single-crystal silicon oxide layer is etched so that it remains only on the top and side surfaces of the walls 4 of the insulator layer using a ive I on E tchlng method.

In FIG. 1C, a silicon oxide layer 5 is formed between the silicon layers 2' formed in the grooves between the walls 4 and 4 of each insulating layer by, for example, chemical vapor deposition (CVD).
or D cposltlon) method, and etched to, for example, a capacitor formation region up to half the depth of the trench. Subsequently, this silicon oxide layer 5 is coated with, for example, N.
When As (arsenic), which is a type impurity, is ion-implanted, the entire surface is covered with a protective film 6 made of, for example, an oxide film, and then heat treatment is performed to activate the impurity ions, a single crystal is formed from the silicon oxide layer 5. N-type impurities are thermally diffused into the silicon layer 2', and the single-crystal silicon layer 2' is doped with N-type only in the vicinity where it contacts the silicon oxide film 5, thereby forming a first N-type diffusion layer 7.

In FIG. 1(d), the silicon oxide film 5 and the protective film 6 are removed, and the P-type single crystal silicon layer 2-1 and the first
The N-type diffusion layer 7 is exposed, and then a first thermal oxide film 8 is formed on the entire surface. This first thermal oxide film 8 becomes a capacitor insulating film in a later step. Next, a first polysilicon layer 9 is applied in the groove between the walls 4 of each insulating layer, e.g.
The capacitor electrode 9 is formed by depositing using the D method and etching down to the capacitor formation region.

Next, in FIG. 1(e), from the capacitor electrode 9,
The first thermal oxide film 8 in the - portion is removed. The first thermal oxide film 8 remaining in this step becomes the capacitor insulating film 8.

Next, a second thermal oxide 11110 is formed on the entire surface by thermal oxidation. At this time, since the oxidation rate of polysilicon is fast, a thermal oxide film 10 that is thicker than the others is formed above the capacitor electrode 9 made of polysilicon. This second thermal oxide film 10 will become a gate insulating film in a later process. Next, a second polysilicon layer 11 is placed in the trench between the walls 4 of each insulator layer.
is deposited by, for example, the CVD method, and etched to the transistor formation region delimited by the thermal oxide film 10.

This second polysilicon layer 11 will become a gate electrode in a later step. Next, for example, an N-type impurity As (arsenic) is added to the upper part of the wall 4 of the insulating layer P! 42 Ions are implanted into the silicon semiconductor layer 2' through the second thermal oxide film 10 and thermally diffused to form a second N-type diffusion layer 7' having a conductivity type opposite to that of the P-type silicon semiconductor layer 2'. do. At this time, the second polysilicon layer 11
The P-type silicon semiconductor layer 2', which is protected by and is not doped to N-type, remains as a P-type diffusion layer 13. An element region is formed by the N-type diffusion layer 7.7'' and the P-type diffusion layer 13 on the side surface of the groove thus formed in the insulating layer 1, that is, on the side surface of the wall 4 of the insulating layer. .Next, RIE
The second polysilicon layer 11 is etched into a predetermined shape using a method to form a gate electrode 11.

Finally, in FIG. 1(f), a silicon oxide film 14 is deposited using the CVD method. Next, the silicon oxide film 14 and the second thermal oxide film 10 are removed so that the second N-type diffusion layer 7' is exposed. Thereafter, AI (aluminum) is deposited on the entire surface by, for example, sputtering, and patterned into a predetermined shape to form bit lines 15, thereby manufacturing a semiconductor memory device according to an embodiment of the present invention.

According to a semiconductor memory device having such a cell structure, a single crystal silicon layer 2'' is provided on the side surface of the groove formed in the insulator layer 1, that is, on the side surface of the wall 4 of the insulator layer, and the single crystal silicon layer 2'' By dividing the layer 2- in the horizontal direction to form the NIJ1 diffusion layer 7.7'' and the P heavy diffusion layer 13, the element region of the cell is placed on the side surface of the groove, that is, on the side surface of the wall 4 of the insulating layer. Therefore, the minimum area of a conventional 1-bit cell is
It is possible to form cells for 2 bits, and without relying on significant improvements in photo-etching technology, the degree of integration is always twice that of the best technology of the time, that is, the next generation. It becomes possible to manufacture a semiconductor memory device with an unprecedented degree of integration.

Next, the semiconductor memory device manufactured according to the above embodiment will be explained with reference to FIGS. 2(a) and 2(b).

FIG. 2(a) is a plan view of a semiconductor memory device manufactured by the method of manufacturing a semiconductor memory device according to the above embodiment.

In FIG. 2(a), a word line 1 as a gate electrode is formed around the wall 4 of the insulating layer through a gate insulating film 10.
1 is formed and is insulated from the word line 11 serving as a gate electrode around the wall 4 of the adjacent insulating layer by an insulating layer 14 . A bit line 15 is formed above these, and in a region where this bit line 15 intersects with a word line 11 serving as a gate electrode formed on both sides of the insulating layer wall 4, the insulating layer wall 4 An N-type diffusion layer 7'' is formed on the surface, and a P-heavy diffusion layer 13 and an N-type diffusion layer 7 are formed, although not shown in the plan view.

In addition, Figure i2 (b) is the cross section A-A shown in Figure 2 (b).
This is a sectional view taken along the same line as FIG. 1(f).

Next, a first modification of the embodiment of the present invention will be described with reference to FIG.

In the above embodiment, the insulating layer 1 was etched to form the insulating layer wall 4, but as shown in FIG. The wall 4 may also be formed.

According to such a configuration, this silicon semiconductor substrate 16
The second silicon layer 2'' can be grown as a single crystal using as a seed crystal.

Next, a second modification of the embodiment of the present invention is shown in FIG. 4(a).
, and (b).

In this second modification, an insulator layer is formed on the silicon semiconductor substrate 16 similar to the first modification, and this is patterned to form the walls 4 of the insulator layer. As shown in FIG. 4(a), when etching the insulating layer, the insulating layer is left in the groove between the walls 4 of the insulating layer at the portion in contact with the silicon semiconductor substrate 16. The silicon semiconductor substrate 16 is etched to form a portion 17 where the silicon semiconductor substrate 16 is exposed.

After that, a silicon layer 2' is formed. With this configuration, the second silicon layer 2' can be grown as a single crystal using the exposed portion 17 of the silicon semiconductor substrate in the trench as a seed crystal.

Next, in FIG. 4(b), this silicon layer 2' is etched so as to remain on the top and side surfaces of the wall 4 of the insulating layer.

According to such a configuration, the silicon semiconductor substrate 16,
Since the insulator layer 4' is interposed between the silicon layer 2' and the silicon layer 2', leakage between adjacent cells is reduced.

In the above embodiments and modifications, the semiconductor layer forming the element region was grown using single crystal silicon, but it goes without saying that polycrystalline silicon may also be used.

[Effects of the Invention] As explained above, according to the present invention, by forming a wall of an insulating layer and forming an element region on the side and top surfaces of this wall, the minimum dimension of the photolithography technology of the time can be reduced to F. When, the minimum area of a cell for 1 bit is 5.76F
It became possible to form a cell for 2 bits in an area of 2.2 mm, and the integration density was always twice that of a semiconductor memory device with a conventional cell structure manufactured using the best photolithography technology of the time. A semiconductor memory device having a highly innovative cell structure and a method for manufacturing the same can be provided.

In addition, in the method of manufacturing a semiconductor memory device having such a cell structure, the word line serving as the capacitor electrode and the gate electrode is formed in a self-aligned manner. Cross section shown, 2nd
Figures (a) and 2(b) are a plan view and a cross-sectional view of the semiconductor memory device whose manufacturing process is shown in Figure 1, and Figure 3 is a
4(a) to 4(b) are cross-sectional views showing a first modification of the embodiment of the present invention, and FIG. 5 is a cross-sectional view showing a second modification of the embodiment of the present invention. (a) to (b) are a plan view and a cross-sectional view of a semiconductor memory device according to the prior art;
The figure is a plan view illustrating the minimum area of a cell for one bit according to the prior art.

1... Insulator layer, 2.2'... Single crystal silicon layer,
3... Photoresist, 4... Wall of insulator layer, 4'.
...Region for insulating the semiconductor layer and substrate, 5. Silicon oxide film, 6. Protective film, 7. N-type diffusion layer, 8.
... Thermal oxide film, 9... Capacitor electrode, 10... Thermal oxide film, 11... Gate electrode, 13... P-type diffusion layer, 14... Insulator layer, 15... Bit Line, 16...
- Silicon semiconductor substrate, 17... Portion where silicon semiconductor substrate 16 is exposed, 100... Silicon semiconductor substrate, 101... Bit line, 102... Word line, 10
3... Trench groove, 104... P-type diffusion layer, 105
... P ten type diffusion layer, 106 ... Gate insulating film, 10
7... Capacitor electrode, 108... Buried contact, 109... Capacitor insulating film.

Applicant's agent: Patent attorney Takehiko Suzue Figure 1 Figure 1 Figure 5 No. figure

Claims (2)

[Claims] (1) At least one groove formed on the substrate so as to have opposing wall surfaces of an insulator, and the upper and lower portions formed on the opposing wall surfaces sandwiching the groove are of the first conductivity type, and the central portion is of the first conductivity type. a capacitor insulating film formed in contact with the semiconductor layer of the second conductivity type and the lower semiconductor layer of the first conductivity type, and a capacitor insulating film formed in contact with the capacitor insulating film and embedded in the bottom of the groove A capacitor electrode, a gate insulating film formed in contact with the semiconductor layer of the second conductivity type in the center, a gate electrode formed in contact with the gate insulating film, and a semiconductor layer of the first conductivity type in the upper part. What is claimed is: 1. A semiconductor device comprising: a conductive layer formed using a conductive layer; (2) forming at least one groove on the substrate so as to have opposing wall surfaces of an insulator, and forming an upper and a lower portion of the first conductivity type on the opposing wall surfaces sandwiching the formed groove;
A step of forming a semiconductor layer having a second conductivity type in the center, a step of forming a capacitor insulating film in contact with the semiconductor layer of the first conductivity type in the lower part, and a step of forming a semiconductor layer in contact with the formed capacitor insulating film and in a groove. a step of forming a capacitor electrode so as to be buried in the bottom of the capacitor, a step of forming a gate insulating film in contact with the second conductivity type semiconductor layer in the center, and a step of forming a gate electrode in contact with the formed gate insulating film. The process of forming and the upper first
1. A method for manufacturing a semiconductor device, comprising the step of forming a conductive layer in contact with a conductive type semiconductor layer.