JPH01305461A - Bus right control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus right control system for an information processing device in which a plurality of processors exchange data via a common bus.

[Conventional technology]

Generally, in an information processing device in which multiple processors exchange data via a common bus, in order to solve the problem of bus usage conflicts, each processor is given a bus usage priority and then A widely used method is to handle bus usage requests from each processor. However, in the above method, as the number of processors connected to the common bus increases, the waiting time for processors set at a lower level to acquire the right to use the bus increases.
Until now, there have been methods such as Japanese Patent Application Publication No. 60-41157, which interrupts bus use of I1>Caninit and give priority to processor bus use, and methods such as Japanese Patent Publication No. 60-19819, which reserve bus use in the order in which bus usage requests occur. Various methods have been proposed to improve bus transfer waiting time.

On the other hand, if we focus on the data that processors transfer using the common bus, we find that there are data that requires urgency, such as real-time input/output data, and data that is less urgent, such as print data to peripheral devices. It can be categorized as unnecessary. Furthermore, the load on each processor changes from moment to moment due to various information processing requests, and even when transferring the same data, the urgency of the transferred data changes depending on the amount of processor load.

In order to improve the responsiveness of the entire system, it is necessary to give bus usage rights preferentially to data transfers that require urgency. Giving priority to the right to use the bus to the processors that do so will improve the overall responsiveness of the system.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not give priority to the right to use the bus with respect to the urgency of data transfer depending on the content of the transferred data and the urgency of data transfer due to the load status of each processor, and the system There was a problem that reduced responsiveness.

The present invention has been made in order to eliminate the drawbacks of such conventional methods, and therefore, an object of the present invention is to provide a method for transmitting data to be transferred in an information processing apparatus in which a large number of processors exchange data via a common bus. By granting the right to use the bus according to the level of urgency, data that requires urgency can be
An object of the present invention is to provide a bus use right control method that reduces bus transfer waiting time and improves system responsiveness.

[Means to solve the problem]

The above object is a means for each processor connected to a common bus to determine the priority of transfer data by a processing program based on the urgency depending on the transfer data and its own load state, and to transmit this as a bus use request signal. This is achieved by the bus control device having means for determining the right to use the bus in accordance with the bus use request signal and a priority determining circuit that operates when there is a conflict between the bus use request signals.

[Effect]

Each processor connected to a common bus requires hardware to physically implement its functions and software to logically control them. Furthermore, the above software is implanted with a processing program that processes the entire processor and a management program that manages them.Furthermore, this management program has a built-in task scheduler that manages the processing plan of the processing program. Common.

When a data transfer request occurs within the processor via the common bus, the type of data to be transferred is determined based on the attributes of the processing program issuing the transfer request and information on the storage location of the transferred data, and its urgency is determined. It is possible. Furthermore, the load state of the processor is determined by the task scheduler.
This can be determined by referring to the processing volume of . Therefore, each processor can determine data priority according to the urgency of the data and the load state of the processor, and outputs this as a bus use request signal to the bus control device.

On the other hand, the bus control device determines the highest data priority order determined by each processor based on the bus use request signal, and only the processor that has issued a bus use request with this highest order is eligible for bus use rights. Become. At this time, the pro set that has issued the bus use request in the highest order is 1
If there is only one processor, the right to use the bus is granted to the processor requesting the bus as is, but if there is a conflict between bus usage requests from two or more processors, the right to use the bus is granted in accordance with the priority set by the bus controller. Usage rights are determined.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.

FIG. 1 is a block diagram showing a configuration example of an information processing apparatus in which the present invention is implemented. In the figure 1. A plurality of processors 11 to 1n are connected to a common bus 2. A common bus use request signal (BREQI~n) is sent from each processor.
is connected to the bus control device 3. The bus control device 3 is composed of a data priority determination circuit and a processor priority determination circuit, and receives a bus use permission signal (ACKI~n).
is output to each processor.

A processor that transfers data via the common bus 2 outputs a bus use request signal to the bus control device 3 depending on the urgency of the transferred data. In the bus control device 3, first, a data order determination circuit is used for each processor.

Among the bus use request signals sent from the processor, only the signal of the highest order is outputted as the input signal (PRI~n) of the processor priority determination circuit 32. The processor priority determination circuit transmits the bus use permission signal (ACKI to n) to the processor in accordance with the priority set by the bus control device 3.

FIG. 2 shows the processor 1 in the embodiment shown in FIG.
1 to 1n show an example of data priority determination processing for programs included in the programs 1 to 1n. In FIG. 2, the processing program first checks whether the transfer data is particularly urgent based on the attributes of the transfer program and the storage location of the transfer data. If urgency is required, the transfer data is assigned a transfer data priority O, which is the highest priority order.Next, the processing program refers to the contents of the task scheduler and registers the transfer data. Check the processor load status based on the amount of processing being performed. If the amount of load on the processor is large, data priority 1 is assigned, and in other cases, data priority 2, which is the lowest priority, is assigned.

FIG. 3 is a time chart of the bus usage right determination process in the embodiment shown in FIG. 1;

The operation will be explained with reference to FIG.

In FIG. 3, processors 1 to 3 are each at level O
, Level 2. When bus use request signals of level O are output simultaneously, the data priority determination circuit outputs only the requests (PRI, PR3) of processor 1 and processor 3, which are requesting level O, which is the highest request level. . In this embodiment, if the priority set by the bus control device is set to processor 1 (high) to processor 3 (low), processor 1 is granted permission to use the bus. (ACKI). When processor 1 finishes using the bus, the right to use the bus is given to processor 3, which had the same priority, and when processor 3 finishes using the bus, the right to use the bus is given to processor 2, which is at a lower level.

〔Effect of the invention〕

As explained above, according to the present invention, the right to use the common bus is determined by the urgency of the data to be transferred by each processor and the priority set by the bus control device. Since this can be done efficiently, the response performance of the system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of data priority determination processing of a processing program included in a processor in the embodiment shown in FIG. 1, and FIG. 5 is a time chart of bus usage right determination processing in the embodiment shown in the figure. 11-1n... Processors 1-n, 2... Common bus, 3... Bus control device, 31... Data priority determination circuit, 32... Processor priority determination circuit.

Claims (1)

[Claims] 1. In an information processing device that consists of a common bus for the purpose of data transfer, a bus control device that controls the common bus, and multiple processors that send and receive data via the common bus, multiple means for the processor to determine the priority of data for each data group;
means for transmitting the determination result as a bus use request signal to the bus control device; and a priority determining circuit that operates when the bus use request signal and the bus use request signal conflict with each other in the bus control device. By providing a means for determining bus usage rights, when a processor transfers data via a common bus, it is possible for the processor itself to variably set the priority of data depending on the urgency of the data. A bus control method is characterized in that a bus control device determines a common bus right based on this.