JPH09180433A - First-in / first-out memory device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To suppress the extension of access time that occurs when switching the selection of word lines, and to enable high-speed operation efficiently with a relatively simple circuit configuration. SOLUTION: Word drivers 12A, 16A, 12
B, 16B, word line, column selectors 14A, 18A, 1
It has two dual port RAMs having two sets of addressing means composed of 4B, 18B and bit lines.
Two sets of these dual port RAMs are provided, and these dual port RAMs are used alternately every time the selection of the word line is switched after completion of sequential writing to all the bits connected to one word line, and prior to the selection switching. By driving the word line of the switching destination in advance, the extension of the access time at the time of selective switching of the word line is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to two sets of addressing means composed of a row decoder, a word line selectively driven by the row decoder, a column selector, and a bit line selected by the column selector. A dual port random access memory (hereinafter referred to as a RAM) is provided, and data sequentially written to the dual port RAM at consecutive addresses from one address designating means, the other address designating means. First-in first-out memory device (hereinafter referred to as FIF)
(Referred to as “O”), particularly, the access time of the dual port RAM which occurs when the selection of the word line is switched at the time of writing sequential data at continuous addresses or at the time of sequential reading in the writing order. The present invention relates to a FIFO that can suppress the bottleneck of the access time of the dual port RAM by suppressing the extension of the memory and can perform the access to the dual port RAM efficiently and at high speed with a relatively simple circuit configuration.

[0002]

2. Description of the Related Art The basic function of a FIFO is to sequentially store input data and output them in the order in which they are stored. Some FIFOs use a RAM. A FIFO using this RAM is generally
A RAM address is sequentially generated by a counter that operates in synchronization with a write clock used when sequentially storing data, and input data is sequentially written while using the address as a RAM write address. On the other hand, in reading the accumulated data in the FIFO, a counter that operates in synchronization with a read clock for controlling the read sequentially generates the addresses of the RAM, and while using this as the read address, the RAM is used.
The data accumulated from are sequentially read in the order of writing. Here, the RAM used for the FIFO is generally a dual port RAM.

This dual-port RAM has two sets of addressing means composed of a row decoder, a word line selectively driven by the row decoder, a column selector, and a bit line selected by the column selector. ing. In this dual-port RAM, two addressing means are thus provided.
By providing a set, it is possible to perform write access and read access independently to one built-in memory cell array and simultaneously as needed. That is, in this dual port RAM, the write clock used for write access and the read clock used for read access may have different frequencies and timings.

Further, in a FIFO using such a dual port RAM, data written sequentially at consecutive addresses using one of two sets of address designating means is transferred from the other address designating means. Read in the order written.

FIG. 6 is a block diagram showing the structure of a FIFO using a conventional dual port RAM.

In FIG. 6, the memory cell array 10 is shown.
, Write port word driver 12, write port column selector 14, read port word driver 16
And the read port column selector 18 constitute a dual port RAM. Also, this conventional FIF
In addition to the dual port RAM configured as above, O is a write address generation circuit 32A and an input circuit 34.
A, a read address generation circuit 42A, and an output circuit 44
A and a flag generation circuit 46A are provided.

The input data DI stored in the FIFO is written in the memory cell array 10 via the input circuit 34A and the write port column selector 14. or,
The data written and accumulated in the memory cell array 10 is read port column selector 18 and output circuit 44.
It can be read out as output data DO via A.

FIG. 7 is a diagram showing a matrix arrangement of the memory cells of the memory cell array 10 of FIG.

In FIG. 7, reference numerals WWD0 to WWD7 indicate a total of eight word lines of one addressing means used for writing data in the FIFO. On the other hand, the word lines of the other addressing means used for reading the data stored in the FIFO by the symbols RWD0 to RWD7 are shown.

Further, a total of 32 memory cells are indicated by "0" to "31" added to the matrix-like rectangular shape in FIG. As described above, in the FIFO dual-port RAM shown in FIG. 6, a total of four memory cells are connected to each word line and a total of eight memory cells are connected to each bit line.

FIG. 8 is a time chart showing the write operation of the conventional FIFO.

The write operation of this conventional FIFO is as follows.
It is controlled by the clock signal WCK. In accumulating the first data in the FIFO, the reset signal WRST input from the outside is dropped at time t11. Then, the value of the counter for generating the write address WAD incorporated in the write address generation circuit 32A becomes "0", and therefore the write address WAD also becomes "0".

After that, the reset signal WRST changes to the time t1.
After rising at 2, the input data DI to be accumulated is inputted and the selection signal WEN is made to fall. After that, when the clock signal WCK rises at time t13, the selection signal WEN in the L state is taken in, the selection signal WE becomes the H state, and at the same time, the input data DI is taken in. The input DI thus fetched is written to the memory cell of the memory cell array 10 corresponding to the write address WAD of "0". Here, the selection signal WE is (W
It is generated by a logical operation of E = (WEN bar) · WCK).

Next, immediately before time t14, the input data DI to be stored next is input. Then, time t1
When the clock signal WCK rises at 4, the value of the above-mentioned counter incorporated in the write address generation circuit 32A is incremented, and the value of the write address WAD is "1".
Becomes After that, the input data DI that has been input is written to the memory cell of the memory cell array 10 corresponding to the write address WAD which has become "1".

Similarly, in synchronization with the rising edge of the clock signal WCK, the counter incorporated in the write address generation circuit 32A is sequentially incremented, and the input data DI sequentially input to the corresponding memory cells of the memory cell array 10. Is written.

Here, in the period up to time t16, the input data DI is written in the memory cell connected to the write word line WWD0, and the write word line WWD0 is set to H over almost the entire period. It is in a state. In the period from time t17 to time t18,
Since the input data DI is written to the memory cell connected to the write word line WWD1, the write word line WWD1 is in the H state for almost the entire period. In the period after time t19, the input data DI is written in the memory cell connected to the write word line WWD2, and correspondingly, the write word line WWD2 is in the H state over almost the entire period. Has become.

Here, in such a write operation, at time ts in FIG. 8, the selection signal WE output from the write address generation circuit 32A rises after the clock signal WCK rises, and the write address generation circuit also rises. This is the time until the value of the write address WAD from the counter built in 32A changes. Further, the time from when the selection signal WE is in the H state and the value of the write address WAD is changed to when the writing to the corresponding memory cell is completed is tw. Then, the write time in the FIFO is (ts + t
w). Further, the cycle of the clock signal WCK needs to be equal to or longer than this (ts + tw) which is the cycle time twcy.

Next, FIG. 9 is a time chart showing a read operation in the conventional example.

The read operation in this conventional example is controlled by the clock signal RCK. First, at the time of reading the first data stored in the FIFO, the reset signal RRST is fallen at time t21.
Then, the counter incorporated in the read address generation circuit 42A is reset to "0", and the value of the read address RAD output from the counter becomes "0".

Then, at time t22, the reset signal R
The selection signal REN falls during the period from the rise of RST to the rise of the clock signal RCK at time t23. When the clock signal RCK rises, the L-state selection signal REN is fetched at this timing.

After this, at time t23, the clock signal RCK
After the rise of the read address generation circuit 42A, the select signal RE output from the read address generation circuit 42A rises and the memory cell array 10 corresponding to the read address RAD of "0"
The read operation of the output data DO from the memory cell is started, and the output data DO is output after a predetermined time.
It is output from A. Here, the selection signal RE is (RE =
This is a signal obtained by the logical operation of (REN bar) / RCK).

Next, at time t24, the clock signal R
CK rises. Then, the read address generation circuit 4
The value of the counter incorporated in 2A is incremented, and the read address RAD becomes "1". Further, the output data D0 is read from the corresponding memory cell of the memory cell array 10 corresponding to the read address RAD after a predetermined time.

Each time the clock signal RCK rises after time t25, the read address RAD is incremented, and the output data DO stored in the corresponding memory cell of the memory cell array 10 can be read.

Here, after the clock signal RCK rises, the selection signal RE output from the read address generation circuit 42A rises, and the counter incorporated in the read address generation circuit 42A is counted up so that the value of the read address RAD becomes Figure 9 shows the time until it changes.
Let time ts as shown inside. The output data DO stored in the corresponding memory cell of the memory cell array 10 after time ts from the rise of the clock signal RCK.
Is output from the output circuit 44A as time tr
(Tra and trb in FIG. 9). Then, the time (ts + tr) after the clock signal RCK rises is the time required to read the stored data. Further, the cycle of the clock signal RCK has a cycle time t.
It should be greater than or equal to rcy (ts + tr).

Here, since the output data is read from the memory cell connected to the read word line RWD0 in the period until time t26, the read word line RWD0 is in the H state in the period. Also, from time t27 to time t2
Since the data stored in the memory cell connected to the read word line RWD1 is read in the period of 8, the read word line RWD1 is in the H state in the period. Time t
In the period after 29, since the data stored in the memory cell connected to the read word line RWD2 is read,
In the period, the read word line RWD2 is in the H state.

[0026]

When the selection of the word line is switched in the period from time t16 to t17 in FIG. 8 and the selection of the word line is also switched in the period from time t18 to t19. Generally, the above-mentioned time tw is extended. This is because the access involving word line transition is generally longer than the access in which only the column address is changed. Further, when the time tw is extended in this way, the entire time required for memory access is also extended.

Further, in FIG. 9, from time t26 to t27.
When the selection of the word line in the period up to is switched,
Also when the selection of the word line in the period from time t28 to t29 is switched, the time tr tends to be extended due to the switching of the selection of the word line as in the case of the write operation. That is, at times tra and trb illustrated in FIG. 9, (tra <trb)
It becomes the relationship. Therefore, the memory access time required when the word line selection is switched becomes a bottleneck in the memory access time.

As described above, generally, in both the write operation and the read operation, the access in which the selection of the word line is switched takes more time than the access in which only the column address is changed. Therefore, in the case of such access in which the selection of the word line is switched, it becomes a bottleneck of the memory access time.

The present invention has been made to solve the above-mentioned conventional problems, and it is a word line when writing sequential data at consecutive addresses or when sequentially reading in a write order. By suppressing the extension of the access time of the dual port RAM that occurs when the selection is switched, the bottleneck of the access time of the dual port RAM is suppressed, and the access to the dual port RAM is efficiently performed with a relatively simple circuit configuration. An object is to provide a FIFO that can be performed at high speed.

[0030]

SUMMARY OF THE INVENTION The present invention is a row decoder,
The dual port random access memory is provided with a dual port random access memory having two sets of addressing means composed of word lines selectively driven by the row decoder, column selectors, and bit lines selected by the column selectors. In a first-in first-out memory device for reading data sequentially written to a memory at consecutive addresses from one addressing means in the order of writing from the other addressing means, the dual port random access for even row addresses Two sets of the dual port random access memories for the memory and the dual port random access memory for odd row addresses, and for every selection of the word line after sequential writing to all bits connected to one word line To access Altering the dual-port random access memory alternately generates addresses for sequentially writing data at consecutive addresses across two sets of the dual-port random access memories, and the dual-port random access memory At the time of memory selection switching, a write address generation circuit for driving a selective word line in the row decoder of the switching destination dual port random access memory in advance prior to the selection switching, and one word line. After sequential reading in the write order for all bits connected to,
Each time the selection of the word line is switched, the dual port random access memory to be accessed is changed to alternately provide addresses for sequential reading in the write order across the two sets of dual port random access memories. In addition, at the time of selection switching of the dual port random access memory, a read for selectively driving the word line in the row decoder of the switching destination of the dual port random access memory prior to the selection switching. An address generation circuit is provided to access the dual-port random access memory for even row addresses when writing sequential data at consecutive addresses and also when sequentially reading in write order.
The problem is solved by alternately accessing the dual port random access memory for odd row address every time the selection of the word line is switched.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a FIFO having a dual port RAM to which the present invention is applied.

In FIG. 1, a memory cell array 10
A, the write port word driver 12A, the write port column selector 14A, the read port word driver 16A, and the read port column selector 18A form a first dual port RAM for even row addresses. Next, the memory cell array 10B, the write port word driver 12B, and the write port column selector 1
The 4B, the read port word driver 16B, and the read port column selector 18B form a second dual port RAM for odd row addresses.

As described above, in contrast to the above-described conventional example, the present embodiment is characterized in that two dual port RAMs are provided.

Next, in the FIFO of this embodiment, in addition to these dual port RAMs, a write address generation circuit 32, an input circuit 34, a read address generation circuit 42, an output circuit 44, and a flag generation circuit 46. It has and.

Here, the memory cell array 10A has a structure as shown in FIG. In FIG. 2, write word lines WWD0, 2, 4, 6 and read word lines RWD0, 2, 4, 6 are shown.
That is, in the memory cell array 10A, only even row addresses exist.

Next, the memory cell array 10B is constructed as shown in FIG. As shown in FIG. 3, in the memory cell array 10B, write word lines WWD1,
3, 5, 7 and read word lines RWD1, 3, 5, 7
Is provided. In this way, the memory cell array 10
In B, only odd row addresses are present.

Further, these memory cell arrays 10A and 1
In 0B, these dual port RAMs are alternately selected and switched every time the word line is selectively switched after each access to the four memory cells connected to one word line. In addition, the memory cell arrays 10A and 1 of the present embodiment
Two 0B are one memory cell array 1 of the above-mentioned conventional example.
Equivalent to 0. In this embodiment, the conventional dual port RAM is divided into two, one for even row addresses and one for odd addresses.

The write address generation circuit 32 determines which dual port RAM is used in the write operation for storing the input data DI. That is, of the addresses determined by the value of the counter incorporated in the write address generation circuit 32, if the column address value is an even number, the dual port R for even row addresses is used.
AM is selected, and if odd, a dual port RAM for odd row address is selected.

Dual port RAM for even row addresses
When is selected, data is written to the memory cell array 10A via the write port column selector 14A. On the other hand, when the dual port RAM for odd row addresses is selected, data is stored in the memory cell array 10B via the write port column selector 14B.

When reading the stored data, which dual port RAM is to be used is determined by the value of the counter incorporated in the read address generating circuit 42. That is, of the addresses indicated by the value of the counter, if the row address is even, the dual port RAM for even row addresses is selected, and if it is odd, the dual port RAM for odd row addresses is selected.

Dual port RAM for even row addresses
When is selected, the data stored in the memory cell array 10A is read out via the read port column selector 18A. On the other hand, when the dual port RAM for odd row address is selected, the read port column selector 18
Through B, the data stored in the memory cell array 10B is read.

FIG. 4 is a time chart showing the write operation of this embodiment.

In the write address generation circuit 32,
As shown in FIG. 4, the built-in counter is reset to "0" at the falling edge of the reset signal WRST and then incremented at every rising edge of the clock signal WCK to change the write address WAD. This write address WAD is predecoded in the write address generation circuit 32, and the write port word driver 1
2A and the write port column selector 14A are used, or whether the write port word driver 12B and the write port column selector 14B are used, and
Output the corresponding addresses for these. After that, the input data DI is written to the corresponding memory cell of the memory cell array 10A or 10B.

From time t31 to time t37, the memory cell array 10A is accessed. Time t3
From 8 to time t39, the memory cell array 10B is accessed. From time t40, the memory cell array 10
Access A.

Here, times t33 to t37 in FIG.
Then, only the column address is changed when the clock signal WCK rises. On the other hand, between time t37 and t38 and between time t39 and t40, the column address becomes "0" and the row address is changed. When changing the row address, the dual port RAM is switched in this embodiment.

Further, when such a dual port RAM is switched, the word line is driven in advance by the row decoder of the destination dual port RAM prior to the switching. Therefore, in this embodiment, the access time can be suppressed even when such word line switching is involved.

Comparing the write operation in the present embodiment shown in FIG. 4 with the conventional operation shown in FIG. 8, the fall of the write word line WWD0 output to the dual port RAM for even row address is used as a reference. As
The rising timing of the write word line WWD1 output to the dual port RAM for odd-numbered row address is advanced. Also, the write word line WW output to the dual port RAM for odd row address
With reference to the falling edge of D1, the rising timing of the write word line WWD2 to be output to the dual port RAM for even row address is advanced.
As described above, in the present embodiment, not only the two dual-port RAMs are alternately selected, but the word line to be switched to is driven in advance, so that the access time is extended when the selection of the word line is switched. It is possible to suppress.

FIG. 5 is a time chart showing the read operation of this embodiment.

In the read address generation circuit 42,
As shown in FIG. 5, the built-in counter is reset to "0" at the rising edge of the reset signal RRST and then incremented at every rising edge of the clock signal RCK to change the read address RAD. This read address RAD is predecoded in the read address generation circuit 42, and the read port word driver 1
6A and the read port column selector 18A are used, or whether the read port word driver 16B and the read port column selector 18B are used,
Output the corresponding addresses for these. After that, the output data DO is read from the corresponding memory cell of the memory cell array 10A or 10B.

From time t41 to time t47, the memory cell array 10A is accessed. Time t4
From 8 to time t49, the memory cell array 10B is accessed. From time t50, the memory cell array 10 starts
Access A.

Here, times t43 to t47 in FIG.
Then, only the column address is changed when the clock signal RCK rises. On the other hand, between time t47 and t48 and between time t49 and t50, the column address becomes "0" and the row address is changed. When changing the row address, the dual port RAM is switched in this embodiment.

When such dual port RAM is switched, the word line is driven in advance by the row decoder of the destination dual port RAM prior to the switching. Therefore, in this embodiment, the access time can be suppressed even when such word line switching is involved.

As shown in FIG. 5, two dual port R
Even in the read operation in this embodiment using AM alternately, first, compared to the conventional example shown in FIG.
The rise of the read word line RWD1 output to the odd port address dual port RAM is accelerated with reference to the fall of the read word line RWD0 output to the even port address dual port RAM. Also, dual port R for odd row address
Read word line RWD that is output to AM and that is output to the dual port RAM for even row addresses, based on the fall of read word line RWD1
The rising timing of 2 has been accelerated. As described above, also in the read operation, in the present embodiment, not only the two dual port RAMs are used alternately, but when the selective switching of the dual port RAM is performed, the dual port of the switching destination is selected prior to the selective switching. The row decoder of the RAM selectively drives the word lines. Therefore, even if the selection of the word line is switched during the read operation, the access time is not extended according to the present embodiment.

Here, the input data DI and the output data D
Let O be 1 bit. Further, in each of the memory cell arrays 10A and 10B, it is assumed that the number of rows is M and the number of columns is N, and the memory cells are composed of a total of (M × N) memory cells. Then, the bit width of the row address generated by the write address generation circuit 32 or the read address generation circuit 42 is (log 2M / log 2) bits, and the bit width of the column address is (log 2N / log 2) bits.

At this time, column addresses 0 to (N-1) are assigned to the dual port RAM for even row addresses, and column addresses N to (2N-1) are assigned to the dual port RAM for odd row addresses. Assigned. As described above, the present embodiment is not limited to FIG. 2 and FIG. 3 described above, and the memory cell array 10 having an arbitrary number of rows and columns can be used.
It can be applied to those using A or 10B. Note that, as shown in FIGS. 2 and 3, in the above-described present embodiment,
(M = 8) and (N = 4).

As described above, in the present embodiment, while applying the present invention, two dual port RAMs are alternately used, and when the dual port RAMs are selectively switched,
Prior to the selection switching, the switching destination dual port R
The word line can be driven by the AM row decoder. Therefore, according to the present embodiment, the access time of the dual port RAM that occurs when the selection of the word line is switched at the time of writing sequential data at consecutive addresses or at the time of sequential reading in the writing order. By suppressing the extension of the dual port RAM, the bottleneck of the access time of the dual port RAM is suppressed, and the dual port RAM
It is possible to obtain an excellent effect that the access to can be efficiently performed at high speed with a relatively simple circuit configuration.

[0058]

As described above, according to the present invention, it occurs when the selection of the word line is switched at the time of writing the sequential data at the consecutive addresses or at the time of the sequential reading in the writing order. The dual port RAM
By suppressing the extension of the access time of the dual port RAM, the bottleneck of the access time of the dual port RAM can be suppressed, and the excellent effect that the access to the dual port RAM can be performed efficiently and at high speed with a relatively simple circuit configuration. Obtainable.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a FIFO using a dual port RAM to which the present invention is applied.

FIG. 2 is a diagram showing a memory cell configuration of a dual port RAM for even row addresses used in the above embodiment.

FIG. 3 is a diagram showing a memory cell configuration of a dual port RAM for odd row addresses used in the above embodiment.

FIG. 4 is a time chart showing a write operation in the embodiment.

FIG. 5 is a time chart showing a read operation in the embodiment.

FIG. 6: FIFO using conventional dual-port RAM
Block diagram showing the configuration of

FIG. 7 is a diagram showing a memory cell configuration of the conventional dual port RAM.

FIG. 8 is a time chart showing a write operation in the conventional example.

FIG. 9 is a time chart showing a read operation in the conventional example.

[Explanation of symbols]

 10, 10A, 10B ... Memory cell array 12, 12A, 12B ... Write port word driver 14, 14A, 14B ... Write port column selector 16, 16A, 16B ... Read port word driver 18, 18A, 18B ... Read port column selector 32, 32A ... Write address generation circuit 34, 34A ... Input circuit 42, 42A ... Read address generation circuit 44, 44A ... Output circuit 46, 46A ... Flag generation circuit WEN, WE, REN, RE ... Selection signal WRST, RRST ... Reset signal WCK , RCK ... Clock signal WWD0 to WWD7 ... Write word line RWD0 to RWD7 ... Read word line DI ... Input data DO ... Output data FUL ... Full flag EPT ... Empty flag ts, tr ... Time WAD ... Write address RA ... read address

Claims (1)

[Claims] 1. A dual-port random access memory having two sets of row decoders, word lines selectively driven by the row decoders, column selectors, and addressing means composed of bit lines selected by the column selectors. A first-in / first-out memory device for reading data sequentially written to the dual-port random access memory from one addressing means at consecutive addresses in the order of writing from the other addressing means. Two sets of the dual port random access memories, the dual port random access memory for address and the dual port random access memory for odd row address, and after every sequential writing to all bits connected to one word line Of word lines By changing the dual port random access memory to be accessed at every switching, an address for writing data sequentially at two consecutive addresses is generated alternately over the two sets of dual port random access memories. At the same time, when the dual port random access memory is selectively switched, a write address generation is performed in advance to selectively drive the word line in the row decoder of the dual port random access memory which is the switching destination before the selective switching. The circuit and every time the selection of the word line is switched after the sequential reading of the writing order for all the bits connected to one word line,
Altering the dual port random access memory to be accessed alternately generates addresses for sequential read in the write order across two sets of the dual port random access memories, and the dual port random access memory When the access memory is selectively switched, a read address generating circuit for driving the word line selectively in the row decoder of the dual port random access memory of the switching destination is provided prior to the selective switching. When writing sequential data at the address
Further, even in the sequential reading in the write order, the word line selection is performed for the access to the dual port random access memory for even row addresses and the access to the dual port random access memory for odd row addresses. A first-in / first-out memory device characterized in that it is performed alternately every time it is switched.