JPH07231449A - Encoder and decoder for picture signal - Google Patents

Abstract

PURPOSE:To best correct the decoded picture signal with a simple configuration. CONSTITUTION:An encoder 18 of an encoding device 1 encodes a PST flag showing the encoding condition of a pre-filter 21 together with the bit stream being picture data at the same time. The bit stream and the PST flag are sent to a recording medium 3 at the same time. The bit stream and the PST flag encoded and stored in the recording medium 3 are decoded by a decoder 31 of a decoding device 2. The decoded bit stream is inputted to a format conversion circuit 32 and it is converted from the block format into the frame format. On the other hand, the decoded PST flag is sent to a post filter 22 which selects the optimal filter by the PST flag.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal coding apparatus and an image signal decoding apparatus suitable for use in compressing and transmitting moving image data.

[0002]

2. Description of the Related Art When moving image data is digitally recorded on a magneto-optical disk, a magnetic tape or the like, or transmitted through a predetermined transmission medium, the data is encoded and compressed to reduce the amount of data. I am trying.

In a system for transmitting a moving image signal to a remote place such as a video conference system or a video telephone system, for example, in order to efficiently use a transmission line,
The image signal is compressed and encoded by utilizing the line correlation and the inter-frame correlation of the video signal.

By utilizing the line correlation, the image signal can be compressed by, for example, DCT (discrete cosine transform) processing.

Further, by utilizing the inter-frame correlation, the image signal can be further compressed and encoded. For example, as shown in FIG. 11, when frame images PC1, PC2, and PC3 are generated at times t1, t2, and t3, respectively, the difference between the image signals of the frame images PC1 and PC2 is calculated to generate PC12. Also, the difference between the frame images PC2 and PC3 is calculated to generate PC23. Normally, the images of frames that are temporally adjacent do not have such a large change, so when the difference between the two is calculated, the difference signal has a small value. Therefore, if this difference signal is encoded, the code amount can be compressed.

However, the original image cannot be restored by transmitting only the differential signal. Therefore, the image of each frame is set to any one of three types of pictures of I picture, P picture, and B picture,
The image signal is compressed and encoded.

That is, for example, as shown in FIG. 12, image signals of 17 frames from frames F1 to F17 are set as a group of pictures (GOP), which is one unit of processing. Then, the image signal of the leading frame F1 is encoded as an I picture, the second frame F2 is processed as a B picture, and the third frame F3 is processed as a P picture. Hereinafter, the fourth and subsequent frames F4 to F17 are alternately processed as a B picture or a P picture.

As the image signal of the I picture, the image signal for one frame is transmitted as it is. On the other hand, as the image signal of the P picture, basically, as shown in FIG.
As shown in FIG. 2 (A), the difference from the image signal of the I picture or P picture preceding it in time is transmitted. Further, as the image signal of the B picture, basically, as shown in FIG. 12B, a difference from the average value of both the temporally preceding frame and the subsequent frame is obtained, and the difference is encoded. Turn into.

FIG. 13 shows the principle of the method of encoding a moving image signal in this way. As shown in the figure, since the first frame F1 is processed as an I picture, it is directly transmitted to the transmission line as the transmission data F1X (intra-picture coding). On the other hand, since the second frame F2 is processed as a B picture, the frame F1 that temporally precedes and the frame F that temporally follows.
The difference (prediction error) from the average value of 3 is calculated, and the difference is transmitted as the transmission data F2X.

However, there are four types of processing as the B picture, which will be described in more detail. The first process is to transmit the data of the original frame F2 as it is as the transmission data F2X (SP1) (intra (intra-picture prediction) coding), and is the same process as in the I picture. The second processing is to calculate the difference from the frame F3 that is temporally later and transmit the difference (SP2) (backward predictive coding). The third process is to transmit a difference (SP3) from the temporally preceding frame F1 (forward predictive coding). Further, the fourth process is to generate a difference (SP4) between the average value of the frame F1 preceding in time and the average value of the frame F3 following, and transmit this as the transmission data F2X (bidirectional predictive coding). .

Of these four methods, the method that minimizes the amount of transmission data is adopted.

When transmitting the difference data, a motion vector x1 (motion vector between frames F1 and F2) between the difference image and the image of the frame (prediction image) for which the difference is calculated (for forward prediction). , Or x2 (frame F
The motion vector between 3 and F2) (for backward prediction) or both x1 and x2 (for bidirectional prediction) are transmitted with the difference data.

In the frame F3 of the P picture, the frame F1 temporally preceding is used as a prediction image to calculate a difference signal (SP3) from the frame and a motion vector x3, which is transmitted as transmission data F3X. (Forward predictive coding). Alternatively, the data of the original frame F3 is directly transmitted as the data F3X (SP
1) (Intra coding). As in the case of the B picture, whichever method is used for transmission is selected so that less transmission data is transmitted.

FIG. 14 shows an example of the configuration of an apparatus which encodes and transmits a moving image signal based on the above-mentioned principle, and decodes this. The encoding device 1 encodes the input video signal and transmits it to the recording medium 3 as a transmission path. Then, the decoding device 2 reproduces the signal recorded on the recording medium 3, decodes the signal, and outputs the decoded signal.

In the encoding device 1, the input video signal is input to the pre-processing circuit 11, where the luminance signal and the chrominance signal (color difference signal in this embodiment) are separated, and each is an A / D converter. A / D conversion is performed at 12 and 13. A /
The video signal converted into a digital signal by A / D conversion by the D converters 12 and 13 is supplied to and stored in the frame memory 14 after being processed by the prefilter 21.
The frame memory 14 stores the luminance signal in the luminance signal frame memory 15 and the color difference signal in the color difference signal frame memory 16, respectively.

The pre-filter 21 performs a process for improving coding efficiency. This is, for example, a noise removal filter and, for example, a filter for limiting the band.

The format conversion circuit 17 converts the frame format signal stored in the frame memory 14 into
Convert to block format signal. That is, FIG.
As shown in FIG. 5, the video signal stored in the frame memory 14 is frame format data in which V lines of H dots are collected per line. The format conversion circuit 17 converts this 1-frame signal into 1
It is divided into N slices in units of 6 lines. Then, each slice is divided into M macroblocks. Each macroblock is composed of a luminance signal corresponding to 16 × 16 pixels (dots), and this luminance signal further includes a block Y [1] in units of 8 × 8 dots.
To Y [4]. Then, this 16 × 16 dot luminance signal includes an 8 × 8 dot Cb signal and an 8 × 8 dot Cb signal.
An 8-dot Cr signal is supported.

The data converted into the block format in this way is supplied from the format conversion circuit 17 to the encoder 18, where it is encoded. The details will be described later with reference to FIG.

The signal encoded by the encoder 18 is output to the transmission line as a bit stream. For example, it is supplied to the recording circuit 19 and recorded on the recording medium 3 as a digital signal.

The data reproduced from the recording medium 3 by the reproducing circuit 30 is supplied to the decoder 31 of the decoding device 2 and decoded. For details of the decoder 31,
It will be described later with reference to FIG.

The data decoded by the decoder 31 is input to the format conversion circuit 32 and converted from the block format to the frame format. Then, the luminance signal of the frame format is supplied to and stored in the luminance signal frame memory 34 of the frame memory 33, and the color difference signal is supplied to and stored in the color difference signal frame memory 35. The luminance signal and the color difference signal read from the luminance signal frame memory 34 and the color difference signal frame memory 35 are processed by the post filter 22 and then,
The D / A converters 36 and 37 respectively perform D / A conversion, supply to the post-processing circuit 38, and synthesize. And
For example, it is output and displayed on a display such as a CRT (not shown).

The post filter 22 performs processing for improving the image quality. For example, it is a filter for removing block distortion and mosquito noise.

Next, an example of the structure of the encoder 18 will be described with reference to FIG.

The image data to be encoded is input to the motion vector detection circuit 50 in macroblock units.
The motion vector detection circuit 50 processes the image data of each frame as an I picture, a P picture, or a B picture according to a preset predetermined sequence.
The image of each frame that is sequentially input is
Which of P and B pictures is to be processed is predetermined (for example, as shown in FIG. 15, the group of pictures composed of frames F1 to F17 is I, B, P, B, P, ... B, P).

The image data of the frame (for example, the frame F1) processed as the I picture is transmitted from the motion vector detecting circuit 50 to the front original image portion 51a of the frame memory 51.
The image data of the frame (for example, frame F2) that is transferred and stored in the reference original image section 51b is the image data of the frame (for example, frame F3) that is transferred and stored in the reference original image portion 51b. , And is transferred to and stored in the rear original image portion 51c.

At the next timing, B
When an image of a frame to be processed as a picture (frame F4) or P picture (frame F5) is input, the image data of the first P picture (frame F3) stored in the backward original image portion 51c until then is It is transferred to the front original image portion 51a, and the next B picture (frame F
The image data of 4) is stored (overwritten) in the reference original image portion 51b, and the image data of the next P picture (frame F5) is stored (overwritten) in the backward original image portion 51c. Such an operation is sequentially repeated.

The signal of each picture stored in the frame memory 51 is read therefrom, and the prediction mode switching circuit 52 performs the frame prediction mode process or the field prediction mode process. Furthermore, under the control of the prediction determination circuit 54, the arithmetic unit 53 performs intra-picture prediction, forward prediction, backward prediction, or bidirectional prediction. Which of these processes is to be performed is determined in accordance with the prediction error signal (difference between the reference image to be processed and the predicted image corresponding thereto). Therefore, the motion vector detection circuit 50
The sum of absolute values of the prediction error signals (may be the sum of squares) used for this determination is generated.

Here, the frame prediction mode and field prediction mode in the prediction mode switching circuit 52 will be described.

When the frame prediction mode is set, the prediction mode switching circuit 52 supplies the four luminance blocks Y supplied from the motion vector detection circuit 50.
[1] to Y [4] are directly output to the arithmetic unit 53 in the subsequent stage. That is, in this case, as shown in FIG. 8, the data of the odd field lines and the data of the even field lines are mixed in each luminance block. In this frame prediction mode, 4
Prediction is performed in units of luminance blocks (macroblocks), and one motion vector is associated with four luminance blocks.

On the other hand, the prediction mode switching circuit 5
2 in FIG. 17A in the field prediction mode.
The signal input from the motion vector detection circuit 50 in the configuration shown in FIG. 17 is converted into luminance blocks Y [1] and Y [2] among four luminance blocks as shown in FIG. Only the dots of the line
The other two luminance blocks Y [3] and Y [4] are configured by the data of the even field lines, and the arithmetic unit 5
Output to 3. In this case, one motion vector is associated with the two luminance blocks Y [1] and Y [2], and the other two luminance blocks Y [3] and Y [4].
Is associated with one other motion vector.

The motion vector detection circuit 50 outputs the sum of absolute values of prediction errors in the frame prediction mode and the sum of absolute values of prediction errors in the field prediction mode to the prediction mode switching circuit 52. Prediction mode switching circuit 5
2 compares the absolute value sums of the prediction errors in the frame prediction mode and the field prediction mode, performs a process corresponding to the prediction mode having the smaller value, and outputs the data to the arithmetic unit 53.

However, such processing is actually performed by the motion vector detection circuit 50. That is, the motion vector detection circuit 50 outputs a signal having a configuration corresponding to the determined mode to the prediction mode switching circuit 52, and the prediction mode switching circuit 52 outputs the signal as it is to the arithmetic unit 53 in the subsequent stage.

In the frame prediction mode, the color difference signal is supplied to the arithmetic unit 53 in a state in which line data of odd fields and line data of even fields are mixed, as shown in FIG. To be done. Further, in the field prediction mode, as shown in FIG. 17B, the upper half (4 lines) of each color difference block Cb, Cr is an odd field corresponding to the luminance blocks Y [1], Y [2]. The lower half (4 lines) is a color difference signal, and the lower half (4 lines) is an even field color difference signal corresponding to the luminance blocks Y [3] and Y [4].

Further, the motion vector detection circuit 50 uses the prediction determination circuit 54 to predict the intra-image,
A sum of absolute values of prediction errors for determining whether to perform forward prediction, backward prediction, or bidirectional prediction is generated.

That is, the sum ΣAij of the signals Aij of the macroblocks of the reference image is used as the sum of the absolute values of the prediction errors of the intra-picture prediction.
Of the absolute value | ΣAij | of the macroblock signal and the sum Σ | Aij | of the absolute value | Aij | of the macroblock signal Aij. Also, as the sum of absolute values of prediction errors in forward prediction, the sum Σ | A of the absolute value | Aij-Bij | of the difference Aij-Bij between the signal Aij of the macroblock of the reference image and the signal Bij of the macroblock of the predicted image.
ij-Bij | is calculated. Further, the sum of absolute values of the prediction errors of the backward prediction and the bidirectional prediction is also obtained in the same manner as in the case of forward prediction (the predicted image is changed to a predicted image different from that in forward prediction).

The sum of these absolute values is supplied to the prediction determination circuit 54. The prediction determination circuit 54 selects the smallest sum of absolute values of prediction errors of forward prediction, backward prediction, and bidirectional prediction as the sum of absolute values of prediction errors of inter prediction. Furthermore, the sum of the absolute values of the prediction error of the inter prediction and the sum of the absolute values of the prediction errors of the intra-picture prediction are compared, the smaller one is selected, and the mode corresponding to the selected sum of the absolute values is set as the prediction mode. select. That is, if the sum of absolute values of prediction errors in intra-picture prediction is smaller, the intra-picture prediction mode is set. If the sum of absolute values of prediction errors in inter prediction is smaller, the mode in which the corresponding sum of absolute values is the smallest is set among the forward prediction, backward prediction, and bidirectional prediction modes.

In this way, the motion vector detection circuit 50
Supplies the signal of the macroblock of the reference image to the arithmetic unit 53 via the prediction mode switching circuit 52 in a configuration corresponding to the mode selected by the prediction mode switching circuit 52 among the frame or field prediction modes. Of the four prediction modes, the prediction determination circuit 54
The motion vector between the prediction image and the reference image corresponding to the prediction mode selected by is detected, and the variable length coding circuit 5
8 and the motion compensation circuit 65. As described above, the motion vector that minimizes the sum of absolute values of the corresponding prediction errors is selected.

The prediction determination circuit 54, when the motion vector detection circuit 50 is reading the image data of the I picture from the front original image portion 51a, uses the intra-frame or field (image) prediction mode (motion compensation is performed as the prediction mode. Mode), and the switch 53d of the calculation unit 53 is set.
To the contact a side. As a result, the I-picture image data is input to the DCT mode switching circuit 55.

As shown in FIG. 18A or FIG. 18B, the DCT mode switching circuit 55 is a state in which the data of four luminance blocks are mixed with the lines of odd fields and lines of even fields ( Either the frame DCT mode) or the separated state (field DCT mode) is output to the DCT circuit 56.

That is, the DCT mode switching circuit 55 is
Mixed data of odd field and even field D
Comparing the coding efficiency in the case of CT processing and the coding efficiency in the case of DCT processing in the separated state,
Select a mode with good coding efficiency.

For example, the input signal is shown in FIG.
As shown in, the odd field and even field lines are mixed, and the difference between the signal of the odd field line and the signal of the even field that are vertically adjacent to each other is calculated, and then the sum of the absolute values (or squared value) is calculated. Sum). In addition, as shown in FIG. 18B, the input signal has a structure in which odd field lines and even field lines are separated, and the difference between the signals of the vertically adjacent odd field lines and the even field lines are set. The difference between the signals is calculated, and the sum (or sum of squares) of the absolute values of each is calculated. Further, both (sum of absolute values) are compared, and the DCT mode corresponding to a smaller value is set. That is, if the former is smaller, the frame DCT mode is set, and if the latter is smaller, the field DCT mode is set.

Then, the data having the structure corresponding to the selected DCT mode is output to the DCT circuit 56, and the DCT flag indicating the selected DCT mode is set to the variable length coding circuit 58, the DCT block rearranging circuit 62, and the motion. Output to the compensation circuit 65.

The prediction mode in the prediction mode switching circuit 52 (FIG. 17) and the DCT mode switching circuit 5
As is clear by comparing the DCT modes in FIG. 5 (FIG. 18), the data structures in both modes are substantially the same for the luminance block.

When the frame prediction mode (a mode in which odd lines and even lines are mixed) is selected in the prediction mode switching circuit 52, the frame DCT mode (in which odd lines and even lines are mixed) is also selected in the DCT mode switching circuit 55. If the field prediction mode (a mode in which the data in the odd field and the data in the even field are separated) is selected in the prediction mode switching circuit 52, the field in the DCT mode switching circuit 55 is high. There is a high possibility that the DCT mode (mode in which the data of the odd field and the data of the even field are separated) is selected.

However, this is not always the case, and the prediction mode switching circuit 52 determines the mode so that the sum of the absolute values of the prediction errors becomes small, and the DCT mode switching circuit 55 encodes the mode. The mode is determined so that the efficiency is good.

The I-picture image data output from the DCT mode switching circuit 55 is input to the DCT circuit 56, subjected to DCT (discrete cosine transform) processing, and converted into DCT coefficients. This DCT coefficient is input to the quantization circuit 57, quantized in a quantization step corresponding to the data storage amount (buffer storage amount) of the transmission buffer 59, and then,
It is input to the variable length coding circuit 58.

The variable length coding circuit 58 is a quantization circuit 57.
In accordance with the supplied quantization step (scale), the image data (in this case, I picture data) supplied from the quantization circuit 57 is converted into a variable length code such as a Huffman code and transmitted. Output to the buffer 59.

In the variable length coding circuit 58, a quantization step (scale) is set by the quantization circuit 57, and a prediction mode (intra-picture prediction, forward prediction, backward prediction, or bidirectional prediction is set by the prediction determination circuit 54. Mode indicating whether or not the motion vector is detected by the motion vector detection circuit 50,
A prediction flag (a flag indicating whether the frame prediction mode or the field prediction mode has been set) is set by the prediction mode switching circuit 52, and a DCT flag (whether the frame DCT mode or the field DCT mode is set by the DCT mode switching circuit 55 is set. Has been input, and these are also variable length coded.

The transmission buffer 59 temporarily stores the input data and stores the data corresponding to the storage amount in the quantizing circuit 57.
Output to. When the remaining amount of data increases to the allowable upper limit value, the transmission buffer 59 increases the quantization scale of the quantization circuit 57 by the quantization control signal,
The amount of quantized data is reduced. On the contrary, when the data remaining amount decreases to the allowable lower limit value, the transmission buffer 59 uses the quantization control signal to quantize circuit 57.
The data amount of the quantized data is increased by reducing the quantization scale of. In this way, overflow or underflow of the transmission buffer 59 is prevented.

Then, the data accumulated in the transmission buffer 59 is read out at a predetermined timing, output to the transmission path, and recorded on the recording medium 3, for example.

On the other hand, the I picture data output from the quantization circuit 57 is input to the inverse quantization circuit 60 and inversely quantized in accordance with the quantization step supplied from the quantization circuit 57. The output of the inverse quantization circuit 60 is IDCT
It is input to the (inverse DCT) circuit 61, subjected to inverse DCT processing, and then input to the DCT block rearranging circuit 62. D
The CT block rearrangement circuit 62 rearranges the input data according to the prediction flag supplied from the prediction mode switching circuit 52 and the DCT flag supplied from the DCT mode switching circuit 55.

That is, when the frame prediction mode is set in the prediction mode switching circuit 52, the data read from the motion compensation circuit 65 and supplied to the arithmetic unit 53 is the odd field data and the even field data. It is said that the and are mixed. This data is also supplied to the calculator 63. Therefore, the DCT block rearrangement circuit 62 converts the data supplied from the IDCT circuit 61 when the frame DCT mode is set.
When the field DCT mode is set, the data in the odd field and the data in the even field are separated, so that the data is rearranged in a mixed state. , To the computing unit 63.

On the other hand, in the prediction mode switching circuit 52, when the field prediction mode is set, the data supplied from the motion compensation circuit 65 to the arithmetic unit 53 is the data of the odd field and the data of the even field separated. It is in a state. Therefore, when the field DCT mode is set by the DCT mode switching circuit 55, the DCT block rearranging circuit 58 is I
The data output from the DCT circuit 61 is supplied to the arithmetic unit 63 as it is. However, when the frame DCT mode is set, the data of the odd field and the data of the even field are mixed. ,
Each of them is sorted into a separated state and is output to the computing unit 63.

That is, the DCT block rearrangement circuit 58.
Is IDCT so that it has the same arrangement state as the arrangement state of the data supplied from the motion compensation circuit 65 to the arithmetic unit 53.
The data output from the circuit 61 is rearranged.

In this case, since the data output from the IDCT circuit 61 is I picture data, it is considered as intra-picture prediction. Therefore, when the DCT mode switching circuit 55 is outputting the frame DCT flag, I
The data output from the DCT circuit 61 is directly transmitted via the calculator 63 to the forward prediction image section 6 of the frame memory 65.
5a and stored. Also, the field DCT
When the flag is output, the data is sorted and then stored.

When the motion vector detection circuit 50 processes the sequentially input image data of each frame as a picture of I, B, P, B, P, B ... After processing the image data of another frame as an I picture, before processing the image of the next input frame as a B picture, the image data of the next input frame is processed as a P picture. This is because a B picture is accompanied by backward prediction and cannot be decoded unless a P picture as a backward predicted image is prepared in advance.

Then, the motion vector detecting circuit 50 starts the processing of the image data of the P picture stored in the backward original image portion 51c after the processing of the I picture. Then, as in the case described above, the sum of absolute values of the inter-frame difference (prediction error) in macroblock units is supplied from the motion vector detection circuit 50 to the prediction mode switching circuit 52 and the prediction determination circuit 54. Prediction mode switching circuit 52
And the prediction determination circuit 54 sets the frame / field prediction mode, or the prediction mode of intra-picture prediction, forward prediction, backward prediction, or bidirectional prediction in accordance with the sum of the absolute values of the prediction errors of the macroblock of the P picture. To do.

When the intra-picture prediction mode is set, the arithmetic unit 53 switches the switch 53d to the contact a side as described above. Therefore, this data is transmitted to the transmission line via the DCT mode switching circuit 55, the DCT circuit 56, the quantization circuit 57, the variable length coding circuit 58, and the transmission buffer 59, like the I picture data. Further, this data is the inverse quantization circuit 60, the IDCT circuit 61, the DC
It is supplied to and stored in the backward predicted image portion 64b of the frame memory 64 via the T block rearrangement circuit 62 and the computing unit 63.

In the forward prediction mode, the switch 53d is switched to the contact b, and the image data (in this case, the I picture image) stored in the forward prediction image portion 64a of the frame memory 64 is read out. The motion compensation circuit 65 performs motion compensation corresponding to the motion vector output from the motion vector detection circuit 50. That is, when the prediction determination circuit 54 instructs the motion compensation circuit 65 to set the forward prediction mode, the motion compensation circuit 65 sets the read address of the forward predicted image portion 64a to the position of the macroblock currently output by the motion vector detection circuit 50. Data is read out by shifting from the corresponding position by an amount corresponding to the motion vector, and predicted image data is generated.

The predicted image data output from the motion compensation circuit 65 is supplied to the calculator 53a. Calculator 53a
Subtracts the predicted image data corresponding to this macroblock supplied from the motion compensation circuit 65 from the data of the macroblock of the reference image supplied from the prediction mode switching circuit 52, and outputs the difference (prediction error). To do. This difference data is the DCT mode switching circuit 55, DC
T circuit 56, quantization circuit 57, variable length coding circuit 58,
It is transmitted to the transmission line via the transmission buffer 59. Also,
This difference data is stored in the inverse quantization circuit 60 and the IDCT circuit 6
1, locally decoded by the DCT block rearrangement circuit 62 and input to the arithmetic unit 63.

The calculator 63 is also supplied with the same data as the predicted image data supplied to the calculator 53a. The calculator 63 adds the predicted image data output by the motion compensation circuit 65 to the difference data output by the DCT block rearrangement circuit 62. As a result, the image data of the original (decoded) P picture is obtained. The image data of the P picture is supplied to and stored in the backward predicted image portion 64b of the frame memory 64.

In this way, the motion vector detection circuit 50 executes the processing of the B picture after the data of the I picture and the P picture are stored in the forward prediction image section 64a and the backward prediction image section 64b, respectively. The prediction mode switching circuit 52 and the prediction determination circuit 54 correspond to the magnitude of the sum of absolute values of inter-frame differences in macroblock units,
The frame / field mode is set, and the prediction mode is set to any of the intra-picture prediction mode, the forward prediction mode, the backward prediction mode, and the bidirectional prediction mode.

As described above, in the intra-picture prediction mode or the forward prediction mode, the switch 53d has the contact a or b.
Can be switched to. At this time, the same processing as in the P picture is performed and the data is transmitted.

On the other hand, when the backward prediction mode or the bidirectional prediction mode is set, the switch 53d is switched to the contact c or d, respectively.

In the backward prediction mode in which the switch 53d is switched to the contact c, the image (in this case, P picture image) data stored in the backward predicted image section 64b is read out and the motion compensation circuit 65 is read. Thus, motion compensation is performed corresponding to the motion vector output by the motion vector detection circuit 50. That is, the motion compensation circuit 65 sets the read address of the backward predicted image portion 64b to the position of the macroblock currently output by the motion vector detection circuit 50 when the backward determination mode setting is instructed by the prediction determination circuit 54. Data is read out by shifting from the corresponding position by an amount corresponding to the motion vector, and predicted image data is generated.

The predicted image data output from the motion compensation circuit 65 is supplied to the calculator 53b. Calculator 53b
Subtracts the prediction image data supplied from the motion compensation circuit 65 from the macroblock data of the reference image supplied from the prediction mode switching circuit 52, and outputs the difference. This difference data is stored in the DCT mode switching circuit 5
5, the DCT circuit 56, the quantization circuit 57, the variable length coding circuit 58, and the transmission buffer 59.

In the bidirectional prediction mode in which the switch 53d is switched to the contact point d, the image data (in this case, the I picture image) stored in the forward predicted image portion 64a and the backward predicted image portion 64b are stored. Image data (in this case, an image of P picture) is read out, and the motion compensation circuit 65 causes the motion vector detection circuit 5 to read.
Motion compensation is performed according to the motion vector output by 0.
That is, when the prediction determination circuit 54 instructs the bidirectional prediction mode to be set, the motion compensation circuit 65 sets the read addresses of the forward prediction image portion 64a and the backward prediction image portion 64b to the read addresses.
The motion vector detection circuit 50 shifts from the position corresponding to the position of the macro block currently output by the amount corresponding to the motion vector (in this case, there are two motion vectors for the forward prediction image and the backward prediction image). Data is read out to generate predicted image data.

The predicted image data output from the motion compensation circuit 65 is supplied to the calculator 53c. Calculator 53c
Subtracts the average value of the predicted image data supplied from the motion compensation circuit 65 from the data of the macroblock of the reference image supplied from the motion vector detection circuit 50, and outputs the difference. This difference data is transmitted to the transmission line via the DCT mode switching circuit 55, the DCT circuit 56, the quantization circuit 57, the variable length coding circuit 58, and the transmission buffer 59.

The B picture image is not stored in the frame memory 64 because it is not used as a predicted image of another image.

In the frame memory 64, the forward predictive image section 64a and the backward predictive image section 64b are bank-switched as necessary, and a predetermined reference image
The one stored in one or the other can be switched and output as the forward prediction image or the backward prediction image.

In the above description, the luminance block is mainly described, but the chrominance block is also processed and transmitted in units of macro blocks similar to the macro block shown in FIG. The motion vector used for processing the color difference block is obtained by halving the motion vector of the corresponding luminance block in each of the vertical direction and the horizontal direction.

FIG. 19 is a block diagram showing the structure of a decoding circuit 90 which is an embodiment of the decoder 31 shown in FIG.
The encoded image data transmitted through the transmission path (recording medium 3) is received by a receiving circuit (not shown), reproduced by a reproducing circuit, temporarily stored in the receiving buffer 81, and then decoded by the decoding circuit 90. Of the variable length decoding circuit 82. The variable length decoding circuit 82 performs variable length decoding on the data supplied from the reception buffer 81, the motion vector, the prediction mode, the prediction flag and the DCT flag to the motion compensation circuit 88, and the quantization step (scale) to the reverse. The decoded image data is output to the quantization circuit 83 and the decoded image data is output to the inverse quantization circuit 83. Furthermore, DC
The T flag and the prediction flag are output to the inverse quantization circuit 83.

The inverse quantization circuit 83 is used in the variable length decoding circuit 8
The image data supplied from No. 2 is inversely quantized according to the quantization step supplied from the variable length decoding circuit 82, and output to the IDCT circuit 84. The data (DCT coefficient) output from the inverse quantization circuit 83 is the IDCT circuit 8
In step 4, inverse DCT processing is performed to restore the original image data.

This image data is further input to the DCT block rearrangement circuit 86. The DCT block rearrangement circuit 86 corresponds to the DCT flag and the prediction flag,
This data is rearranged so that it has the same arrangement as the data output by the motion compensation circuit 88 to the arithmetic unit 87, and is output to the arithmetic unit 87.

When the image data supplied from the DCT block rearrangement circuit 86 is I picture data,
The data is output from the computing unit 86, and is supplied to the forward prediction image unit 87a of the frame memory 87 to generate predicted image data of image data (P picture or B picture data) that is input to the computing unit 86 later. Will be remembered. In addition, this data is the format conversion circuit 32.
(FIG. 14).

When the image data supplied from the IDCT circuit 84 is P picture data in which the image data one frame before is the predicted image data and is the data in the forward prediction mode, the forward prediction of the frame memory 87 is performed. The image data (I-picture data) one frame before stored in the image section 87a is read out, and the motion compensation circuit 8
At 8, the motion compensation corresponding to the motion vector output from the variable length decoding circuit 82 is performed. Then, in the arithmetic unit 86, the image data (difference data) supplied from the DCT block rearrangement circuit 86 is added and output. The added data, that is, the decoded P picture data is stored in the rear of the frame memory 87 to generate predictive image data of image data (B picture or P picture data) that is input later to the calculator 86. It is supplied to and stored in the predicted image section 87b.

Even in the case of P-picture data, the intra-picture prediction mode data is stored in the backward-prediction image section 87b as it is without any special processing by the computing unit 87, like the I-picture data.

Since this P picture is an image to be displayed next to the next B picture, it is not yet output to the format conversion circuit 32 at this point (as described above, the P input after the B picture is input). Pictures have been processed and transmitted before B pictures).

When the image data supplied from the DCT block rearrangement circuit 86 is B picture data,
Corresponding to the prediction mode supplied from the variable length decoding circuit 82, the image data of the I picture stored in the forward prediction image section 87a of the frame memory 87 (in the case of the forward prediction mode) and the backward prediction image section 87b. Stored P-picture image data (in backward prediction mode) or both image data (in bidirectional prediction mode)
Is read out, and the motion compensation circuit 88 performs motion compensation corresponding to the motion vector output from the variable length decoding circuit 82 to generate a predicted image. However, when motion compensation is not required (in the case of the intra-picture prediction mode), the predicted picture is not generated.

The data thus motion-compensated by the motion compensating circuit 88 is processed by the arithmetic unit 86 by the DCT.
It is added to the output of the block rearrangement circuit 86. This addition output is output to the format conversion circuit 32.

However, since this addition output is B picture data and is not used for generating a predicted image of another image, it is not stored in the frame memory 87.

After the B-picture image is output, the P-picture image data stored in the backward-predicted image section 87b is read out and sent to the format conversion circuit 32 via the motion compensation circuit 88 and the arithmetic unit 86. Supplied. However, at this time, motion compensation is not performed.

The decoder 31 includes a prediction mode switching circuit 52 and a DC in the encoder 18 of FIG.
Although the circuits corresponding to the T mode switching circuit 55 are not shown, the processing corresponding to these circuits, that is, the configuration in which the signals of the lines of the odd field and the even field are separated is necessary for the original mixed configuration. The process of returning according to
The motion compensation circuit 88 executes.

Further, although the processing of the luminance signal has been described above, the processing of the color difference signal is similarly performed. However, the motion vector used is one for the luminance signal, which is halved in the vertical and horizontal directions.

[0085]

When the post filter 22 is provided as in the decoding apparatus shown in FIG. 14, there are various kinds of filters in the post filter 22. Which kind of filter is optimum? Depends on the nature of the image quality and the conditions at the time of encoding.

For example, when the coding bit rate is low, the decoded image is significantly deteriorated, and therefore, in order to compensate for this, it is necessary to strongly apply a filter for improving the image quality. On the other hand, when the encoding bit rate is high, the decoded image maintains the high image quality as it is, and using the same filter as in the case of the low bit rate causes the problem that the image quality is deteriorated. is there.

Further, for example, considering only the case of a low bit rate, a fast moving image has poor coding efficiency and the image quality is significantly deteriorated. Therefore, it is necessary to strongly apply a filter for improving the image quality. However, if this is used for an image with high coding efficiency, there is a problem that the image quality deteriorates.

That is, in the conventional image signal processing apparatus for encoding / decoding image data, there is a problem that the image data cannot be optimally compressed / decompressed according to the characteristics of the image quality and the conditions at the time of encoding. .

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an image signal coding apparatus and an image signal decoding apparatus capable of optimally correcting a decoded image signal with a simple configuration. To aim.

[0090]

An image signal coding apparatus according to claim 1 is provided with an image signal coding apparatus including an encoder 18 as coding means for coding an image signal based on a predetermined predicted image signal. In the device, the encoder 18
When the image signal is encoded based on the predicted image signal, the encoding condition flag indicating the encoding condition of the image signal is encoded.

The image signal coding apparatus according to claim 1 is
The image flag is used as image information of the bit stream, the encoding flag is present in the user area of the image information of the bit stream, and the encoding flag is based on the encoding bit rate of the image information of the bit stream encoded by the encoder 18. A post filter selection circuit 140 can be provided as a flag setting means for setting

The image signal decoding apparatus according to claim 4 is an image signal decoding apparatus for decoding an encoded image signal obtained by encoding an image signal based on a predetermined predicted image signal, wherein the encoded image signal is the image signal. And a coding condition flag indicating a coding condition of the image signal, and a post filter 22 as an image correcting means for correcting the decoded image signal based on the coding condition flag.

[0093]

[Operation] In the image signal encoding device according to claim 1,
By encoding the encoding condition flag indicating the encoding condition of the image signal when the encoder 18 encodes the image signal based on the predicted image signal, the encoding is performed when the image signal is decoded with a simple configuration. It is possible to optimally correct the image signal based on the conversion condition flag.

Further, in the image signal coding apparatus according to the first aspect, the post filter selection circuit 140 uses the encoder 1
8 sets the coding flag based on the coding bit rate of the image information of the bit stream to be coded,
The image signal can be corrected more optimally.

In the image signal decoding apparatus according to the fourth aspect, the post filter 22 corrects the decoded image signal based on the coding condition flag indicating the coding condition of the image signal. , When decoding the image signal,
It is possible to optimally correct the image signal based on the coding condition flag.

[0096]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment shown in FIG. 1 has the same construction as the prior art, so only different constructions will be described.

The image data coding apparatus 1 and the image data decoding apparatus 2 of the first embodiment are the same as the conventional example and the encoder 1.
8, the configurations of the decoder 31 and the post filter 22 are different, and in this embodiment, as shown in FIG. 1, the encoder 18 of the encoding device 1 causes the encoder 18 of the encoding device 1 to simultaneously encode the bit stream which is image data and the encoding condition of the pre-filter 21. Indicating P
Encode ST flag and PST with bitstream
The flag is transmitted to the recording medium 3.

The bit stream and the PST flag coded and stored in the recording medium 3 are decoded by the decoder 31 of the decoding device 2, and the decoded bit stream is input to the format conversion circuit 32, and the block Format is converted to frame format. On the other hand, the decoded PST flag indicates that the post filter 22
The post filter 22 selects the optimum filter according to the PST flag.

The determination of the PST flag by the encoder 18 is performed by the following method in this embodiment.
That is, this is a method of forcibly inputting and setting the PST flag from the outside, and a method of determining the PST flag will be described.

FIG. 2 shows the configuration of the encoder 18 that implements this determination method. The input PST flag is input to the variable length coding circuit 58. Then, in the variable length coding circuit 58, the bit stream is variable length coded as in the conventional example, and the input PST flag is variable length coded.

The PST flag is stored in the storage medium 3 together with the bitstream as user data in the bitstream. MPEG, MPE
In G2 system, "user data" is sequence, GOP,
Since it can be set after the picture header, the PST flag can be similarly set for each sequence, GOP, and picture header.

Here, Tables 1 to 4 show the syntax of the MPEG video. "Extention and in Table 1
"extention data" or "user data" in "user data (i)"
Is recorded.

[0103]

[Table 1]

Table 2 shows "extention and user data" in Table 1.
(i) "indicates that when" user data start cord "is described here," user data "is described next.

[0105]

[Table 2]

Table 3 shows "user data". "user data"
Are recorded in 8-bit units. For example, "0000 0000 0
When "000 0000 0000 0001" occurs, it means that "user data" ends.

[0107]

[Table 3]

The PST flag is stored in "" user data "as an 8-bit flag, for example.The PST flag is shown in Table 4. Here, for example, filters 1, 2, ..., N are various types of post filter 22. Shows a filter.

[0109]

[Table 4]

Note that the PST flag is a sequence, GO
Since P and P can be set after the picture header, it is possible to use that value until the next reset, that is, the same filter is used until it is reset.

It is also possible to set the PST flag with a sequence flag. In this case, the resetting is performed by "user data" after the sequence, GOP and picture header.
It may be done in.

The bit stream stored in the storage medium 3 is decoded by the decoder 31. As shown in FIG. 3, the configuration of this decoder 31 is similar to that of the decoding circuit 90 shown in the conventional example of FIG. 19, and the bit stream is variable length decoded by the decoding circuit 90 via the reception buffer 81. When input to the circuit 82, the variable length decoding circuit 82
Then, the variable length code is solved. At this time, the PST flag recorded in "user data" is decoded and transmitted to the post filter 22 shown in FIG. Other decoder 31
The configuration and operation of are the same as those of the conventional example.

The post filter 22 uses, for example, the post filter 22 according to the PST flag thus decoded.
A median filter, a low-pass filter, or the like is selected as each type of filter. The median filter and the low-pass filter can be a filter group including a plurality of types of filters depending on parameters.

More specifically, as shown in FIG. 4, the post filter 22 uses the switches 101 and 102 to filter 100 (1) to 10 (10) based on the input PST flag.
0 (N) is selected, and the color difference signal C and the luminance signal Y stored in the frame memories 34 and 35 as a bit stream are selected.
Is output to the selected filter, and the signal processed by the selected filter is output to the D / A converters 36 and 37 via the switches 103 and 104.

Next, a median filter as an example of the filter of the post filter 22 will be described. The median filter is a filter that effectively removes block distortion and mosquito noise. As shown in FIG. 5, around a certain pixel stored in the field memory group 120,
For example, the 3 × 3 pixels are extracted by the 3 × 3 pixel extraction circuit 121, and rearranged by the rearrangement circuit 122 in the descending order. At this time, in the case of the central value, that is, in the case of 3 × 3 pixels, the fifth value is called a median.
An detector 123 detects D / A as the value of the pixel.
Output to the converters 36 and 37. A pixel value before filtering is used as the pixel value for obtaining the median.

In the calculation of the median, 3 × 3 pixels around a certain pixel are used, but the present invention is not limited to this, and the pixel group for which the median is calculated may be set in any manner. Then, the effect of the filter can be changed by changing the pixel group for which the median is obtained.

For example, when a median filter that takes a median of 3 × 3 pixels for all pixels is applied, block distortion and the like can be removed, but a strong filter that results in a blurred image as a whole (filter 1).

On the other hand, 3 × is applied only to the block edge.
When a median filter that takes a median of 3 pixels is applied, block distortion can be removed and a high frequency component can be maintained as compared with the filter 1 (filter 2).

Further, a one-dimensional median filter can be applied. In this case, compared with the filters 1 and 2, the efficiency of removing block distortion is lowered, but the high frequency component can be maintained to some extent (filter 3).

The filters 1, 2 and 3 are switched by the PST flag to select the optimum filter.

As described above, according to the image data encoding / decoding apparatus of the first embodiment, the optimum filter is selected by switching the switches 101 and 102 by the post filter 22 based on the input PST flag. be able to.

Next, the second embodiment will be described. The second embodiment is almost the same as the first embodiment, and the difference is that P
The setting method of the ST flag is that it is set based on various parameters generated at the time of encoding, and other configurations are the first.
Since it is the same as the embodiment, only different configurations will be described, the same configurations will be denoted by the same reference numerals, and description thereof will be omitted.

PS in the encoder 18 of the second embodiment
In the T flag determination method, as shown in FIG. 6, the post filter selection circuit 140 is responsive to various parameters input to the variable length encoder circuit 58 and the generated bit amount (encoding parameter) output from the bit counter. Determine the filter to be used for post-processing. Post filter selection circuit 1
The 40 also outputs a PST flag indicating the post filter to be used to the variable length coding circuit 58. The variable length coding circuit 58 performs variable length coding on the PST flag as in the first embodiment.

Next, an example of a method of determining the PST flag by the encoder 18 will be described. The case where the post filter 22 is particularly required is a case where the bit rate is low and the coding efficiency is low. In this case, block distortion, mosquito noise, and the like appear prominently, resulting in severe deterioration of the image. Post-processing is required to make such image deterioration unnoticeable. On the other hand, an image having a high coding efficiency, which has been encoded at a high bit rate, is still decoded and maintains high image quality, so excessive post-processing rather causes deterioration of image quality. .

Therefore, the lower the coding bit rate,
It is necessary to have a strong filter that removes block distortion and the like, and it is necessary to apply a stronger filter to a sequence with poor coding efficiency.

The coding parameters representing these are:
There are quantized coefficients. This quantized coefficient takes a smaller value as the coding bit rate increases, and takes a smaller value as the coding efficiency increases. That is, the PST flag may be adaptively switched according to the size of the quantized coefficient.

The quantizer scale code is
In the case of the MPEG system, it is set in macroblock units. Table 5 shows the macroblock syntax.

[0128]

[Table 5]

First, after encoding one frame, the average value MEAN_Q of the quantized coefficients in one frame is obtained. PS
As shown in Table 4, when the T flag has a larger value corresponding to a stronger filter, the larger the MEAN_Q, the larger the PST flag is assigned. MEAN_
The relationship between Q and the PST flag is as shown in FIG.
The relationship may be linear or stepwise as shown in FIG. 7B (FIG. 7B is a control method in which the post filter does not change frequently).

Note that the relationship between MEAN_Q and the PST flag is configured by using either one of FIGS. 7A and 7B, and it is assumed that the encoder side and the decoder side have the same relationship. .

Specifically, as shown in FIG. 8, in the post filter selection circuit 140, when the quantization scale (quantization coefficient) is input, the averaging circuit 150 calculates MEAN_Q for each frame. Then, the PST determination circuit 1
51 determines the PST flag based on MEAN_Q,
It is output to the variable length coding circuit 58. Other configurations and operations are the same as those in the first embodiment.

As a modification of the above-mentioned method using the quantized coefficient, there is a method using only the coding bit rate. In this case, the PST flag is set after the sequence header.

As described above, the second embodiment is the first
In addition to the effect of the embodiment, since the setting of the PST flag is performed based on various parameters generated at the time of encoding, the optimum PST flag can be set according to the content of encoding, and a more optimum filter can be selected. .

Next, a third embodiment will be described. The third embodiment is almost the same as the second embodiment, except that a post filter selection circuit 140 that selects a post filter is used.
Is provided on the decoding device side, and other configurations are the second
Since it is the same as the embodiment, only different configurations will be described, the same configurations will be denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 9, in the third embodiment, the second
In the embodiment, the post filter selection circuit 140 provided in the encoder 18 of the encoding device 1 is provided in the decoding device 2 and configured.

As shown in FIG. 10, the decoder 31 of the third embodiment has the same configuration as the decoding circuit 90 shown in the conventional example of FIG.
When input to the variable length decoding circuit 82 of the decoding circuit 90 via 1, the variable length decoding circuit 82 solves the variable length code. At this time, the quantized coefficient as the encoding parameter is decoded and transmitted to the post filter 22. Other configurations, operations and effects are the same as those of the second embodiment.

[0137]

As described above, according to the image processing method of the first aspect, when the image signal is encoded by the encoding means based on the predicted image signal, the encoding condition of the image signal is set. Since the coding condition flag shown is coded, the image signal can be optimally corrected based on the coding condition flag when decoding the image signal with a simple configuration.

In the image signal coding apparatus according to the first aspect, the coding flag is set by the flag setting means based on the coding bit rate of the image information of the bit stream coded by the coding means. There is an effect that the image signal can be corrected more optimally.

According to the image signal decoding apparatus of the fourth aspect, the image correcting means corrects the decoded image signal based on the coding condition flag indicating the coding condition of the image signal, With a simple configuration, when the image signal is decoded, the image signal can be optimally corrected based on the coding condition flag.

[Brief description of drawings]

FIG. 1 is a first image data encoding / decoding device according to the present invention.
It is a block diagram which shows the structure of an Example.

2 is a block diagram showing a configuration of an encoder 18 of FIG.

3 is a block diagram showing a configuration of a decoding circuit 90 as a decoder 31 of FIG.

FIG. 4 is a block diagram showing a configuration of a post filter 22 of FIG.

5 is a block diagram showing the configuration of a median filter as a filter example of the post filter 22 of FIG.

FIG. 6 is a block diagram showing a configuration of an encoder 18 according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram illustrating an operation of the post filter selection circuit 140 in FIG.

8 is a block diagram showing a configuration of a post filter selection circuit 140 of FIG.

FIG. 9 is a third image data encoding / decoding device of the present invention.
It is a block diagram which shows the structure of an Example.

10 is a block diagram showing a configuration of a decoding circuit 90 as the decoder 31 of FIG.

FIG. 11 is a diagram illustrating the principle of high efficiency encoding.

[Fig. 12] Fig. 12 is a diagram for describing the types of pictures in the case of compressing image data.

FIG. 13 is a diagram illustrating the principle of encoding a moving image signal.

[Fig. 14] Fig. 14 is a block diagram illustrating a configuration example of an image signal encoding device and a decoding device.

15 is a diagram illustrating a format conversion operation of the format conversion circuit 17 in FIG.

16 is a block diagram showing a configuration example of an encoder 18 in FIG.

17 is a diagram for explaining the operation of the prediction mode switching circuit 52 in FIG.

18 is a diagram illustrating the operation of the DCT mode switching circuit 55 in FIG.

19 is a block diagram showing a configuration example of a decoding circuit 90 which is an example of the decoder 31 of FIG.

[Explanation of symbols]

 1 Encoding Device 2 Decoding Device 3 Recording Medium 12, 13 A / D Converter 14 Frame Memory 15 Luminance Signal Frame Memory 16 Color Difference Signal Frame Memory 17 Format Conversion Circuit 18 Encoder 21 Prefilter 22 Post Filter 31 Decoder 32 Format Conversion Circuit 33 frame memory 34 luminance signal frame memory 35 color difference signal frame memory 36, 37 D / A converter 49 picture determination circuit 50 motion vector detection circuit 51 frame memory 52 prediction mode switching circuit 53 arithmetic unit 54 prediction determination circuit 55 DCT mode switching circuit 56 DCT circuit 57 Quantization circuit 58 Variable length coding circuit 59 Transmission buffer 60 Inverse quantization circuit 61 IDCT circuit 63 Operator 64 Frame memory 65 Motion compensation circuit 81 Reception buffer 82 variable length decoding circuit 83 inverse quantization circuit 84 IDCT circuit 86 arithmetic unit 87 frame memory 88 motion compensation circuit 100 (1) to 100 (N) filter 1 to filter N 101, 102 switch 121 3 × 3 pixel extraction circuit 122 Rearrangement circuit 123 Median detection circuit 140 Post filter detection circuit 150 Averaging circuit 151 PST determination circuit

Claims (8)

[Claims] 1. An image signal coding apparatus comprising a coding means for coding an image signal on the basis of a predetermined predicted image signal, wherein the coding means codes the image signal on the basis of the predicted image signal. An image signal coding apparatus, wherein a coding condition flag indicating a coding condition of the image signal is coded at the time of coding. 2. The image signal is image information of a bitstream, and the encoding flag is present in a user area of the image information of the bitstream.
The image signal encoding device according to. 3. Based on a coding bit rate of the image information of the bit stream coded by the coding means,
The image signal encoding apparatus according to claim 2, further comprising flag setting means for setting the encoding flag. 4. An image signal decoding apparatus for decoding an encoded image signal, which is an image signal encoded based on a predetermined predicted image signal, wherein the encoded image signal is the image signal and the encoding of the image signal. An image signal decoding apparatus comprising: an encoding condition flag indicating a condition, the image signal decoding device comprising an image correction unit that corrects the decoded image signal based on the encoding condition flag. 5. The image signal decoding apparatus according to claim 4, wherein the image signal is image information of a bit stream, and the encoding flag exists in a user area of the image information. . 6. The image signal decoding apparatus according to claim 5, wherein the encoding flag is set based on an encoding bit rate of the image information of the encoded bit stream. 7. The image correction means comprises a plurality of filters, and selects the plurality of filters based on the flag to correct the image signal. The image signal decoding device according to item 1. 8. The image signal decoding apparatus according to claim 4, wherein the filter is a median filter.