JPH07210496A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To efficiently transfer a large amount of data even when a window area in a bus space is small. CONSTITUTION:A DMA controller 1 increases the address of a transfer destination by each transfer cycle and outputs it to the low order part of an address bus. In a register 2, the last value of a transfer destination address signal to be outputted from the DMA controller 1 is set in advance and a comparator 3 compares the transfer destination address signal outputted from the DMA controller 1 and the last address value set in the register 2 so as to output a coincident signal when they are coincident. A counter 4 counts the coincident signal and outputs the obtained coincident signal to the high order part of the address bus as the transfer destination address signal. At the same time, the low order part of the address bus is reset to be an initial value by the auto-initializing function of the DMA controller 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device using a DMA controller.

[0002]

2. Description of the Related Art Conventionally, data transfer using a DMA controller is performed as shown in FIGS. That is, as shown in FIG.
Address data B via the bus space
Write to At this time, the write destination of the address space B is set in the map register, and specifically, the upper 8 bits A16 to A23 of the address signals A0 to A23 for specifying the address are set by the map register. Here, the remaining lower 16 bits A0 to A15 are
This corresponds to the amount of data in the window area on the bus space sent in one transfer cycle. Further, the value of the map register is reset by the CPU every transfer cycle, so that the data is transferred to a different position on the address space B.

[0003]

However, if the window area on the bus space is not sufficiently large as compared with the size of the address spaces A and B, as in the example of FIG. When an attempt is made to transfer, the transfer must be repeated many times, and the DMA transfer must be interrupted to reset the map register. That is, D
When the MA transfer is started, as shown in FIG. 9, an internal bus acquisition cycle for acquiring the internal bus from the CPU is required. Further, when the bus space is used by a plurality of CPUs, the bus space for this bus space is required. A bus acquisition cycle is also required.

For example, No. 1 to No. 2 of the address space A
Areas up to 55 are No. 1 to No. 255 of address space B
When DMA transfer is performed to the areas up to, the map register setting cycle for interrupting the DMA transfer accompanying the map register setting becomes 254 times. As described above, when the window area on the bus space is small, there is a problem in that the time required for processing other than data transfer increases and it is inefficient. The present invention has been made to solve the above problems, and an object of the present invention is to enable a large amount of data to be efficiently transferred even when the window area on the bus space is small. To provide a transfer device.

[0005]

In order to achieve the above object, a first invention is a DMA controller having an auto-initialize function, which increments a transfer destination address for each transfer cycle and outputs the incremented address to a lower part of an address bus. , If the register in which the final value of the transfer destination address signal output from the DMA controller is preset and the transfer destination address signal output from the DMA controller are compared with the final address value set in the register and they match, It is characterized by comprising a comparator which outputs a coincidence signal and a counter which outputs a count value obtained by counting the coincidence signal as a transfer destination address signal to an upper portion of the address bus.

According to a second aspect of the present invention, a DMA controller having an auto-initialize function which increments a transfer destination address for each transfer cycle and outputs the incremented transfer destination address to a lower portion of an address bus, and a final value of a transfer destination address signal output from the DMA controller are provided. Is set in advance and D
A comparator that compares the transfer destination address signal output from the MA controller with the final address value set in the register and outputs a coincidence signal when they match, and a FIFO in which a plurality of transfer destination addresses are stored in advance in the transfer order.
(First In First Out) The buffer, the delay line connected to the output side of the comparator, the output of the delay line as the input clock, the output of the FIFO buffer as the input signal, and the output value as the transfer destination address signal. And a flip-flop for outputting to the unit.

According to a third aspect of the present invention, a DMA controller having an auto-initialize function that increments a transfer destination address for each transfer cycle and outputs the incremented address to a lower part of an address bus, and counts clocks input to the DMA controller, The clock counter that outputs a count-up signal when the number of clocks corresponding to the final value of the transfer destination address signal output from the clock counter and the count-up signal of the clock counter are counted and the count value is used as the transfer destination address signal of the address bus. It is characterized in that it is provided with a counter for outputting to an upper part.

[0008]

According to the first aspect of the invention, the transfer destination address is incremented by the DMA controller for each transfer cycle and is output to the lower part of the address bus. Also,
The final value of the transfer destination address signal output from the DMA controller is preset in the register, and the transfer destination address signal output from the DMA controller and the final address value set in the register are compared by the comparator, and they match. In that case, a match signal is output. Further, the coincidence signal is counted by the counter, and the obtained count value is output to the upper portion of the address bus as the transfer destination address signal. At the same time, the initial value is reset in the lower part of the address bus by the auto-initialize function of the DMA controller. As a result, even if the window area in the bus space is narrow, it is possible to continuously transfer the data larger than the window area.

In the second invention, the transfer destination address is incremented by the DMA controller for each transfer cycle and output to the lower part of the address bus. The final value of the transfer destination address signal output from the DMA controller is preset in the register, and the transfer destination address signal output from the DMA controller is compared with the final address value set in the register by the comparator. When they match, a match signal is output.

Further, the output signal of the comparator is input as a clock of the flip-flop via the delay line, and the output of the FIFO buffer in which a plurality of transfer destination addresses are stored in advance in the transfer order is input to the flip-flop. The output value of the flip-flop is output to the upper portion of the address bus as a transfer destination address signal. At the same time, the initial value is reset in the lower part of the address bus by the auto-initialize function of the DMA controller. As a result, even if the window area in the bus space is narrow, it is possible to continuously transfer the data larger than the window area.

In the third invention, the DMA controller increments the transfer destination address for each transfer cycle and outputs it to the lower part of the address bus. The clock input to the DMA controller is counted by the clock counter. When the count value counts the number of clocks corresponding to the final value of the transfer destination address signal output from the DMA controller, a count-up signal is output. Further, the count-up signal output from the clock counter is counted, and the count value is output to the upper part of the address bus as the transfer destination address signal. At the same time, the initial value is reset in the lower part of the address bus by the auto-initialize function of the DMA controller. As a result, even if the window area in the bus space is narrow, it is possible to continuously transfer the data larger than the window area.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment according to the first invention, and FIG. 2 is a timing chart showing its operation. In FIG. 1, 1 is a DMA controller (DM
AC), 2 is a register, 3 is a comparator, and 4 is a counter that functions as a map register. Here, FIG.
Similarly, the transfer procedure will be described assuming that the DMA transfer is performed from the address space A to the address space B through the window.

(1) 0000h is set in the register 2 as a lower address of the end address of the transfer destination window. (2) The upper address (A
16 to A23) are set and a load clock is given. (3) The transfer source start address (A0000h) and the number of transfers (arbitrary) are set in the DMA controller 1. (4) Set the transfer destination start address (C00000h) and the number of transfers (8000h) in the DMA controller 1 to enable the auto-initialize function. The transfer is in 16-bit units.

(5) Start DMA transfer. (6) The DMA controller 1 has a lower address (A0-A
Data is transferred while incrementing 15). (7) When the lower address reaches 0000h, the EQ terminal of the comparator 3 becomes active, the counter 4 is incremented (or decremented), and the map register value is updated. At the same time, the transfer destination start address and the transfer count are automatically reset by the auto-initialize function of the DMA controller 1. That is, the initial setting value is reset.

After (8), the operations of (6) and (7) are repeated. (9) When the transfer count of the transfer source reaches the set value, the DMA transfer is completed. Note that FIG. 2 shows the lower address (A0
~ A15) reaches the maximum value, and then the value of the upper address (A16 to A23) is incremented. * RD and * WT in the figure represent read / input to the DMA controller 1. It is a write signal.

FIG. 3 is a block diagram showing the configuration of the second embodiment according to the second invention, and FIG. 4 is a timing chart showing the operation thereof. In FIG. 3, 1 is a DMA controller, 2 is a register, 3 is a comparator, 5 is a FIFO buffer, 6 is a delay line, and 7 is a flip-flop functioning as a map register. Here, the transfer procedure will be described on the assumption that the DMA transfer is performed from the address space A to the address space B through the window as in FIG.

(1) 0000h is set in the register 2 as a lower address of the end address of the transfer destination window. (2) The upper address (A16 to A23) is set in the order of transfer from the data bus to the FIFO buffer 5, that is, the map register value of the transfer destination is set. (3) The transfer source start address (A0000h) and the number of transfers (arbitrary) are set in the DMA controller 1.

(4) The transfer destination start address (C00000h) and the transfer count (8000
Set h) to enable the auto-initialize function. The transfer is in 16-bit units. (5) The clock CLKA is input to the FIFO buffer 5 and the delay line 6, the data in the FIFO buffer 5 is latched by the flip-flop 7, and DMA transfer is started.

(6) The DMA controller 1 transfers data while incrementing the lower address (A0 to A15). (7) When the lower address reaches 0000h, the EQ terminal of the comparator 3 becomes active, and at the same time, the flip-flop 7 latches the data from the FIFO buffer 5 and updates the map register value. At the same time, the transfer destination start address and the transfer count are automatically reset by the auto-initialize function of the DMA controller 1. (8) After that, the operations of (6) and (7) are repeated. (9) When the transfer count of the transfer source reaches the set value, the DMA transfer is completed.

Note that FIG. 4 shows the progress when the value of the lower address (A0 to A15) reaches the maximum value and the value of the upper address (A16 to A23) is incremented by these operations. * RD and * WT are DM
This is a read / write signal input to the A controller 1. In addition, as shown in FIG. 4, the delay line 6
CLKA is delayed with respect to the FIFO output by providing. That is, the delay line 6 includes the flip-flop 7
It is provided to satisfy the setup and hold times of. In this embodiment, since the transfer is started in the transfer order preset in the FIFO buffer 5, it is possible to set the map register value in the discontinuous area.

FIG. 5 is a block diagram showing the configuration of the third embodiment according to the third invention, and FIG. 6 is a timing chart showing the operation thereof. In FIG. 5, 1 is a DMA controller, 8 is a counter, and 9 is a counter that functions as a map register. Here, as in FIG. 8, the address space A
The transfer procedure will be described assuming that the DMA transfer is performed from the address space B to the address space B through the window.

(1) The map register value of the transfer destination is set in the counter 9 from the data bus. (2) The transfer source start address (A0000h) and the number of transfers (arbitrary) are set in the DMA controller 1. (3) The transfer start address (C00000h) and the number of transfers (00FFh) are set in the DMA controller 1 to enable the auto-initialize function. (4) Start DMA transfer. (5) The DMA controller 1 uses the lower address (A0-A
Data is transferred while incrementing 15).

(6) Here, assuming that it takes FFh times to transfer one ROW address, the RC of the counter 8
The counter 9 is updated when the O output becomes active, and the upper address (A16 to
A23) is updated. (7) At the same time, the transfer destination start address and the transfer count are automatically reset by the auto-initialize function of the DMA controller 1. (8) After that, the operations of (6) and (7) are repeated. (9) When the transfer count of the transfer source reaches the set value, the DMA transfer is completed.

Note that FIG. 6 shows the progress when the value of the lower address (A0 to A15) reaches the maximum value and the value of the upper address (A16 to A23) is incremented by these operations. * RD and * WT are DM
Read / write signal input to the A controller 1, *
RAS (ROW ADDRESS STROBE) is a clock input to the counter 8. This example
When the counter 8 counts * RAS, DM
The clock is counted at the same timing as the count of the address counter in the A controller 1. Therefore, this embodiment is effective when data is transferred in units of RAS using DRAM (dynamic memory).

Thus, each of these embodiments is shown in FIG.
In the case of transferring Nos. 1, 2, 3 ... Of the address space A, the DMA transfer is not interrupted due to the resetting of the map register as shown in FIG. 7, and the data transfer can be continued continuously. It will be possible. It should be noted that each of the embodiments assumes memory-memory transfer by the DMA controller, but is also applicable to I / O-memory transfer.

[0026]

As described above, according to the first invention,
When the lower transfer destination address output from the DMA controller reaches the final value, the address signal to the upper address bus is incremented, so that the DMA transfer is not interrupted. As a result, even if the window area in the bus space is narrow, it is possible to continuously transfer data in the window area or more, and the efficiency of data transfer is improved.

According to the second aspect of the invention, when the lower transfer destination address output from the DMA controller reaches the final value, the next preset address signal is output to the upper address bus, so that the DMA is generated. Transfers are uninterrupted. As a result, even if the window area in the bus space is narrow, it is possible to continuously transfer data in the window area or more, and the efficiency of data transfer is improved. Further, particularly in the present invention, it becomes possible to transfer data to the transfer destinations of discontinuous addresses.

According to the third invention, the fact that the lower transfer destination address output from the DMA controller has reached the final value is counted by another counter, and the address signal to the upper address bus is incremented. As a result, the DMA transfer is not interrupted and the data transfer is continuously performed. As a result, even if the window area in the bus space is narrow, it is possible to continuously transfer data in the window area or more, and the efficiency of data transfer is improved. In particular, the present invention can be applied when a DRAM is used as the memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment according to the first invention.

FIG. 2 is a timing diagram illustrating the operation of the embodiment of FIG.

FIG. 3 is a block diagram showing a configuration of a second embodiment according to the second invention.

FIG. 4 is a timing diagram illustrating the operation of the embodiment of FIG.

FIG. 5 is a block diagram showing a configuration of a third embodiment according to the third invention.

FIG. 6 is a timing diagram illustrating the operation of the embodiment of FIG.

FIG. 7 is an explanatory diagram of a transfer cycle according to each embodiment.

FIG. 8 is an explanatory diagram showing a conventional DMA transfer.

FIG. 9 is an explanatory diagram showing a transfer cycle of a conventional DMA transfer.

[Explanation of symbols]

 1 DMA controller 2 register 3 comparator 4 counter 5 FIFO buffer 6 delay line 7 flip-flop 8, 9 counter

Claims (3)

[Claims] 1. A DMA controller having an auto-initialize function, which increments a transfer destination address for each transfer cycle and outputs the same to a lower part of an address bus, and a final value of a transfer destination address signal output from the DMA controller is preset. The register, the transfer destination address signal output from the DMA controller and the final address value set in the register are compared and a match signal is output when they match, and the count value obtained by counting the match signal A data transfer device comprising: a counter that outputs a transfer destination address signal to a higher-order part of an address bus. 2. A DMA controller having an auto-initialize function, which increments a transfer destination address for each transfer cycle and outputs it to the lower part of the address bus, and a final value of a transfer destination address signal output from the DMA controller is preset. Register, a comparator that outputs the match signal when the transfer destination address signal output from the DMA controller and the final address value set in the register are compared, and a match signal is stored in advance. FIF
The O buffer, the delay line connected to the output side of the comparator, and the flip line that uses the output of the delay line as the input clock and the output of the FIFO buffer as the input signal and outputs the output value as the transfer destination address signal to the upper part of the address bus. A data transfer device including: a flop. 3. A DMA controller having an auto-initialize function, which increments a transfer destination address for each transfer cycle and outputs the same to a lower part of an address bus, and counts clocks input to the DMA controller and outputs them from the DMA controller. A clock counter that outputs a count-up signal when the number of clocks corresponding to the final value of the transfer destination address signal is counted, and a count-up signal of the clock counter is counted and the count value is output to the upper part of the address bus as the transfer destination address signal. A data transfer device, comprising: