JPH06349267A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] To enable accurate data to be read from a memory cell even if the layout area of the DRAM is reduced or the storage capacity is increased. [Structure] A relatively long pair of main bit lines BLm and / BLm, and a plurality of pairs of sub bit lines BLs and / BLm.
BLs are arranged and their sub-bit lines BLs or / B
Ls is connected to the main bit line BLm or / BLm by a transfer gate T or / T. The parasitic capacitance per unit length of the main bit line pair BLm, / BLm is set to 1/4 or less than that of the sub bit line pair.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (hereinafter referred to as "DRAM") having a hierarchical bit line structure.
Said).

[0002]

2. Description of the Related Art FIG. 17 is a block diagram showing the overall structure of a conventional DRAM. Such a DRAM is disclosed in, for example, “IEEE Journal of Solid-State Circuits, vol.27,
No. 7, p. 1020 ”. With reference to FIG. 17, this DRAM includes blocks B1 to B32, sense amplifier columns S1 to S34, and a row decoder RD.
And a column decoder CD.

FIG. 18 is a wiring diagram showing a part of the DRAM shown in FIG. 17 in more detail. Referring to FIG. 18, each of the blocks B1 to B32 includes 1024 pairs of bit lines BL and / BL arranged in the row direction and 256 word lines WL arranged in the column direction. And a memory cell MC arranged at or near the intersection of the word line and one bit line BL or / BL.

Each sense amplifier row S1 to S34 includes a plurality of sense amplifiers SA. Each sense amplifier SA includes two N-channel MOS transistors cross-coupled between the bit line pair BL, / BL and two P-channel MOS transistors similarly cross-coupled.

In this DRAM, a shared sense amplifier system is adopted. That is, one sense amplifier SA includes blocks B1 to B32 on both sides adjacent to each other.
Are connected to each other through the pair of bit line pairs BL and / BL and the pair of N channel MOS transistor pairs Tb and / Tb. These transistor pairs Tb, / T
The block selection line SS is connected to the gate electrode of b. For example, in FIG. 17, when the left block B1 is selected, the left block selection line SS2 in the right block B2 is lowered to the L level. On the other hand, when the right block B2 is selected, the right block selection line SS1 in the left block B1 is lowered to the L level.

In this DRAM, sense amplifiers SA are alternately arranged on both sides of blocks B1 to B32. Therefore, the pitch of the sense amplifier SA is twice the pitch of the bit line pair BL, / BL.

Further, each sense amplifier row S1 to S34 further includes an equalize circuit 10 and a precharge circuit 12.
And an input / output circuit 14. The equalizer circuit 10 includes an N-channel MOS transistor Te and short-circuits the bit line pair BL, / BL to make the potentials of the bit line pair BL, / BL equal, that is, Vcc / 2. The precharge circuit 12 includes N-channel MOS transistors Tp and / Tp, and connects the bit line pair BL, / BL to the intermediate potential V.
Precharge to cc / 2. The input / output circuit 14 includes N-channel MOS transistors Ti and / Ti, outputs the potential generated on the bit line pair BL, / BL to the outside via the input / output line pair IO, / IO, and from the outside. The potential input via the I / O line pair IO, / IO is supplied to the bit line pair BL, / BL. The gate electrodes of these transistors Ti and / Ti are connected to the column selection line CS.
It is connected to the. The column select line CS is selectively raised to the H level by the column decoder CD.

FIG. 19 shows a memory cell M shown in FIG.
It is a wiring diagram which shows C and its periphery in more detail.

Referring to FIG. 19, memory cell MC includes a transfer gate TG having a source electrode connected to one bit line BL of the bit lines and a gate electrode connected to word line WL, and a transfer gate. The memory cell capacitor Cs has one electrode connected to the drain electrode of the TG, and the other electrode is applied with a predetermined potential, usually Vcc / 2. That is, the memory cell MC is
A transfer gate controlled by the word line WL and a memory cell capacitor Cs for storing data are provided.

Each bit line BL, / BL has a parasitic capacitance Cb.
Have. The parasitic capacitance Cb is one bit line BL, / B
It is almost proportional to the number of memory cells MC connected to L. The length of the bit lines BL, / BL is the memory cell M
This is because the larger the number of C, the longer it needs to be.

Next, the read operation of this DRAM will be briefly described. The storage node potential of the memory cell capacitor Cs, that is, the potential of one electrode on the side connected to the drain electrode of the transfer gate TG is the power supply potential Vcc.
Alternatively, the memory cell MC stores 1-bit data by being set to the ground potential GND.

At the time of reading, bit line pair BL and / BL is previously set to intermediate potential Vcc / 2 by equalize transistor Te and precharge transistor Tp, and equalize line EQ is lowered to L level and then word When the line WL is raised to the H level, the transfer gate TG of the memory cell MC becomes conductive, and the data stored in the memory cell capacitor Cs is read out to the bit line BL via the transfer gate TG.

As described above, when the data in memory cell MC is read onto one bit line BL, a potential difference | ΔV | expressed by the following equation is generated between bit lines BL and / BL.

| ΔV | = (Vcc / 2) / (Cb / Cs + 1) Here, Cb represents the parasitic capacitance of one bit line, and Cs represents the capacitance of the memory cell capacitor.

This potential difference | ΔV |
However, if this potential difference | ΔV | is too small, the sense amplifier SA cannot sufficiently amplify this potential difference | ΔV |.

For example, D having a storage capacity of 16 Mbits
In the RAM, the value of Cb / Cs is about “10”, and thus the potential difference | ΔV | is as small as 150 mV when the power supply potential Vcc is 3.3V. Therefore, in order for the DRAM to operate stably, the parasitic capacitance C
The value of b should be as small as possible.

[0017]

For the above reason, the conventional DRAM is composed of 32 blocks B1 to B32 as shown in FIG. That is, if the length of the bit line pair BL, / BL is made longer,
The number of sense amplifier rows can be less than 34. However, if the length of the bit line pair BL, / BL is made longer, the value of the parasitic capacitance Cb becomes larger.
Therefore, in the conventional DRAM, although the number of sense amplifier rows is large, the bit line pair BL, / BL
Was so short that a sufficient potential difference | ΔV | was obtained.

Therefore, the storage capacity is from 1 Mbit to 4
One bit line BL or / BL even if it increases with each generation, M bit, 16 Mbit, 64 Mbit
The number of memory cells MC connected to is fixed to 128, with some exceptions.

On the other hand, although the memory cell MC is being miniaturized due to three-dimensionalization or the like, the sense amplifier rows S1 to S3 are formed.
The size of 4 is not much smaller than that of the memory cell MC. Therefore, as the storage capacity increases, the ratio of the sense amplifier rows S1 to S34 in the entire chip increases. This hinders the realization of 256 Mbit and even 1 Gbit DRAM.

Further, as the storage capacity increases and the miniaturization progresses, there is a problem that the probability of occurrence of defects, dust, etc. increases and the yield decreases. As a countermeasure, spare memory cells are redundantly arranged in the DRAM. A DRAM is manufactured, and if the manufactured DRAM contains defective memory cells, the defective memory cells are replaced with spare memory cells.

For example, when some spare memory cells are redundantly provided together with some spare word lines, if the normal word line is broken or short-circuited, the normal memory selected by the word line is selected. If no data can be read from the cell, the regular word line is replaced with the spare word line. That is, when an address for selecting the regular word line is given,
The spare word line thus replaced is programmed by a fuse circuit or the like so as to rise to the H level.

In the DRAM, when word line WL is raised to H level and data is read onto bit line pair BL, / BL, sense amplifier SA is activated to amplify the read data. At this time, the memory cell M
Since the data in C is destroyed, the amplified data is written back to the memory cell MC.

Therefore, if the regular word line WL in the block B1 is defective, the spare word line provided in the same block B1 is replaced with the regular word line WL. In order to replace the regular word line WL in the block B1 with the spare word line provided in the different blocks B2 to B32, the different block B2 must be replaced.
The sense amplifier SA in ~ B32 must be activated. Therefore, when a regular word line in one block becomes defective, it is very complicated to control that word line to replace a spare word line in another block.

Normally, for example, 256 regular word lines and two spare word lines are provided in one block. The defective word line is then replaced with the spare word line in the same block. For example, in the case of 2 blocks, a total of 4 spare word lines are provided.
In this case, if three regular word lines in one block become defective, there is a problem that the DRAM cannot be relieved even though four spare word lines are provided. It was

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor memory device having a smaller size.

Another object of the present invention is to provide a semiconductor memory device having a larger storage capacity.

Still another object of the present invention is to provide a semiconductor memory device having a small size and capable of accurately reading data.

Still another object of the present invention is to provide a semiconductor memory device having a large memory capacity and capable of accurately reading data.

Still another object of the present invention is to provide a semiconductor memory device having a small size and a sufficient operation speed.

Still another object of the present invention is to provide a semiconductor memory device having a large storage capacity and a sufficient operating speed.

Still another object of the present invention is to provide a semiconductor memory device which can be manufactured with a high yield.

Still another object of the present invention is to provide a semiconductor memory device which can be manufactured with a high yield and which has a simple control circuit.

Still another object of the present invention is to provide a semiconductor memory device that can be quickly tested.

[0034]

A semiconductor memory device according to claim 1, wherein a main memory cell block, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, And a plurality of sense amplifier means. The main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are arranged in a plurality of rows corresponding to each of the plurality of sub memory cell blocks, and each of the plurality of sub bit line pairs is arranged in a plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. Connected. The plurality of main bit line pairs are arranged in a plurality of rows, and each has a parasitic capacitance per unit length that is ¼ or less of the parasitic capacitance per unit length of the sub bit line pair. It is provided corresponding to the sub bit line pair, and each responds to the selection signal to bring the corresponding sub bit line pair and the main bit line pair of the row in which the sub bit line pair is located into a conductive state. The plurality of sense amplifier means are provided corresponding to the plurality of main bit line pairs, and each amplifies the potential difference appearing between the main bit lines of the corresponding main bit line pair.

A semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect, wherein each switching means pair is arranged on one end side of a corresponding sub-bit line pair. The switching means and the second switching means disposed on the other end side of the corresponding sub bit line pair are provided, and the first or second switching is performed on the adjacent sub bit line pair of the adjacent sub memory cell block. One of the switching means of the means is arranged adjacently.

According to another aspect of the semiconductor memory device of the present invention, a main memory cell block, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, and a plurality of sense amplifier means. Equipped with. The main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are arranged in a plurality of rows corresponding to each of the plurality of sub memory cell blocks, and each of the plurality of sub bit line pairs is arranged in a plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. Connected. The plurality of main bit line pairs are arranged in a plurality of rows, and each has a parasitic capacitance per unit length that is ¼ or less of the parasitic capacitance per unit length of the sub bit line pair. The plurality of switching means pairs are provided corresponding to the sub-bit line pairs, and each responds to the selection signal with the corresponding sub-bit line pair and the main bit line pair of the row in which the sub-bit line pair is located. Is made conductive. The plurality of sense amplifier means are
It is provided corresponding to a plurality of main bit line pairs, each of which is
The potential difference appearing between the main bit lines of the corresponding main bit line pair is amplified. Each switching means pair has a first switching means arranged on one end side of the corresponding sub-bit line pair and a second switching means arranged on the other end side of the corresponding sub-bit line pair. Together with the first sub-bit line pair of the adjacent sub-memory cell blocks.
Alternatively, one of the second switching means is arranged adjacent to the other switching means.

A semiconductor memory device according to a fourth aspect is the semiconductor memory device according to the second or third aspect,
The first and second switching means of each switching means pair are connected between the sub-bit line of the corresponding sub-bit line pair and the main bit line of the main bit line pair of the row in which the sub-bit line pair is located. , A MOS transistor which receives a selection signal at its gate electrode, and which is arranged adjacent to an adjacent sub-bit line pair of an adjacent sub-memory cell block.
One of the source / drain electrodes connected to the main bit line of the S transistor is commonly formed.

According to another aspect of the semiconductor memory device of the present invention, a main memory cell block, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, and a plurality of sense amplifier means. Equipped with. The main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are arranged in a plurality of rows corresponding to each of the plurality of sub memory cell blocks, and each of the plurality of sub bit line pairs is arranged in a plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. Connected. The plurality of main bit line pairs are arranged in a plurality of rows. A plurality of switching means pairs are provided corresponding to the sub-bit line pairs, each of which responds to a selection signal,
The corresponding sub bit line pair and the main bit line pair of the row in which the sub bit line pair is located are brought into conduction. The plurality of sense amplifier means are provided corresponding to the plurality of main bit line pairs, and each amplifies the potential difference appearing between the main bit lines of the corresponding main bit line pair. Each switching means pair is arranged adjacent to a switching means pair for an adjacent sub bit line pair of an adjacent sub memory cell block, has two MOS transistors receiving a selection signal at their gate electrodes, and has an adjacent sub memory. One of the source / drain electrodes connected to the main bit line of the MOS transistor arranged adjacent to the adjacent sub bit line pair of the cell block is formed in common.

According to another aspect of the semiconductor memory device of the present invention, a plurality of main memory cell blocks, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, and a plurality of senses. Equipped with amplifier means. Each main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are arranged in a plurality of rows corresponding to each of the plurality of sub memory cell blocks, and each of the plurality of sub bit line pairs is arranged in a plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. Connected. The plurality of main bit line pairs are arranged in a plurality of rows. The plurality of switching means pairs are provided corresponding to the sub-bit line pairs, and each responds to the selection signal with the corresponding sub-bit line pair and the main bit line pair of the row in which the sub-bit line pair is located. Is made conductive. The plurality of sense amplifier means are provided corresponding to the plurality of main bit line pairs, and each amplifies the potential difference appearing between the main bit lines of the corresponding main bit line pair. Corresponding two main bit line pairs of the plurality of main bit line pairs are arranged on both sides of one corresponding sense amplifier means of the plurality of sense amplifier means. The semiconductor memory device further includes a plurality of first memory devices.
Of transistor pairs and a plurality of second transistor pairs. The plurality of first transistor pairs are provided corresponding to the plurality of sense amplifier means, and each of them connects one of the two main bit line pairs to one sense amplifier means in response to the first block selection signal. To do. The plurality of second transistor pairs are provided corresponding to the plurality of sense amplifier means, and each of the plurality of second transistor pairs is complementary to one corresponding first transistor pair in response to the second block selection signal. The other of the two main bit line pairs is connected to one sense amplifier means.

According to another aspect of the semiconductor memory device of the present invention, a main memory cell block, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, and a plurality of sense amplifier means. Equipped with. The main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are arranged in a plurality of rows corresponding to each of the plurality of sub memory cell blocks, and each of the plurality of sub bit line pairs is arranged in a plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. Connected. The plurality of main bit line pairs are arranged in a plurality of rows. A plurality of switching means pairs are provided corresponding to the sub-bit line pairs, each of which responds to a selection signal,
The corresponding sub bit line pair and the main bit line pair of the row in which the sub bit line pair is located are brought into conduction. The plurality of sense amplifier means are provided corresponding to the plurality of main bit line pairs, and each amplifies the potential difference appearing between the main bit lines of the corresponding main bit line pair. Half of the plurality of sense amplifier means form a first group, the other half form a second group, and the sense amplifier means of the first group are arranged every two rows and every two columns. The group of sense amplifier means is arranged every two rows and every two columns on the rows and columns other than the rows and columns where the first group of sense amplifier means is arranged.

According to another aspect of the semiconductor memory device of the present invention, a main memory cell block, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, and a plurality of sense amplifier means. Equipped with. The main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are arranged in a plurality of rows corresponding to each of the plurality of sub memory cell blocks, and each of the plurality of sub bit line pairs is arranged in a plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. Connected. The plurality of main bit line pairs are arranged in a plurality of rows. A plurality of switching means pairs are provided corresponding to the sub-bit line pairs, each of which responds to a selection signal,
The corresponding sub bit line pair and the main bit line pair of the row in which the sub bit line pair is located are brought into conduction. The plurality of sense amplifier means are provided corresponding to the plurality of main bit line pairs, and each amplifies the potential difference appearing between the main bit lines of the corresponding main bit line pair. The main memory cell block further has a spare memory cell block having a plurality of spare memory cells arranged in a plurality of rows and a plurality of columns. The semiconductor memory device further includes a plurality of spare word lines, a plurality of spare sub-bit line pairs, and a plurality of spare switching means pairs. The plurality of spare word lines are arranged in a plurality of columns, and each is connected to a plurality of spare memory cells arranged in a corresponding column. The plurality of spare sub-bit line pairs are arranged in a plurality of rows corresponding to the spare memory cell blocks, and each is connected to a plurality of spare memory cells arranged in the corresponding row. The plurality of spare switching means pairs are provided corresponding to the spare sub-bit line pairs, and each of them corresponds to the spare sub-bit line pair and the corresponding spare sub-bit line pair and the row in which the spare sub-bit line pair is located. The main bit line pair is brought into conduction.

A semiconductor memory device according to a ninth aspect is the semiconductor memory device according to the eighth aspect, wherein a spare word intersecting with a corresponding one spare sub-bit line pair among a plurality of spare sub-bit line pairs. The number of lines is equal to the number of word lines intersecting one corresponding sub bit line pair among the plurality of sub bit line pairs, and the number of spare memory cells connected to one spare sub bit line pair is It is made equal to the number of memory cells connected to one sub-bit line pair.

According to another aspect of the semiconductor memory device of the present invention, a plurality of main memory cell blocks, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, and a plurality of sense amplifiers. Means, and a plurality of comparison means. Each main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are arranged in a plurality of rows corresponding to each of the plurality of sub memory cell blocks, and each of the plurality of sub bit line pairs is arranged in a plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. Connected. The plurality of main bit line pairs are arranged in a plurality of rows. A plurality of switching means pairs are provided corresponding to the sub-bit line pairs, and each responds to the selection signal with the corresponding sub-bit line pair and the main bit line pair of the row in which the sub-bit line pair is located. Is made conductive. The plurality of sense amplifier means are provided corresponding to the plurality of main bit line pairs, and each amplifies the potential difference appearing between the main bit lines of the corresponding main bit line pair. Each comparing means correspondingly compares the potential of one main bit line pair of the corresponding two main bit lines of the plurality of main bit line pairs with the potential of the other main bit line pair. A semiconductor memory device according to claim 11, wherein a main memory cell block, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, a plurality of sense amplifier means, and a plurality of sense amplifier means. Equipped with dummy lines. The main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are
Each of the plurality of sub memory cell blocks is arranged in a plurality of rows, and each is connected to the plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. The plurality of main bit line pairs are arranged in a plurality of rows.
The plurality of switching means pairs are provided corresponding to the sub-bit line pairs, and each responds to the selection signal with the corresponding sub-bit line pair and the main bit line pair of the row in which the sub-bit line pair is located. Is made conductive. The plurality of sense amplifier means are provided corresponding to the plurality of main bit line pairs, and each amplifies the potential difference appearing between the main bit lines of the corresponding main bit line pair. The plurality of dummy lines are arranged along the column direction between the plurality of sub-bit line pairs and are given a predetermined potential.

According to another aspect of the semiconductor memory device of the present invention, there are provided a main memory cell block, a plurality of word lines, a plurality of sub bit line pairs, a plurality of main bit line pairs, a plurality of switching means pairs, a plurality of sense amplifier means, And a plurality of sub-equalizing means. The main memory cell block has a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and has a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. The plurality of word lines are arranged in a plurality of columns, and each is connected to the plurality of memory cells arranged in a corresponding column. The plurality of sub bit line pairs are arranged in a plurality of rows corresponding to each of the plurality of sub memory cell blocks, and each of the plurality of sub bit line pairs is arranged in a plurality of memory cells arranged in a corresponding row of the corresponding sub memory cell block. Connected. The plurality of main bit line pairs are arranged in a plurality of rows. The plurality of switching means pairs are provided corresponding to the sub-bit line pairs, and each responds to the selection signal with the corresponding sub-bit line pair and the main bit line pair of the row in which the sub-bit line pair is located. Is made conductive. The plurality of sense amplifier means are provided corresponding to the plurality of main bit line pairs, and each amplifies the potential difference appearing between the main bit lines of the corresponding main bit line pair. The plurality of sub-equalizing means are provided corresponding to the plurality of sub-bit line pairs, and each connect one sub-bit line of the corresponding sub-bit line pair to the other sub-bit line.

A semiconductor memory device according to a thirteenth aspect is the semiconductor memory device according to the twelfth aspect, further comprising a plurality of main equalizing means. The plurality of main equalizing means are provided corresponding to the plurality of main bit line pairs, and each connect one main bit line of the corresponding main bit line pair to the other main bit line.

A semiconductor memory device according to a fourteenth aspect is the semiconductor memory device according to any one of the fifth to thirteenth aspects, wherein the parasitic capacitance per unit length of the main bit line pair is a sub bit line. It is set to 1/4 or less of the parasitic capacitance per unit length of the pair.

[0047]

[Action]

In the semiconductor memory device according to the first aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, since the parasitic capacitance per unit length of the main bit line pair is set to 1/4 or less of that of the sub bit line pair, even if the length of the main bit line pair is long, the data from the memory cell is Is read, a sufficiently large potential difference is generated between the main bit lines. Therefore, the sense amplifier means can surely amplify the potential difference.

In the semiconductor memory device according to the second aspect, since the plurality of switching means are arranged in a staggered manner, that is, the plurality of switching means are distributed in the row direction, the layout of the switching means is easy. Become.

In the semiconductor memory device according to the third aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, since the plurality of switching means are arranged in a staggered manner, that is, the plurality of switching means are arranged dispersedly in the row direction, the layout of the switching means becomes easy.

According to another aspect of the semiconductor memory device of the present invention, one source / drain electrode of the MOS transistors arranged adjacent to each other is commonly formed. Is shortened.

In the semiconductor memory device according to the fifth aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, the MOS adjacent to each other
Since one source / drain electrode of the transistor is formed in common, the length of the semiconductor memory device in the row direction is shortened accordingly.

In the semiconductor memory device according to the sixth aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, since the shared sense amplifier system is adopted, the number of sense amplifier means can be further reduced, and the length of the semiconductor memory device in the row direction is further shortened.

In the semiconductor memory device according to the seventh aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, since the plurality of sense amplifier means are arranged in a zigzag manner, that is, the plurality of sense amplifier means are arranged dispersedly in the row direction, the layout of the sense amplifier means becomes easy.

In the semiconductor memory device according to the eighth aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, since a plurality of spare word lines are collectively arranged so as to intersect with one spare sub-bit line, any spare word line intersecting any of the sub-bit lines can be replaced with the spare word line. Further, since the sub bit line and the spare sub bit line are connected to the same main bit line, the same sense amplifier means is activated when it is replaced by the redundant word line and when it is not replaced.

According to another aspect of the semiconductor memory device of the present invention, the number of spare word lines intersecting one spare sub-bit line is equal to the number of word lines intersecting one spare sub-bit line. And the switching means is defective, the sub-bit line, the switching means, and the plurality of word lines intersecting the sub-bit line are collectively crossed with the spare sub-bit line, the spare switching means, and the spare sub-bit line. Replaced by a plurality of spare word lines.

In the semiconductor memory device according to the tenth aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, since the same data is stored correspondingly in the memory cell means on both sides of the comparison means, and the potential of one main bit line pair and the potential of the other main bit line pair are correspondingly compared, It is possible to quickly test whether or not the data is correctly read from all the memory cell means.

In the semiconductor memory device according to the eleventh aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, since a predetermined potential is applied to the dummy line arranged along the column direction between the sub bit lines, the parasitic transistor between the sub bit lines is forcibly turned off. Therefore, the data read between the sub-bit lines do not leak to each other.

In the semiconductor memory device according to the twelfth aspect, since the hierarchical bit line structure is adopted, the length of the main bit line pair can be increased and the number of sense amplifier means can be reduced. Therefore, the length of this semiconductor memory device in the row direction is shortened. Moreover, since one sub bit line and the other sub bit line are directly connected to each other, the main bit line pair is equalized more quickly than the sub bit line pair is indirectly equalized. .

In the semiconductor memory device according to the thirteenth aspect, since one main bit line and the other main bit line are directly connected, the main bit line pair is equalized surely and quickly.

In the semiconductor memory device according to the fourteenth aspect, since the parasitic capacitance per unit length of the main bit line pair is set to 1/4 or less of that of the sub bit line pair, even if the main bit line is Even if the length of the pair is long, a sufficiently large potential difference occurs between the main bit lines when data is read from the memory cell. Therefore, the sense amplifier means can surely amplify the potential difference.

[0062]

Embodiments of a semiconductor memory device according to the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 shows a first embodiment of the present invention.
3 is a wiring diagram showing a partial configuration of a DRAM according to the invention. Referring to FIG. 1, this DRAM has a plurality of main bit line pairs BLm.
And / BLm, a plurality of sense amplifiers SA, a plurality of word lines WL, and a plurality of sub bit line pairs BLs and / B.
Ls, a plurality of transfer gate pairs T and / T connecting the main bit line pair BLm and / BLm to the sub bit line pair BLs and / BLs, and a plurality of memory cells MC.
With.

FIG. 2 is a plan view specifically showing a part of the DRAM shown in FIG. Referring to FIGS. 1 and 2, main bit line pair BLm, / BLm is arranged along the row direction. Each sense amplifier SA is connected to each main bit line pair BLm, / BLm, and one main bit line (hereinafter referred to as “true main bit line”) BLm and the other main bit line (hereinafter referred to as “complementary”). Main bit line ") / BLm
Amplifies the potential difference between and. The word lines WL are arranged along the column direction. Each main bit line pair BLm, / BL
16 pairs of sub-bit line pairs BLs, / BLs are arranged along m.

The sub bit line pair BLs, / BLs has a parasitic capacitance cb per unit length of the main bit line pair BLm, / BLm.
The parasitic capacitance cbs per unit length is four times or more of m. That is, the parasitic capacitance cbm per unit length of the main bit line pair BLm, / BLm is equal to the sub bit line pair BLs, / B.
It is set to 1/4 or less of the parasitic capacitance cbs per unit length of Ls.

Each transfer gate T, / T is connected between the main bit line BLm or / BLm and the sub bit line BLs or / BLs, and its gate electrode is connected to the sub block selection line BS. Therefore, the transfer gates T and / T are connected to the sub block selection line BS.
In response to a predetermined control signal supplied from the main bit line BLm or / BLm and the sub bit line BLs or / BL.
Connect to one end of s.

Memory cell MC is arranged near the intersection of sub-bit line pair BLs and / BLs and word line WL. FIG. 3 is a cross-sectional view showing a memory cell of the DRAM shown in FIGS. 1 and 2 and its periphery.

Referring to FIG. 3, the memory cell MC is similar to that of FIG.
Similar to the memory cell MC in the conventional DRAM shown in FIG. 9, it is composed of one transfer gate TG and one memory cell capacitor Cs. Transfer gate TG is formed of an N channel MOS transistor, and has N type source / drain electrodes 16 and 18 connected to sub-bit line BLs1, and a gate electrode formed of word line WL1. The memory cell capacitor Cs includes a storage node 20 connected to one source / drain electrode 18 of the transfer gate TG,
And the cell plate 22.

Aluminum lines AL1 to AL3 for lowering the resistance of the word lines are provided on the word lines WL1 to WL3, respectively. Word lines WL1 to W
L3 and aluminum lines AL1 to AL3 are connected at predetermined intervals through contact holes (not shown).

Memory cell MC may be arranged below the intersection of sub-bit line BLs or / BLs and word line WL. Such a memory cell MC is called a cross-point memory cell, and is referred to as, for example, "IEDM Technical Digest
P. 592, December 1988 ".

Referring again to FIG. 1, 16 sub-bit line pairs BLs, BLs, along one main bit line pair BLm, / BLm.
/ BLs is provided. Also, 64 word lines WL1 intersect with one sub-bit line pair BLs, / BLs.
To WL64 are provided.

64 word lines WL1 to WL64
And n pairs of sub-bit line pairs BLs1, /
BLs1 to BLsn, / BLsn and 2 × n transfer gates T1, / T1 to Tn, / Tn
And 64 × n memory cells MC form each of the sub-blocks Bs1 to Bs16. 16 sub-blocks B
s1 to B16 form one main block Bm. This main block Bm corresponds to one of blocks B1 to B32 in the conventional DRAM shown in FIG.

Referring again to FIG. 2, for example, sub block selection lines BS2 and BS3 are arranged along the column direction between word line WL64 in sub block Bs2 and word line WL1 in sub block Bs3. . Sub-block selection lines BS2 and BS3 form the gate electrodes of transfer gates / T1 and T2. One of the source / drain regions of these two transfer gates / T1 has one contact hole 24
Is connected to the complementary main bit line / BLm1.

One source / drain region of the transfer gate / T1 in the sub block Bs2 is connected to the complementary sub bit line / BLs1 via the contact hole 26, and the transfer gate / T1 in the sub block Bs3 is connected.
One of the source / drain regions of T1 is connected to the complementary sub bit line / BLs1 via the contact hole 26.

One of the source / drain regions of the two transfer gates / T2 is a contact hole 2
4 to the complementary main bit line / BLm2. Transfer gate / T in sub-block Bs2
2 is connected to the complementary sub-bit line / BLs2 in the sub-block Bs2 via the contact hole 26, and one source / drain region of the transfer gate / T2 in the sub-block Bs3 is a contact. Sub block Bs3 through the hole 26
Is connected to the complementary sub-bit line / BLs2.

Therefore, sub-blocks Bs1 to Bs1
Transfer gates T1, / T1 disposed between 6
All of Tn and / Tn have one source / drain electrode in common. For example, the transfer gate T1 in the sub block Bs1 and the transfer gate T1 in the sub block Bs2 have one source / drain electrode in common.

Two transfer gates T which are adjacent to each other with one of these source / drain electrodes in common
1, / T1 to Tn, / Tn are arranged in a staggered pattern. That is, these adjacent transistors T1, /
Half of T1 to Tn, / Tn form the first group, and the other half form the second group. The transistors of the first group are arranged every two rows and every two columns, and the transistors of the second group are arranged on two rows and columns other than the row and the column where the transistors of the first group are arranged. Every two rows.

Here, the transfer gate of the memory cell MC and the transfer gates T1, / T1 to Tn, / Tn connecting the main bit line and the sub bit line are formed in the same structure.

DR having the hierarchical bit line structure as described above
In AM, since sub-bit line BLs or / BLs is surrounded by memory cell capacitor Cs, parasitic capacitance cbs per unit length thereof has a very large value. The main bit line BLm or / BLm is a memory cell MC
Since it is arranged above and not surrounded by the conductive layer, the parasitic capacitance cbm per unit length thereof becomes a very small value.

For example, sub-bit lines BLs and / BLs are formed of tungsten-silicide, and main bit line BL
When m and / BLm are formed of tungsten, the resistance value of the main bit line is very small.
The film thickness of BLm can be made extremely thin, and as a result, the parasitic capacitance of the main bit line can be further reduced.

Next, the DRA having this hierarchical bit line structure
The operation of M will be described. For example, sub-block Bs
When data is read from the memory cell MC in No. 1, the sub block select line BS1 is raised to the H level and the transfer gates T1, / T1 in the sub block Bs1.
All of ~ Tn and / Tn are in a conductive state. At this time, the other sub block selection lines BS2 to BS16 are maintained at the L level, so that those sub blocks Bs2 to Bs are kept.
16 transfer gates T1, / T1 to Tn, /
Tn is maintained in a non-conducting state.

Then, when one of the word lines WL1 to WL64 in sub-block Bs1 rises to the H level, the data from each memory cell MC connected to the selected word line corresponds to the corresponding sub-line. Bit line BLs
1 or / BLs1 to BLsn or / BLsn. Each read data is transmitted through the corresponding transfer gate T1 or / T1 to Tn or / Tn to the corresponding main bit line BLm1 or / BLm1 to BLmn.
Or transmitted to / BLmn. Then, one main bit line BLm1 to BLmn and the other main bit line / BLm1
~ / BLmn is the potential difference between the sense amplifiers SA1 to S1.
Amplified by An. After that, main bit line pair BLm
A selected main bit line pair of 1, BLm1 to BLmn, / BLmn is connected to an input / output line, and data appearing on the selected main bit line pair is output via the input / output line. .

On the other hand, when data is written to the memory cell MC in the sub block Bs1, the sub block Bs
The sub block selection line BS1 in 1 is raised to the H level, and the transfer gates T1, / T1 to Tn, / Tn in the sub block Bs1 are rendered conductive. Sub-block selection line B in other sub-blocks Bs2 to Bs16
S2-BS16 are maintained at the L level, and transfer gates T1, / T1-Tn, / Tn in those sub blocks Bs2-Bs16 are maintained in the non-conductive state.

Then, data is externally input via the input / output circuit (not shown) to the main bit line pair BLm1, / BLm1.
It is transmitted to BLmn, / BLmn. The transmitted data is amplified by the sense amplifier connected to the selected main bit line pair.

Then, when one selected word line WL in sub-block Bs1 rises to the H level, the amplified data is selected in the main bit selected in memory cell MC connected to that word line WL. It is written via the transfer gate and the sub bit line corresponding to the line pair.

The data of the memory cell connected to the unselected main bit line pair via the transfer gate and the sub bit line and also to the selected word line is read, but the sense amplifier is read. Since it has been activated, it is rewritten in the same manner as the read operation, so that data destruction does not occur.

DRAM having a hierarchical bit line structure as described above
In the above, since the main bit line pair BLm, / BLm is formed long, the number of sense amplifier rows S becomes smaller than in the conventional case. Therefore, the size of this DRAM is smaller than the conventional one. Further, since more memory cells can be arranged in a small area than in the conventional case, a DRAM having a large storage capacity can be easily realized.

For example, in the conventional 16 Mbit DRAM shown in FIG. 16, it is necessary to provide 34 sense amplifier rows S, whereas in this DRAM, 16 sense amplifier rows S may be provided. . Therefore,
The length of the DRAM in the row direction is significantly shorter than that of the conventional one.

Moreover, the parasitic capacitance cbm per unit length of the main bit line pair BLm, / BLm is equal to the sub bit line pair BL.
Since the parasitic capacitance cbs per unit length of s, / BLs is set to 1/4 or less, a sufficiently large potential difference is generated between the main bit line pair BLm, / BLm during data reading. Therefore, the sense amplifier SA can surely amplify the potential difference, so that accurate data is read.

Here, the reason why it is preferable that the parasitic capacitance cbm per unit length of the main bit line pair is set to 1/4 or less of the parasitic capacitance cbs of the sub bit line pair will be described in detail.

In the conventional DRAM, the parasitic capacitance per unit length of the bit line pair is cb, and the length of the bit line pair is l.
Then, the parasitic capacitance Cb of one bit line is represented by the following equation.

Cb = cb × l (1) In order to bring the advantage that the DRAM having a hierarchical bit line structure has a smaller number of sense amplifier columns, the length of the main bit line pair BLm, / BLm is the same as that of the conventional one. It must be at least twice the length of the bit line pair. On the other hand, if the length of the sub-bit line pair BLs, / BLs is not shorter than the length of the conventional bit line pair, the total parasitic capacitance Cbt of the main bit line pair and the sub bit line pair becomes larger than that of the conventional one. This is because the main bit line pair BLm, / BLm is always connected to the sub bit line pair BLs, / BLs.

Generally, in DRAM, memory cells are selected by binary addresses, so the number of memory cells connected to the sub-bit line is 2 ⁿ units, and therefore the length of the sub-bit line is 1/2 ^n. It can only be shortened in units. Therefore, the sub bit line pair BLs, / BL
Even if the length of s is long, it must be half the length of the conventional bit line pair.

Therefore, the total parasitic capacitance Cbt of the main and sub bit line pairs in this DRAM is represented by the following equation.

Cbt = cbs × l / 2 + 2 × cbm × l (2) Here, the parasitic capacitance cbs per unit length of the sub-bit line pair.
Is difficult to make smaller than the parasitic capacitance cb per unit length of the conventional bit line pair, the parasitic capacitance cbs per unit length of the sub bit line pair is per unit length of the conventional bit line pair. Is equal to the parasitic capacitance cb.

In this DRAM, the main bit line BLm
In order for a sufficiently large potential difference to occur between / BLm and / BLm, the following equation must hold.

Cbt ≦ Cb (3) Substituting the above equations (1) and (2) into this equation (3) gives the following equation.

Cbm ≦ cbs / 4 (4) As is apparent from the equation (4), the parasitic capacitance cbm per unit length of the main bit line pair is the parasitic capacitance per unit length of the sub bit line pair. It is desirable to be 1/4 or less of cbs. To reduce the parasitic capacitance cbm per unit length of the main bit line pair is to reduce the main bit line pair BL as described above.
Since m and / BLm are not surrounded by the conductive layer, they are easy. Further, the parasitic capacitance cbm per unit length of the main bit line pair is sufficient if it is at least one fourth of the parasitic capacitance cbs per unit length of the sub bit line pair, but if it is smaller than that, it will be further. preferable.

As described above, if the parasitic capacitance cbm per unit length of the main bit line pair is at least a quarter of the parasitic capacitance cbs per unit length of the sub bit line pair, the main bit line pair. Since a potential difference of the same magnitude as that in the conventional case occurs in BLm and / BLm, the sense amplifier SA can surely amplify the potential difference. Therefore, the DRA has a smaller size than the conventional one and has the same performance as the conventional one.
M is realized.

Further, the transfer gates T and / T are 2
Since they are arranged in a staggered pattern, the transfer gates can be easily laid out. Further, since one source / drain power source of the transfer gates T and / T is commonly used, the length of the main block Bm in the row direction becomes short.

[Second Embodiment] FIG. 4 shows a second embodiment of the present invention.
FIG. 6 is a wiring diagram showing a partial configuration of a DRAM according to the present invention.

Referring to FIG. 4, this DRAM has a plurality of main bit line pairs BLm and / BLm, a plurality of sense amplifiers SA, a plurality of word lines WL, and a plurality of sub bit line pairs B.
Ls, / BLs, a plurality of transfer gates T,
The memory cell MC includes a plurality of memory cells MC and a pseudo word line WLp. The parasitic capacitance cbm per unit length of the main bit line pair BLm, / BLm is preferably the sub bit line pair BLs, / B.
The parasitic capacitance cbs per unit length of Ls is set to 1/4, and more preferably smaller than that.

The difference between the second embodiment and the first embodiment is that the transistor pairs composed of two transfer gates T and / T are arranged in a zigzag pattern in the first embodiment. In the second embodiment, they are arranged in one column along the column direction, and two pseudo word lines WLp are arranged between the sub blocks Bs2 and Bs3.

In the second embodiment, one sub bit line BLs is connected to one main bit line BLm via the transfer gate T. Other sub bit line / BL
s is connected to the other main bit line / BLm via the transfer gate / T.

In the second embodiment, the transfer gates T and / T are arranged in one row, and the sub block selection line BS is provided in each of the sub blocks Bs1 to Bs16.
Since only one BS1, BS2, BS3 ... Is arranged, the length in the row direction is shorter than that in the first embodiment. The purpose and function and effect of the pseudo word line WLp will be described in detail later in Example 11.

[Third Embodiment] FIG. 5 shows a third embodiment of the present invention.
FIG. 6 is a wiring diagram showing a partial configuration of a DRAM according to the present invention.

Referring to FIG. 5, this DRAM has a plurality of main bit line pairs BLm1, / BLm1, BLm2, / BL.
m2, a plurality of sense amplifiers SA1, SA2, a plurality of word lines WL1 to WL64, a plurality of sub bit line pairs BLs1, / BLs1, BLs2, / BLs2 ..., A main bit line pair and a sub bit line pair. , Transfer gates T1, / T1, T2, / T2, ..., A plurality of memory cells MC, and a plurality of transfer gates Tb1, / Tb1, Tb connecting a main bit line pair and a sense amplifier.
2, / Tb2 ...

The parasitic capacitance cbm per unit length of the main bit line pair BLm, / BLm is preferably the sub bit line pair BL.
The parasitic capacitance cbs per unit length of s, / BLs is set to a quarter, and more preferably smaller than that.

The third embodiment differs from the first embodiment in that the shared sense amplifier system is adopted. That is, one sense amplifier SA1, SA2
Two main bit line pairs BLm1, / BLm on both sides of ...
1, BLm2, / BLm2 ... Are arranged. Main bit line pair BLm1, / BLm1, BLm2, / B on one side
Between Lm2 and the sense amplifiers SA1, SA2 ...
Transfer gate Tb1, / Tb1, Tb2, / T
b2 ... Are connected. Main bit line pair BLm on the other side
, / BLm1, BLm2 / BLm2 and the sense amplifiers SA1, SA2 ...
b1, / Tb1, Tb2, / Tb2 are connected.

Transfer gates Tb1, / on one side
The gate electrodes of Tb1, Tb2, / Tb2 are commonly connected to one block selection line SS1. Transfer gates on the other side Tb1, / Tb1, Tb2, / Tb2
Gate electrodes are commonly connected to one block selection line SS2.

These block selection lines SS1 and SS
A complementary selection signal is applied to 2. Therefore,
The sense amplifiers SA1, SA2 ... Have two main bit line pairs BLm1, / BLm1, BLm2, / BLm2 ...
One of the main bit line pairs BLm1, / BLm1, BLm2, / BLm connected selectively.
Amplify the potential difference between 2 ...

In the third embodiment, for example, the left 2
The two transfer gates Tb1 and / Tb1 are the first
Form a transistor pair. The first transistor pair connects the left main bit line pair BLm1, / BLm1 and the sense amplifier SA1 in response to the first selection signal from the block selection line SS1. The two transfer gates Tb1 and / Tb1 on the right side form a second transistor pair. The second transistor pair includes a right main bit line pair BLm1, / BLm1 and a sense amplifier SA1 in response to a second selection signal from the block selection line SS2.
And connect. This second selection signal is complementary to the first selection signal.

In the third embodiment, since two main bit line pairs share one sense amplifier, the number of sense amplifiers is reduced. Therefore, the length of the DRAM in the row direction is further reduced.

[Fourth Embodiment] FIG. 6 shows a fourth embodiment of the present invention.
FIG. 6 is a wiring diagram showing a structure of a DRAM according to the present invention.

The fourth embodiment differs from the third embodiment in that shared sense amplifiers SA1 to SAn are arranged in a staggered pattern. That is, the sense amplifier S
The row pitch of A1 to SAn is twice the row pitch of the main bit line pair and the sub bit line pair. Therefore, the layout of the sense amplifier becomes easier than that of the third embodiment.

[Fifth Embodiment] FIG. 7 shows a fifth embodiment of the present invention.
FIG. 6 is a wiring diagram showing a partial configuration of a DRAM according to the present invention.

Referring to FIG. 7, this DRAM has a plurality of main bit line pairs BLm and / BLm, a plurality of sense amplifiers SA, a plurality of word lines WL, and a plurality of sub bit line pairs B.
Ls, / BLs, a plurality of transfer gates T, / T connecting the main bit line pair and the sub bit line pair, a plurality of memory cells MC, and a pseudo word line WLp. The parasitic capacitance cbm per unit length of the main bit line pair BLm, / BLm is preferably 1/4 of the parasitic capacitance cbs per unit length of the sub bit line pair BLs, / BLs, and more preferably more than that. It has been made smaller.

The fifth embodiment differs from the second embodiment in that sense amplifiers SA are alternately arranged. That is, half of the plurality of sense amplifiers SA in the entire DRAM according to the fourth embodiment form the first group, and the remaining half form the second group. The sense amplifiers SA of the first group are arranged every two rows and every two columns, and the sense amplifiers SA of the second group are other than the rows and columns where the sense amplifiers SA of the first group are arranged. Are arranged every two rows and every two columns on the rows and columns.

As described above, in the fifth embodiment, since the sense amplifiers SA are arranged every two rows and every two columns, the layout of the sense amplifiers SA1 to SAn becomes easy.

[Sixth Embodiment] FIG. 8 shows a sixth embodiment of the present invention.
FIG. 6 is a wiring diagram showing a partial configuration of a DRAM according to the present invention.

Referring to FIG. 8, this DRAM has a plurality of main bit line pairs BLm and / BLm, a plurality of sense amplifiers SA, a plurality of word lines WL, and a plurality of sub bit lines BL.
s, / BLs, a plurality of transfer gates T connecting the main bit line pair and the sub bit line, and a memory cell MC. The parasitic capacitance cbm per unit length of the main bit lines BLm, / BLm is preferably the sub-bit lines BLs, / BLm.
The parasitic capacitance cbs per unit length of BLs is set to 1/4, and more preferably smaller than that.

The difference of the sixth embodiment from the second embodiment is that in the second embodiment, the sub bit line pair BLs, /
While the BLs are arranged in parallel, that is, like a folded bit line structure, in the sixth embodiment, the sub bit lines BLs and / BLs are arranged in a straight line, that is, like an open bit line. That is the point. Therefore, the sub bit lines BLs, / BLs and the word lines WL
Memory cells MC are arranged at all the intersections with.

For example, when data is read from memory cell MC in sub block Bs1, sub block select line BS1 rises to H level. As a result, the transfer gates T1, T2, T3 ... In the sub block Bs1.
Becomes conductive, and the sub bit line / BLs and one main bit line / BLm are connected. In this state, when the selected word line WL rises to the H level, the word line W
Data is read from the memory cell MC connected to L,
A potential difference occurs between the main bit line pair BLm and / BLm. This potential difference is amplified by the sense amplifier SA.

In Examples 1 to 5 above,
While the pitch of the main bit line pair and the pitch of the sub bit line pair are the same, in the sixth embodiment, the pitch of the sub bit line pair is twice the pitch of the main bit line pair. Therefore, the DRAM according to the sixth embodiment can be manufactured more easily than the DRAMs according to the first to fifth embodiments.

[Embodiment 7] FIG. 9 shows a seventh embodiment of the present invention.
FIG. 6 is a wiring diagram showing a partial configuration of a DRAM according to the present invention.

Referring to FIG. 9, this DRAM has a plurality of main bit line pairs BLm, / BLm similar to the second embodiment.
, A plurality of sense amplifiers SA, and a plurality of word lines WL
A plurality of sub-bit line pairs BLs, / BLs, a plurality of transfer gates T, / T connecting the main bit line pair and the sub-bit line pair, a plurality of memory cells MC, and a pseudo word line WLp. Prepare

Unlike the second embodiment, this DRAM further includes a plurality of spare word lines WLs, a plurality of spare sub-bit line pairs BLss, / BLss, a main bit line pair and a spare sub-bit line pair. A plurality of spare transfer gates Ts, / Ts for connecting the plurality of spare memory cells and a plurality of spare memory cells M
Cs and.

The spare word lines WLs are arranged in the column direction. Spare sub-bit line pair BLss, / BL
The ss is arranged along the main bit line pair BLm, / BLm. Spare transfer gate Ts, / Ts
Connects one main bit line BLm, / BLm to one spare sub-bit line BLss, / BLss. The spare memory cell MCs is arranged at or near the intersection of the main bit line pair BLm, / BLm and the spare sub bit line pair BLss, / BLss.

Main block Bm in this DRAM
Is 16 sub-blocks Bs1 to Bs16 and 1
It is composed of a spare sub-block Bss.
The spare sub-block Bss is a redundant circuit that is activated when there is a defect somewhere in the normal sub-blocks Bs1 to Bs16.

One regular sub-block Bs1 to Bs1
Six word lines WL1 to WL64 are arranged in the unit 6. Eight spare word lines WLs1 to WLs8 are arranged in the spare sub-block Bss.

The parasitic capacitance cbm per unit length of the main bit line pair BLm, / BLm is preferably 4 of the parasitic capacitance cbs per unit length of the sub bit line pair BLs, / BLs.
It is reduced by a factor of 1, more preferably by less. Similarly, the parasitic capacitance cbm per unit length of the main bit line pair BLm, / BLm is preferably the parasitic capacitance cb per unit length of the spare sub bit line pair BLss, / BLss.
It is made a quarter of ss, more preferably smaller than that.

In this DRAM, if any word line WL is defective, the defective word line WL is replaced with any spare word line WLs. That is, when the defective word line WL is accessed,
Instead of the defective word line WL, the spare word line WLs is raised to H level. At this time, the spare sub-block selection line BSs is also raised to the H level, so that at the time of reading, the spare memory cell MCs connected to the spare word line WLs is mainly connected via the spare transfer gates Ts and / Ts. Bit line pair BLm, / B
Data is read into Lm. At the time of writing, the data of the main bit line pair BLm, / BLm is spare transfer gates Ts, / Ts and the spare sub bit line pair BLs.
It is written into the spare memory cell MCs via s, / BLss.

Therefore, in one main block Bm, even when the spare word line WLs is selected, the same sense amplifier SA as when the regular word line WL is selected is activated. That is, when the spare word line WLs is selected, it is not necessary to activate the sense amplifier SA different from the sense amplifier SA that is activated when the regular word line WL is selected. Is never complicated.

If the defective word line is less than 8 out of the 1024 word lines WL, no matter which sub block Bs1 to Bs16 the defective word line is in, the spare sub block Bss is stored. Spare word line WL
can be replaced with s. Therefore, the manufactured DR
The AM relief rate is improved.

[Embodiment 8] FIG. 10 is a wiring diagram showing a partial structure of a DRAM according to an embodiment 8 of the invention.

Referring to FIG. 10, the DRAM includes a plurality of main bit line pairs BLm and / BLm and a plurality of sense amplifiers S.
A, a plurality of word lines WL, and a plurality of sub bit line pairs BL
s, / BLs and a plurality of transfer gates T, / T connecting one main bit line and one sub bit line in response to a control signal supplied from the sub block selection line BS.
And a plurality of memory cells MC.

This DRAM further includes a plurality of spare word lines WLs and a plurality of spare sub-bit line pairs BLss //.
One main bit line BLm, / B in response to BLss and a spare control signal from the spare sub-block select line BSs.
A plurality of spare transfer gates Ts, / for connecting Lm and one spare sub-bit line BLss, / BLss.
Ts and a plurality of spare memory cells MCs.

The difference of the eighth embodiment from the seventh embodiment is that the spare sub-block Bss has 64 spare word lines W similarly to the regular sub-blocks Bs1 to Bs16.
The point is that Ls1 to WLs64 are provided.

The seventh embodiment cannot deal with the case where the entire regular sub-block Bs becomes defective. On the other hand, in the eighth embodiment, one regular sub-block Bs
Even if all of 1 to Bs16 become defective, the entire defective sub-block can be replaced with the spare sub-block Bss. Therefore, the manufactured DRA
The relief rate of M is further improved.

[Ninth Embodiment] FIG. 11 is a wiring diagram showing a partial structure of a DRAM according to a ninth embodiment of the present invention.

Referring to FIG. 11, this DRAM has a plurality of main bit line pairs BLm, / BLm, a plurality of sense amplifiers SA, a plurality of word lines WL, and a plurality of sub bit line pairs BLs, / BLs. And transfer gates T and / T connecting one main bit line and one sub bit line, a plurality of memory cells MC, and a test circuit 26.

The ninth embodiment differs from the first embodiment in that the test circuit 26 is provided. The test circuit 26 is arranged between the main block Bm1 and the main block Bm2, and is composed of a wired exclusive OR circuit.

Although not shown, on the right side of FIG. 11, the sense amplifier row S3, the main block Bm2,
A test circuit, a main block Bm4, and a sense amplifier row S4 are arranged. The same applies to the right side. That is, the main blocks Bm3 and Bm4
A test circuit is also provided between the and.

The test circuit 26 includes a plurality of comparison circuits C.
Equipped with M1 to CMn. The comparison circuits CM1 to CMn are
Four N-channel MOS transistors Tc1 to Tc
It is composed of 4. The drain electrodes of the transistors Tc1 and Tc3 in the comparison circuits CM1 to CMn are
It is commonly connected to the match line ML. Comparison circuit CM1
The source electrodes of the transistors Tc2 and Tc4 in CMn are commonly connected to the common source line MCS.

When this DRAM is tested, all memory cells MC in main block Bm1 are tested.
And all memory cells MC in the main block Bm2
And, the same data is written correspondingly. For example, the word line W in the sub block Bs2 of the main block Bm1
Memory cell MC connected to L and sub-bit line BLs1
, The same data as the data written in the memory cell MC connected to the word line WL and the sub bit line BLs1 in the sub block Bs2 of the main block Bm2 is written. In addition, the sub block Bs3 of the main block Bm1
In the memory cell MC connected to the word line WL2 and the sub bit line BLs2 in the sub block Bs3 of the main block Bm2, the word line WL2 and the sub bit line BLs2 in the sub block Bs3 are included.
The same data as the data written in the memory cell MC connected to and is written.

Before the data is read from the memory cell MC, the match line ML is precharged to H level,
Moreover, the H level is supplied to the common source line MCS.

In this state, when word line WL at the relatively same position between both main blocks Bm1 and Bm2 is activated, data is read from corresponding memory cell MC to corresponding sub bit line BLs. It The read data is transmitted to the corresponding main bit line BLm and amplified by the sense amplifier SA.

Since the same data, for example, H-level data, is written in both main blocks Bm1 and Bm2 correspondingly, if there is no defect in either main block Bm1 or Bm2, comparison circuit CM1 is generated.
Whether the transistors Tc1 and Tc3 in .about.CMn are both turned on, for example, based on H-level data, and the transistors Tc2 and Tc4 are both read, for example, L-level based on data; Alternatively, transistors Tc1 and Tc3 are both non-conductive and transistors Tc2 and Tc4 are both conductive. Therefore, match line ML and common source line MCS are maintained in a non-conductive state. Therefore, even if the common source line MCS is at the L level in this state, the match line ML maintains the H level, and it can be seen that no defect exists.

If any one of the main blocks Bm1 or Bm2 has a defect, the transistors Tc1 and Tc1.
Since the c2 is in the conducting state and the transistors Tc3 and Tc4 are in the non-conducting state or vice versa, the match line M
L and the common source line MCS are brought into conduction. Therefore, when the common source line MCS falls to the L level, the match line ML also falls to the L level, and it can be seen that there is a defect.

That is, the potentials of the main bit line pair BLm and / BLm in the main block Bm1 and the potentials of the main bit line pair BLm and / BLm in the main block Bm2 all correspond to each other. If the match line M
L is maintained at H level. However, any one main bit line pair BLm in the main block Bm1
And / BLm and the corresponding main block Bm
When the potentials of main bit line pair BLm and / BLm in 2 do not correspond to each other, match line ML is lowered to the L level.

As described above, according to this DRAM, the memory cells MC connected to the two word lines WL can be simultaneously tested, so that the entire DRAM can be quickly tested.

[Embodiment 10] FIG. 12 is a wiring diagram showing a structure of a test circuit in a DRAM according to Embodiment 10 of the present invention.

Referring to FIG. 12, this tenth embodiment is directed to one having a spare memory cell consisting of a spare row,
The test circuit 28 includes a plurality of comparison circuits CM and a plurality of spare comparison circuits CMs. Each comparison circuit CM has two pairs of main bit lines BLm and / BLm arranged on both sides thereof.
Connected with. Each spare comparison circuit CMs has two pairs of spare main bit line pairs BLms, / arranged on both sides thereof.
It is connected to BLms. That is, this DRAM
Includes a redundant circuit arranged along the row direction.

For example, when main bit line pair BLm, / BLm or memory cell MC connected thereto has a defect, main bit line pair BLm1, / BLm1 to BLmi including main bit line pair BLm, / BLm having the defect. ，
/ BLmi instead of the spare main bit line pair BL in row i
ms1, / BLms1 to BLmsi, / BLmsi
Are activated in response to the selection signal SE. That is, in this DRAM, when a normal memory cell MC or the like is defective, it is replaced with a redundant circuit in units of i rows.

The test circuit 28 further includes a link element 30.
And an N-channel MOS transistor 32. The link element 30 is connected between the source electrodes of the transistors Tc2 and Tc4 in the i comparison circuits CM1 to CMi and the common source line MCS. The link element 30 is connected every i rows. The N-channel MOS transistor 32 is connected between the source electrodes of the transistors Tc2 and Tc4 in the i spare comparison circuits CMs1 to CMsi and the common source line MCS. The source electrode of the transistor 32 has a selection signal S for activating the redundant circuit described above.
E is supplied.

In the case where this DRAM is tested, if a redundant circuit is used, the link element 30 connected to the corresponding comparison circuit CM1-CMi is disconnected.

Therefore, this D is the same as in the ninth embodiment.
When the RAM is tested, the comparison circuit CM deactivated
No test result data is output from 1 to CMi.
Therefore, the DRAM provided with the redundant circuit can be accurately tested along the row direction. If the link element 30 as described above is not provided, the row is always defective and the match line ML is always at the L level.

[Embodiment 11] FIG. 13 is a plan view showing a partial structure of a DRAM according to an embodiment 11 of the invention.

The eleventh embodiment is an improvement of the sixth embodiment shown in FIG. That is, in the fifth embodiment, one end of the one sub-bit line BLs and one end of the other sub-bit line / BLs face each other, so that the data generated on the one sub-bit line BLs is parasitic between them. It may slightly leak to the other sub-bit line / BLs through the transistor.

Therefore, as shown in FIG. 13, two pseudo word lines WLp are arranged between one sub-bit line BLs and the other sub-bit line / BLs. These pseudo word lines WLp are arranged along the column direction between the word line WL64 in the left sub block and the word line WL1 in the right sub block. Then, the ground potential GND is applied to these pseudo word lines WLp.

Sub-bit lines BLs and / BLs are connected to a transfer gate field region 36 through a contact hole 34. This transfer gate
Sub bit lines BLs, / BLs and main bit lines BLm, / B
It is for connecting to Lm. The field region 36 is connected to a memory cell capacitor (not shown) via a contact hole 38. The memory cell capacitor is formed on this contact hole 38. A memory cell capacitor (not shown) is also formed between the pseudo word lines WLp. This is to make the structure between the pseudo word lines WLp the same as the structure of the other parts to facilitate the manufacturing process.

DRAM provided with this pseudo word line WLp
, The ground potential G is applied to the pseudo word line WLp.
ND is given. On the other hand, an N-channel transistor is parasitic between the sub bit lines BLs and / BLs. Therefore, this parasitic transistor is forced to be in a non-conducting state, so that sub-bit lines BLs and / BLs are
Data does not leak to each other.

[Embodiment 12] FIG. 14 is a wiring diagram showing a partial structure of a DRAM according to Embodiment 12 of the invention.
FIG. 15 is a plan view specifically showing a part of the DRAM shown in FIG.

Referring to FIGS. 14 and 15, this DR
AM includes a plurality of main bit line pairs BLm, / BLm, a plurality of sense amplifiers SA, a plurality of word lines WL, a plurality of sub bit line pairs BLs, / BLs, and a main bit line BLm,
A plurality of transfer gates T, / T connecting / BLm and sub-bit lines BLs, / BLs; a plurality of memory cells MC; and an N-channel MOS transistor Tem for equalizing main bit line pair BLm, / BLm. , N for equalizing the sub-bit line pair BLs, / BLs
A channel MOS transistor Tes is provided.

The most characteristic feature of the twelfth embodiment is that an N channel MOS transistor Tes for equalizing sub-bit line pair BLs and / BLs is provided. The N-channel MOS transistor Tem for equalizing the main bit line pair BLm and / BLm is not shown in the first to eleventh embodiments, but is provided similarly to the twelfth embodiment.

Referring to FIG. 15, the sub-bit line pair equalizing transistor Tes has the same structure as the sub-bit line pair BLs.
And / BLs, and two equalize lines EQs2 arranged along the column direction are connected to the transistors T
It constitutes the gate electrode of es.

FIG. 16 is a timing chart showing an operation of the DRAM shown in FIGS. 14 and 15.

First, as shown in FIGS. 16B, 16C and 16D, the equalizing line EQm for the main bit line and the equalizing lines Qs1 and Qs2 for the sub bit lines are set to the H level. . Therefore, the main bit line pair BLm, /
The potentials of BLm and the sub-bit line pair BLs, / BLs are all made equal.

Then, as shown in FIG. 16E, when sub-block select line BS1 in sub-block Bs1 rises to the H level, sub-bit line pair BLs and / BLs in sub-block Bs1 are connected to main bit lines. BLm and /
It is connected to BLm, respectively.

Then, as shown in FIGS. 16B and 16C, an equalize line EQm for the main bit line and an equalize line EQs for the sub bit line in sub block Bs1.
Both 1 fall to L level. At this time, the equalize line EQs2 for the sub bit line in the sub block Bs2 is maintained at the H level.

Then, as shown in FIG. 16A, when any word line WL in sub-block Bs1 rises to the H level, data from memory cell MC connected to that word line corresponds to the sub-line. Bit lines BLs, / BLs
Read to. The read data is read to main bit line BLm or / BLm via corresponding transfer gate T1, T2 or / T1, / T2.

As described above, in this DRAM, sub-bit line pair BLs and / BLs is main bit line pair BLm.
Since they are equalized in advance before being connected to / BLm and / BLm, even if the length of sub-bit line pair BLs, / BLs is long, their potentials are quickly made equal. Therefore, the data read / write time is not delayed as compared with the conventional case.

Sub bit line pair BLs and / BLs
Since the equalizing line EQs forming the gate electrode is set to the L level except when is equalized,
Similar to the eleventh embodiment, the sub-bit line pair BLs and /
The parasitic transistor between BLs is made non-conductive, and no data leaks between them. Further, since the transistor Tes for equalizing the sub-bit line pair is provided by utilizing the space between the regularly arranged memory cells MC, the layout area is not particularly increased. Moreover, without significantly changing the manufacturing process,
This transistor Tes can be formed.

In the twelfth embodiment, the sub-bit line pair BLs, / BLs is formed like an open bit line structure. However, as shown in FIG. The same effect can be obtained even if the equalizing transistor is provided for each sub-bit line pair in the DRAM provided with and is controlled by the timing shown in FIG.

[Other Embodiments] In the above embodiment,
Although the parasitic capacitance per unit length of the main bit line pair is set to 1/4 or less of the parasitic capacitance per unit length of the sub bit line pair, the present invention is not particularly limited thereto.

That is, for example, in a DRAM having a hierarchical bit line structure, transfer gates connecting a main bit line pair and a sub bit line pair may be arranged alternately. Further, the shared sense amplifier system may be adopted in the DRAM having the hierarchical bit line structure. In a DRAM having a hierarchical bit line structure,
It suffices that the sense amplifiers are arranged alternately.

In the DRAM having the hierarchical bit line structure, all spare word lines may be arranged in the spare sub block. Further, in such a DRAM, the number of word lines in the regular sub block and the number of spare word lines in the spare sub block may be equal.

In a DRAM having a hierarchical bit line structure, a test circuit may be provided between main blocks. Further, in such a DRAM, a redundant circuit may be provided along the row direction, a test circuit corresponding to the redundant circuit may be provided, and a link element may be provided in the test circuit corresponding to the regular circuit.

In a DRAM having a hierarchical bit line structure, it is sufficient that pseudo word lines are arranged between the sub bit line pairs along the column direction. Further, an equalizing transistor dedicated to the sub bit line pair may be provided between the sub bit line pair.

In addition, for example, in a DRAM having a hierarchical bit line structure, transfer gates connecting a main bit line pair and a sub bit line pair are alternately arranged, a shared sense amplifier system is adopted, and the sense amplifier is The above-mentioned embodiments may be appropriately combined, such as those arranged alternately.

[0181]

According to the semiconductor memory device of the first aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, since the parasitic capacitance per unit length of the main bit line pair is set to 1/4 or less of that of the sub bit line, data can be accurately read from the memory cell.

According to the semiconductor memory device of the second aspect, since the plurality of switching means are arranged in a zigzag pattern, the layout can be facilitated.

According to the semiconductor memory device of the third aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, since the plurality of switching means are arranged in a staggered pattern, the layout can be facilitated.

According to the semiconductor memory device of the fourth aspect, since one source / drain electrodes of the MOS transistors adjacent to each other are formed in common, the layout area can be further reduced.

According to the semiconductor memory device of the fifth aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, the MOS adjacent to each other
Since one source / drain electrode of the transistor is formed in common, the layout area can be made smaller.

According to the semiconductor memory device of the sixth aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, since the shared sense amplifier system is adopted, the layout area can be further reduced.

According to the semiconductor memory device of the seventh aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, since the plurality of sense amplifier means are arranged in a staggered pattern, the layout area can be further reduced.

According to the semiconductor memory device of the eighth aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, even if there is a defect in the word line intersecting any of the sub-bit lines, it can be replaced with the spare word line, so that this semiconductor memory device can be manufactured with a high yield. Further, when the spare word line is used, the same sense amplifier as when the normal word line is used is activated, so that the control is not particularly complicated.

According to the semiconductor memory device of the ninth aspect, when there is a defect in one normal sub-bit line and a word line intersecting with the normal sub-bit line, one spare sub-bit line and the spare sub-bit line are crossed together. This semiconductor memory device can be manufactured with a high yield because it can be replaced with a spare word line.

According to the semiconductor memory device of the tenth aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, since the potential of one main bit line and the potential of the other main bit line pair are correspondingly compared, it is possible to quickly test whether or not this semiconductor memory device is normal.

According to the semiconductor memory device of the eleventh aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, since the data read from the memory cell to one sub-bit line does not leak to the other sub-bit line, the data can always be read accurately.

According to the semiconductor memory device of the twelfth aspect, since the hierarchical bit line structure is adopted, the layout area can be made smaller or the storage capacity can be made larger. Moreover, since the sub bit line is directly equalized, the operation speed does not slow down.

According to the semiconductor memory device of the thirteenth aspect, since the main bit line is also directly equalized, the main bit line is accurately and promptly equalized.

According to the semiconductor memory device of the fourteenth aspect, since the parasitic capacitance per unit length of the main bit line pair is set to 1/4 or less of that of the sub bit line, the data is read from the memory cell. Can be read accurately.

[Brief description of drawings]

FIG. 1 is a wiring diagram showing a partial configuration of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a part of the DRAM shown in FIG. 1 more specifically.

FIG. 3 is a sectional view showing a memory cell and its periphery in the DRAM shown in FIGS. 1 and 2.

FIG. 4 is a wiring diagram showing a partial configuration of a DRAM according to a second embodiment of the present invention.

FIG. 5 is a wiring diagram showing a partial configuration of a DRAM according to a third embodiment of the present invention.

FIG. 6 is a wiring diagram showing a structure of a DRAM according to a fourth embodiment of the present invention.

FIG. 7 is a wiring diagram showing a partial configuration of a DRAM according to a fifth embodiment of the present invention.

FIG. 8 is a wiring diagram showing a partial configuration of a DRAM according to a sixth embodiment of the present invention.

FIG. 9 is a wiring diagram showing a partial configuration of a DRAM according to a seventh embodiment of the present invention.

FIG. 10 is a wiring diagram showing a partial configuration of a DRAM according to an eighth embodiment of the present invention.

FIG. 11 is a wiring diagram showing a partial configuration of a DRAM according to a ninth embodiment of the present invention.

FIG. 12 is a wiring diagram showing a partial configuration of a DRAM according to a tenth embodiment of the present invention.

FIG. 13 is a plan view specifically showing a partial configuration of a DRAM according to an eleventh embodiment of the present invention.

FIG. 14 is a wiring diagram showing a partial configuration of a DRAM according to a twelfth embodiment of the present invention.

FIG. 15 is a plan view showing a part of the DRAM shown in FIG. 14 more specifically.

16 is a timing chart showing an operation of the DRAM shown in FIGS. 14 and 15. FIG.

FIG. 17 is a block diagram showing an overall configuration of a conventional DRAM.

FIG. 18 is a wiring diagram showing a partial configuration of the conventional DRAM shown in FIG.

FIG. 19 is a wiring diagram showing a memory cell and its periphery in the DRAM shown in FIGS. 17 and 18.

[Explanation of symbols]

BLm, / BLm Main bit line pair, BLs, / BLs
Sub-bit line pair, T // T transfer gate, SA
Sense amplifier, WL word line, MC memory cell,
BLms, / BLms spare main bit line pair, BLss,
/ BLss spare sub-bit line pair, Ts, / Ts spare transfer gate, WLs spare word line, CM comparator circuit, 26, 28 test circuit, 30 link element,
WLp pseudo word line, Tes Sub-bit line equalizing transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyasu Fujishima 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation ULS Development Research Center

Claims (14)

[Claims] 1. A main memory cell block having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. A plurality of word lines connected to a plurality of memory cells arranged in a corresponding column, arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks, respectively. A plurality of sub-bit line pairs connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub-memory cell block, arranged in the plurality of rows, each unit of the sub-bit line pair A plurality of main bit line pairs having a parasitic capacitance per unit length which is less than or equal to ¼ of the parasitic capacitance per length, are provided corresponding to the sub bit line pairs, and each of them is responsive to a selection signal, Corresponding sub-bit line And a plurality of switching means pairs for bringing the main bit line pair of the row in which the sub bit line pair is located into a conductive state, and the plurality of main bit line pairs are provided corresponding to the respective main bit line pairs. A semiconductor memory device comprising a plurality of sense amplifier means for amplifying a potential difference appearing between main bit lines of a bit line pair. 2. Each switching means pair includes a first switching means arranged at one end side of the corresponding sub bit line pair and a second switching means arranged at the other end side of the corresponding sub bit line pair. A switching means, and a first sub-bit line pair for an adjacent sub-memory cell block.
Alternatively, one switching means of the second switching means is arranged adjacent to each other.
The semiconductor memory device according to 1. 3. A main memory cell block having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns, A plurality of word lines connected to a plurality of memory cells arranged in a corresponding column, arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks, respectively. A plurality of sub bit line pairs connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub memory cell block; a plurality of main bit line pairs arranged in the plurality of rows; A plurality of lines are provided corresponding to the line pairs, each of which makes a corresponding sub-bit line pair and a main bit line pair of a row in which the sub-bit line pair is located conductive in response to a selection signal. Switching means pair And a plurality of sense amplifier means provided corresponding to the plurality of main bit line pairs, each for amplifying a potential difference appearing between the main bit lines of the corresponding main bit line pair. The pair has first switching means arranged on one end side of the corresponding sub bit line pair and second switching means arranged on the other end side of the corresponding sub bit line pair, and is adjacent to each other. To the adjacent sub-bit line pair of the sub-memory cell block
2. A semiconductor memory device, wherein one switching means of the switching means is disposed adjacent to each other. 4. The first and second of each switching means pair.
Is connected between the sub bit line of the corresponding sub bit line pair and the main bit line of the main bit line pair of the row in which the sub bit line pair is located, and the MOS transistor receives the selection signal at its gate electrode. One of the source / drain electrodes connected to the main bit line of the MOS transistor arranged adjacent to the adjacent sub bit line pair of the adjacent sub memory cell block is formed in common. 4. The semiconductor memory device according to claim 2 or claim 3. 5. A main memory cell block having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. A plurality of word lines connected to a plurality of memory cells arranged in a corresponding column, arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks, respectively. A plurality of sub bit line pairs connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub memory cell block; a plurality of main bit line pairs arranged in the plurality of rows; A plurality of lines are provided corresponding to the line pairs, each of which makes a corresponding sub-bit line pair and a main bit line pair of a row in which the sub-bit line pair is located conductive in response to a selection signal. Switching means pair And a plurality of sense amplifier means provided corresponding to the plurality of main bit line pairs, each for amplifying a potential difference appearing between the main bit lines of the corresponding main bit line pair. The pair is two MOS transistors arranged adjacent to the switching means pair for the adjacent sub-bit line pair of the adjacent sub-memory cell block and receiving the selection signal at the gate electrode thereof. 2. The semiconductor memory device according to claim 1, wherein one source / drain electrode connected to the main bit line of the MOS transistor arranged adjacent to the adjacent sub-bit line pair is formed in common. 6. A main memory cell block having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. A plurality of word lines connected to a plurality of memory cells arranged in a corresponding column, arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks, respectively. A plurality of sub bit line pairs connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub memory cell block; a plurality of main bit line pairs arranged in the plurality of rows; A plurality of lines are provided corresponding to the line pairs, each of which makes a corresponding sub-bit line pair and a main bit line pair of a row in which the sub-bit line pair is located conductive in response to a selection signal. Switching means pair And a plurality of sense amplifier means provided corresponding to the plurality of main bit line pairs, each for amplifying a potential difference appearing between the main bit lines of the corresponding main bit line pair. The corresponding two main bit line pairs of the bit line pairs correspond to the corresponding one of the plurality of sense amplifier means.
One of the two main bit line pairs is provided in correspondence with the plurality of sense amplifier means, and one of the two main bit line pairs is provided in response to a first block selection signal. A plurality of first transistor pairs for connecting to the sense amplifier means and a plurality of sense amplifier means are provided corresponding to the plurality of sense amplifier means, each of which is responsive to and corresponds to a second block selection signal.
A semiconductor device further comprising a plurality of second transistor pairs for connecting the other one of the two main bit line pairs to the one sense amplifier means in a complementary manner to one first transistor pair. Storage device. 7. A main memory cell block having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. A plurality of word lines connected to a plurality of memory cells arranged in a corresponding column, arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks, respectively. A plurality of sub bit line pairs connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub memory cell block; a plurality of main bit line pairs arranged in the plurality of rows; A plurality of lines are provided corresponding to the line pairs, each of which makes a corresponding sub-bit line pair and a main bit line pair of a row in which the sub-bit line pair is located conductive in response to a selection signal. Switching means pair And a plurality of sense amplifier means provided corresponding to the plurality of main bit line pairs, each for amplifying a potential difference appearing between the main bit lines of the corresponding main bit line pair. Half of the amplifier means form a first group, and the other half form a second group, and the sense amplifier means of the first group are arranged in every two rows and every two columns, and in the second group. The group of sense amplifier means is arranged every two rows and every two columns on a row and a column other than the row and the column where the first group of sense amplifier means is arranged. Storage device. 8. A main memory cell block having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. A plurality of word lines connected to a plurality of memory cells arranged in a corresponding column, arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks, respectively. A plurality of sub bit line pairs connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub memory cell block; a plurality of main bit line pairs arranged in the plurality of rows; A plurality of lines are provided corresponding to the line pairs, each of which makes a corresponding sub-bit line pair and a main bit line pair of a row in which the sub-bit line pair is located conductive in response to a selection signal. Switching means pair And a plurality of sense amplifier means provided corresponding to the plurality of main bit line pairs, each for amplifying a potential difference appearing between the main bit lines of the corresponding main bit line pair. The block further has a spare memory cell block having a plurality of spare memory cells arranged in a plurality of rows and a plurality of columns, and arranged in the plurality of columns, each of which is arranged in a corresponding column. A plurality of spare word lines connected to the spare memory cells, arranged in the plurality of rows corresponding to the spare memory cell blocks, and each connected to a plurality of spare memory cells arranged in the corresponding row. A plurality of spare sub-bit line pairs and the spare sub-bit line pairs are provided corresponding to the spare sub-bit line pairs, and each of the spare sub-bit line pair and the corresponding spare sub-bit line pair responds to a spare selection signal. A semiconductor memory device further comprising a plurality of pairs of auxiliary switching means for bringing a pair of main bit lines of a row located therein into a conductive state. 9. The number of the spare word lines intersecting with the corresponding one spare sub-bit line pair of the plurality of spare sub-bit line pairs is determined by the number of the corresponding one sub-bit of the plurality of sub-bit line pairs. The number of the spare memory cells connected to the one spare sub-bit line pair is equal to the number of the word lines intersecting the line pair, and the number of the memory cells connected to the one spare bit line pair is equal to the number of the spare memory cells. 9. The semiconductor memory device according to claim 8, wherein the semiconductor memory device is equal to 10. A plurality of main memory cell blocks each having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. A plurality of word lines arranged in the plurality of columns, each of which is connected to a plurality of memory cells arranged in a corresponding column, and arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks. A plurality of sub-bit line pairs, each of which is arranged and connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub-memory cell block; and a plurality of main bit lines arranged in the plurality of rows A pair provided corresponding to the sub-bit line pair, each of which makes a corresponding sub-bit line pair and a main bit line pair of a row in which the sub-bit line pair is located conductive in response to a selection signal. Multiple to do A pair of switching means, a plurality of sense amplifier means provided corresponding to the plurality of main bit line pairs, each for amplifying a potential difference appearing between the main bit lines of the corresponding main bit line pair, and each of , The corresponding two of the plurality of main bit line pairs
A semiconductor memory device comprising a plurality of comparing means for correspondingly comparing the potential of one main bit line pair of one main bit line pair and the potential of the other main bit line pair. 11. A main memory cell block having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns. A plurality of word lines connected to a plurality of memory cells arranged in a corresponding column, arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks, respectively. A plurality of sub bit line pairs connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub memory cell block; a plurality of main bit line pairs arranged in the plurality of rows; A plurality of lines are provided corresponding to the line pairs, each of which makes a corresponding sub-bit line pair and a main bit line pair of a row in which the sub-bit line pair is located conductive in response to a selection signal. Switching means A plurality of sense amplifier means provided corresponding to the plurality of main bit line pairs, each for amplifying a potential difference appearing between the main bit lines of the corresponding main bit line pair, and the plurality of sub-bits. A semiconductor memory device comprising: a plurality of dummy lines which are arranged between line pairs along a column direction and to which a predetermined potential is applied. 12. A main memory cell block having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of sub memory cell blocks obtained by dividing the plurality of columns into a plurality of columns, in the plurality of columns. A plurality of word lines connected to a plurality of memory cells arranged in a corresponding column, arranged in the plurality of rows corresponding to each of the plurality of sub memory cell blocks, respectively. A plurality of sub bit line pairs connected to a plurality of memory cells arranged in a corresponding row of a corresponding sub memory cell block; a plurality of main bit line pairs arranged in the plurality of rows; A plurality of lines are provided corresponding to the line pairs, each of which makes a corresponding sub-bit line pair and a main bit line pair of a row in which the sub-bit line pair is located conductive in response to a selection signal. Switching means A plurality of sense amplifier means provided corresponding to the plurality of main bit line pairs, each for amplifying a potential difference appearing between the main bit lines of the corresponding main bit line pair, and the plurality of sub-bits. A semiconductor memory device provided corresponding to a line pair, each including a plurality of sub-equalizing means for connecting one sub-bit line of the corresponding sub-bit line pair to the other sub-bit line. 13. A plurality of main equalizing means provided corresponding to the plurality of main bit line pairs, each for connecting one main bit line of the corresponding main bit line pair to the other main bit line. 13. The semiconductor memory device according to claim 12, further comprising: 14. The parasitic capacitance per unit length of the main bit line pair is ¼ of the parasitic capacitance per unit length of the sub bit line pair.
The semiconductor memory device according to any one of claims 5 to 13, characterized in that: