JPH0630390B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS semiconductor device, more specifically, an N-channel transistor (hereinafter abbreviated as NchTr.).
Of the CMOS type semiconductor device capable of alleviating the electric field concentration in the drain region and improving the punch-through breakdown voltage of a P-channel transistor (hereinafter abbreviated as PchTr.).

2. Description of the Related Art In recent years, for semiconductor devices, CMOS type semiconductor devices have been actively developed due to the demand for low power consumption. This CMOS
When miniaturizing a semiconductor device of the Nch Tr. Effect due to electric field concentration in the drain region of PchTr. Deterioration of the characteristics due to the short channel effect of the above becomes a problem. NchTr. In order to suppress the above hot carrier effect, there is a method of providing a low concentration diffusion at the gate side end of the source / drain diffusion layer, for example, a double diffusion drain structure has been proposed. In addition, PchTr. In order to improve the punch-through withstand voltage, there is a method of increasing the substrate impurity concentration or implanting phosphorus ions with high energy to form an n-type region having a relatively high concentration in a deep region under the gate insulating film. A CMOS structure combining these methods is shown in FIG. Here, a P-type well structure is shown. In the figure, 1 is an n-type substrate, 2 is a P-type well region, 3 is an element isolation region, 4 is a gate insulating film, and 5 is a polysilicon gate. Reference numeral 6 is an n-type region formed by deep implantation of phosphorus ions, which is formed only in the Pch region before forming the gate electrode. Further, 7 is a low concentration n-type diffusion layer, and 8 is a high concentration n-type diffusion layer. These low-concentration and high-concentration n-type diffusion layers 7 and 8 are formed by first implanting low-concentration phosphorus ions, performing drive-in, and then implanting high-concentration arsenic. However, in order to form this double diffused drain structure, in CMOS,
Since the mask process is required twice when forming the n-type diffusion layer 6 by deeper ion implantation, the process becomes complicated and there is a serious problem in practical use. Reference numeral 9 is a P-type diffusion layer made of boron.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the present invention, the NchTr. Of the PchTr. The present invention provides a method of manufacturing a CMOS type semiconductor device capable of suppressing the short channel effect.

Means for Solving the Problems According to the method of the present invention, a well region of opposite conductivity type is formed in a semiconductor substrate having one conductivity type, and a pair of polysilicon gate electrodes are formed in the semiconductor substrate and the well region. After the formation, phosphorus ions are self-alignedly implanted on the entire surface of the substrate to form an N-type diffusion layer, and then, arsenic or phosphorus is implanted on the N-channel side and boron is implanted on the P-channel side, overlapping the N-type diffusion layer. And a source / drain region having an impurity concentration higher than that of the N-type diffusion layer is formed.

Effect According to the manufacturing method of the present invention, the NchTr. Hot carrier effect and Pc
hTr. It is possible to obtain the CMOS type semiconductor device in which the characteristic deterioration due to the short channel effect is suppressed.

EXAMPLE Next, a method for manufacturing a CMOS type semiconductor device according to the present invention will be described with reference to the drawings of FIGS. Here, a case of a P-well type CMOS semiconductor device will be described as an example.

First, as shown in FIG. 1A, a P well 2 is formed in an n-type silicon substrate 1 by a normal technique, and an oxide film 3 for element isolation is formed.
Then, the gate oxide film 4 and the polysilicon gate 5 are formed. After that, phosphorus ions 10 are implanted over the entire surface of the substrate under the conditions of an acceleration energy of 80 KeV and an implantation dose of 5 × 10 ¹³ cm ^-2 . Then, 1000 ° C. in a nitrogen atmosphere,
Drive-in is performed for 10 minutes to form a low concentration n-type diffusion layer 7'by phosphorus diffusion as shown in FIG. 1b. The low-concentration n-type diffusion layer 7 ′ of phosphorus has a diffusion depth of about 0.7 μm.
Thereafter, as in the conventional case, as shown in FIG. 1c, arsenic or phosphorus ions are implanted into the high-concentration n-type diffusion layer 8 serving as the N-channel side source / drain, for example, arsenic is implanted at 40 KeV 4
By implanting under the condition of × 10 ¹⁵ cm ^-2 , and by implanting boron into the high-concentration P-type diffusion layer 9 serving as the P-channel side source / drain under the condition of implanting 3 × 10 ¹⁵ cm ^-2 at 25 KeV, The formation of the source / drain diffusion layer is completed. After that, by using a known technique, by forming an interlayer insulating film, opening a contact window, and forming an aluminum electrode wiring,
The CMOS semiconductor device is completed.

Although the method of the present invention described above is simpler in process than the conventional method described above, the NchT
r. With respect to the above, the withstand voltage of about 2V was improved and the generation of hot carriers could be suppressed as compared with the case of the source / drain structure in which the implantation of only arsenic was performed once. In addition, PchTr. Regarding the above, the short-channel effect was remarkable in the conventional source / drain structure by implanting only boron from the channel length of about 1.5 μm, whereas the one formed by the method of the present invention is , Channel length 1.
The short channel effect could be suppressed to about 2 μm.

EFFECTS OF THE INVENTION As described above, according to the method of the present invention, the process is simple and the NchTr. Hot carrier effect and PchTr. It is possible to suppress the characteristic deterioration due to the short channel effect, and it is possible to form a highly reliable fine CMOS type semiconductor device.

[Brief description of drawings]

1A to 1C are sectional views corresponding to the manufacturing process for explaining the manufacturing method of the present invention, and FIG. 2 is a sectional view of a CMOS semiconductor device formed by a conventional method. 1 ... Silicon substrate, 2 ... P well region, 3 ... Element isolation oxide film, 4 ... Gate oxide film, 5 ... Polysilicon gate, 6 ... N-type diffusion layer by deep implantation of phosphorus,
7, 7 '... low-concentration n-type diffusion layer, 8 ... high-concentration n-type diffusion layer, 9 ... high-concentration P-type diffusion layer, 10 ... phosphorus ion.

Claims (2)

[Claims] 1. A well region of opposite conductivity type is formed in a semiconductor substrate of one conductivity type, a pair of gate electrodes is formed in the semiconductor substrate and the well region, and the gate electrode is used as a mask. By implanting N-type impurity ions, an N-type diffusion layer is formed in advance in the portions to be the source / drain regions of the N-channel and P-channel, and then the N-type diffusion layer is formed.
The source having a higher impurity concentration in the type diffusion layer
A method of manufacturing a CMOS semiconductor device, comprising forming a drain region. 2. The CMOS according to claim 1, wherein the N-type impurity ions forming the N-type diffusion layer are phosphorus with an implantation amount of 1 × 10 ^{12 to} 5 × 10 ¹⁴ cm ^-2. Type semiconductor device manufacturing method.