JPH06290138A - Address bus control system - Google Patents

Abstract

PURPOSE:To minimize the generation of noises and also to shorten the access time to a memory by providing an address increment function on a device set at the address receiving side. CONSTITUTION:An address generating circuit 110 included in a device 100 set at the address transmitting side activates and outputs an increment state signal 111 if the address to be generated has a value equal to the value obtained by just increasing the precedent address by 1. An output buffer circuit 120 suppresses the address 112 generated by the circuit 110 and fixes an output address 121 of the transmitting side. Meanwhile, a device 200 set at the address receiving side latches an unincreased address by a register 211 and then increases the address to produce an internally generated address 214. Thus, an address 221 of the receiving side is acquired. As a result, an address bus can be set at a fixed level in an increment mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address bus control system for transmitting an address from an address transmitting side device to an address receiving side device via an address bus.

[0002]

2. Description of the Related Art In recent years, against the backdrop of advances in semiconductor technology,
The amount of memory in computer systems is also increasing. Along with this, the number of address lines in the address bus in the computer system tends to increase. In addition, machine cycles are being shortened.

[0003]

Therefore, in the address bus, since a large number of address lines change at high speed, the address bus becomes a noise source and causes various troubles. There is. In addition, speeding up the machine cycle leads to the problem that only a memory with a fast access time can be used.

In view of the above situation, an object of the present invention is to provide an address bus control system which can prevent the generation of noise as much as possible. A further object of the present invention is to provide an address bus control system that contributes to shortening the memory access time.

[0005]

According to the address bus control method of the present invention, in a computer system, it is often the case that a specific amount of data is continuously read from a specific address of a memory. Paying attention to the fact that the address value on the bus is in the increment state in which it increases by one during the corresponding period,
The above object is achieved by providing the address receiving side device with an address increment function. That is, the address bus control system according to the present invention is for transmitting an address from the address transmitting side device to the address receiving side device via the address bus, and has the following features. First, when the address to be output is a value that is incremented by 1 from the address in the previous cycle, the address transmitting side device suppresses the output of the address to the address bus and a signal indicating the suppression state. Is provided. Further, the address receiving side device increments the address of the previous cycle when detecting the inhibition state,
Means for internally generating an address.

[0006]

According to the above structure, the level of the address bus can be fixed to a constant level during the address increment. Further, during the address increment, since the address can be directly generated inside the address receiving side device, the address can be determined earlier than the address is obtained from the outside, and the access time of the memory or the like can be shortened in a pseudo manner.

[0007]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a schematic circuit diagram for explaining the configuration of an address bus control system according to an embodiment of the present invention. In the figure, an address generation circuit 110 in the address transmission side device 100 is a circuit for inputting the output of a CPU or the like and generating an address to be accessed. When the generated address is a value obtained by simply incrementing the previous address by 1, the circuit 110 makes the increment state signal 111 active (logical value 1) and outputs it. The output buffer circuit 120 in the address transmission side device 100 recognizes whether or not the increment is in progress by inputting the increment state signal 111. During the increment, the output buffer circuit 120 suppresses the generated address 112 from the address generation circuit 110, and sets the high (high) and the low (lo).
w) or fixing the address bus, that is, the transmission side output address 121 to a high impedance state. This makes it possible to completely suppress the generation of noise during the increment.

On the other hand, the address receiving side device 200 inputs the increment state signal 111, and in the normal state which is not the increment state, the selector 220 selects the value of the address bus 121 so that the receiving side input address. 221 is obtained. Further, in the increment state, the selector 220 causes the address internal generation circuit 210 to
By selecting the internally generated address 214 which is the output of, the receiving side input address 221 is obtained. The address internal generation circuit 210 is a circuit that latches the address before the increment state by the register 211 and increments it by using the incrementer 212 and the delay latch 213. Those skilled in the art can easily make the details of the above circuits and the timing design of the address receiving side device 200.

FIG. 2 is a time chart for explaining the address generation process according to the address bus control method of this embodiment. As shown in this figure, the output address on the transmission side becomes high impedance during the increment, but the increment signal becomes active at the same time. In response, the receiving side input address is
The external input from the bus is switched to the internal generation, and the value internally incremented is used. At the time of internal generation, the address can be determined earlier than at the time of external input, so that the access time seems to be faster as shown in the figure.

Although the embodiments of the present invention have been described above, the present invention is not of course limited thereto.
It is easy for a person skilled in the art to devise various embodiments. For example, the actual circuit design will vary widely.

[0012]

As described above, according to the present invention,
Provided is an address bus control method which can prevent generation of noise as much as possible and contributes to shortening of memory access time.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram for explaining a configuration of an address bus control system according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating an address generation process according to an address bus control method according to an exemplary embodiment of the present invention.

[Explanation of symbols]

 100 ... Address transmission side device 110 ... Address generation circuit 111 ... Increment state signal 112 ... Transmission side generation address 120 ... Output buffer circuit 121 ... Transmission side output address 200 ... Address reception side device 210 ... Address internal generation circuit 211 ... Register 212 ... Incrementer 213 ... Register 214 ... Internally generated address 220 ... Selector 221 ... Reception side input address

Claims (1)

[Claims] 1. An address bus control system for transmitting an address from an address transmitting side device to an address receiving side device via an address bus, wherein the address transmitting side device outputs an address of a previous cycle. When the value is incremented by one, the means for suppressing output of the address to the address bus and outputting a signal indicating the suppression state, the address receiving side device is An address bus control system comprising: means for internally generating an address by incrementing the address in the previous cycle when the above is detected.