JPH06139783A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] The resistance parasitic on the source is substantially reduced without expanding the wiring region to suppress the rise in the potential of the source line and improve the read / write efficiency. [Structure] Grounding transistors RTr ₁ to RTr _n connecting each bit line BL _{1 to} BL _n to the ground potential, and grounding transistors provided on odd-numbered bit lines BL ₁ and BL _{3 to} BL _n-1
Gates of RTr ₁ and RTr _{3 to} RTr _{n-1 have} means for inputting an inverted signal of an address signal for selecting bit lines BL ₁ and BL _{3 to} BL _n-1 of odd-numbered columns and an even-numbered bit line. BL ₂ , BL ₄
~ Grounding transistors RTr ₂ , RTr ₄ ~ R provided in BL _n
The gate of Tr _n has bit lines BL ₂ and BL ₄ of even-numbered columns
Means for inputting an inverted signal of an address signal for selecting BL _n .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention reduces the source resistance of a floating gate field effect transistor that stores information in a nonvolatile manner, prevents the source potential from rising when reading information, and ensures reliable reading of information. The present invention relates to a nonvolatile semiconductor memory device capable of writing.

[0002]

2. Description of the Related Art As a storage element for storing information in a non-volatile manner, a field effect transistor having a floating gate for holding a charge according to the information is generally used.

FIG. 1 shows a conventional memory cell array portion 1 disclosed in Japanese Patent Application No. 1-137496 and writing to it.
It is a circuit diagram which shows the structure of the circuit which reads. In FIG. 1, a memory cell array unit 1 includes a plurality of memory transistors MTr ₁₁ to MTr _1n , each of which is a field effect transistor having a floating gate for storing information in a nonvolatile manner.
..., MTr _m1 to MTr _mn are arranged in a matrix in m rows and n columns. Memory transistor MTr ₁₁ ~ in each row
The control gates of MTr _1n , ..., MTr _m1 to MTr _mn are supplied with corresponding control gate selection signals G _{1 to} G _m from the X decoder 3 through word lines WL _{1 to} WL _m .

On the other hand, the memory transistors MTr ₁₁ to M in each column
The drains of Tr _m1 , MTr ₁₂ to MTr _m2 , MTr _1n to MTr _mn are connected to the respective bit lines BL _{1 to} BL _n in each column, and the source of each memory transistor MTr ₁₁ to MTr _mn is common to each row. To the source lines S ₁ and S ₂ at both ends.

One end of each of the bit lines BL _{1 to} BL _n is connected to a circuit 6 such as a sense amplifier and an I / O buffer via one of the Y gate transistors Tr _{1 to} Tr _n of the Y gate section 2. , And the other end is a grounding transistor Tr ₁ ′, Tr ₂ ′ ...
It is grounded with a Tr _n ′ interposed. The Y decoders 4 to Y are provided to the gates of the Y gate transistors Tr _{1 to} Tr _n , respectively.
The gate selection signals Y _{1 to} Y _n are applied to the respective gates of the transistors for grounding Tr ₁ ′, Tr ₂ ′, ..., Tr _n ′ from the complementary signal generator 7 and the Y decoder 4 to the Y gate selection signal Y. ₁ inverted signal / Y ₁ which is a complementary signal of ~Y _n, / Y ₂
~ / Y _n are given respectively.

The Y decoder 4 responds to the internal column address signal input from the complementary signal generator 7 to generate Y gate selection signals Y _{1 to} Y _n and their inverted signals / Y ₁ to / Y _n , The Y gate selection signals Y ₁ and Y ₂ to Y _n are the inverted signals / Y ₁ to / Y of the Y gate transistors Tr _{1 to} Tr _n , respectively.
_n is applied to the gates of the grounding transistors Tr ₁ ′ to Tr _n ′. In the other figures, R indicates the resistance of the source diffusion region.

When one of the applied Y gate selection signals Y _{1 to} Y _n is at a high (H) level, one of the Y gate transistors Tr _{1 to} Tr _n becomes conductive,
One bit line BL _{1 to} BL _n is connected to the sense amplifier and I / O buffer 6 via the Y gate unit 2, and _{one of} the applied inverted signals / Y ₁ to / Y _n is at high level. In this case, one of the grounding transistors Tr ₁ ′ to Tr _n ′ becomes conductive, and each one bit line BL _{1 to} BL _n is grounded.

FIG. 2 is a block diagram showing the details of the Y decoder 4 and the complementary signal generator 7. The Y decoder 4 has a 3-input AND gate corresponding to the number of each bit line BL _{1 to} BL _n.
4a to 4n, each of which has an address signal A ₀ , A ₁ , A ₂ and an inverter 7 at its input end through a complementary signal generator 7.
One of the inverted signals / A ₀ , / A ₁ and / A ₂ is input via a, 7b and 7c, and each output terminal is connected to the Y gate section 2 of Y
Each of the gate transistors Tr _{1 to} Tr _n is connected to one gate. Each AND gate 4a~4n input address signals A _0, A _1, A ₂ and its inverted signal / A _0, / A
_1, so that the charge of the switch function for turning on and off the Y-gate transistors Tr ₁ to Tr _n based on the / A _2.

The operation of such a conventional nonvolatile semiconductor memory device will be described below. First, memory transistor MTr ₁₁
The operation of writing information into the memory transistor, that is, the case of injecting charges into the floating gate of the memory transistor MTr ₁₁ will be described. The X decoder 3 selects the word line WL ₁ in response to the external address signal, and writes the selected word line WL ₁ to the control gate selection signal G of the high voltage V _PP level.
Provide _one. As a result, all the memory transistors MTr ₁₁ to MTr _1n connected to the selected word line WL ₁ are turned on.

On the other hand, Y decoder 4 for selecting the bit lines BL ₁ to is connected to the memory transistor MTr ₁₁ selected, in response to the internal column address signals Y gate select signals Y ₁ to write high voltage V _PP 'Set to level. As a result, the Y gate transistor Tr ₁ is turned on, and the write high voltage V _PP ′ from the write circuit is selected to the selected bit line BL ₁
Given to. Incidentally, the address signal A _{0 of the} Y gate transistor Tr ₁ is low level, that is, the inverted address signal /
It is selected when A ₀ is high level, and is not selected in the opposite case.

On the other hand, simultaneously with this, the Y decoders 4 to Y
The inverted signals / Y ₁ to / Y _{n of the} gate selection signal are applied to the gates of the grounding transistors Tr ₁ ′ to Tr _n ′, respectively. For example, _assuming that the Y gate selection signal Y ₁ is at a high level and the other Y gate selection signals Y _{2 to} Y _n are at a low level, only the inversion signal / Y ₁ among these inversion signals / Y ₁ to / Y _n. It goes low and the other inversion signals / Y ₂ to / Y _{n go} high. Therefore, only the grounding transistor Tr ₁ ′ is turned off, the other grounding transistors Tr ₂ ′ to Tr _n ′ are turned on, and all the non-selected bit lines BL _{2 to} BL _n except the selected bit line BL ₁ are turned on. It becomes the ground potential.

[0012] As for the memory transistor MTr ₁₂ for example in this state, the control gate of the memory transistor MTr _12, that is, the word line WL ₁ control gate select signals G ₁ of the write high voltage V _PP level is applied, the memory transistors MTr ₁₂ is in the ON state, and the bit line BL ₂ is in the state of being connected to the source of the memory transistor MTr ₁₂ via the ON resistance.

As a result, the ground potential of the bit line BL ₂ is transmitted to the source of the memory transistor MTr ₁₂ , and regarding the memory transistor MTr ₁₁ , the two source lines consisting of the source line S ₁ and the bit line BL ₂ are the source. The state is almost the same as that provided for the region, and the source resistance of the memory transistor MTr ₁₁ is about 0.5R.

Similarly, the other memory transistors MTr ₁₃ ...
Source resistances of MTr _1n are all about 0.5R, and all memory transistors MTr connected to the same word line WL _1
Since the source resistances of _{11 to} MTr _1n are substantially the same and the source lines S ₁ and S ₂ are grounded, the floating of the source potential in each of the memory transistors MTr ₁₂ to MTr _1n is significantly reduced. .

As a result, even if the source lines S ₁ and S ₂ are provided every eight memory transistors, the source resistance of the memory transistors provided farther from the source lines S ₁ and S ₂ is higher. The phenomenon that the source potential floats does not occur, and the source resistance value of each memory transistor MTr ₁₂ to MTr _1n itself is reduced to a value lower than the conventional value and can be made uniform. MTr ₁₁ can be prevented variation in apparent threshold voltage of ~ MTr _1n, it is possible to perform accurate writing to each memory transistors MTr ₁₁ ~ MTr _1n.

Next, the case of reading data from the memory transistor will be described. Even in this case, a case where the read operation is performed on the memory transistor MTr ₁₁ will be described as an example. The read operation is the same as the conventional _one, and the control gate selection signal G ₁ at the power supply potential V _CC level is transmitted from the X decoder 3 to the selected word line WL ₁ .
Similarly, the Y gate selection signal Y from the Y decoder 4
₁ also becomes power supply potential V _CC level, and Y gate transistor
Tr ₁ turns on.

The grounding transistors Tr ₂ ′ to Tr _n ′ are turned on in response to the inverted signals / Y ₂ to / Y _n , and the unselected bit lines BL _{2 to} BL _n are connected to the ground potential. Further, the read potential is transmitted from the circuit of the sense amplifier and the input / output buffer I / O to the selected bit line BL ₁ .

Of the memory transistors MTr ₁₁ to MTr _1n connected to the word line WL ₁ , the memory transistor MTr
Information is not written to the memory transistor MTr ₁₃ among the memory transistors provided between the same source metal wirings as ₁₁ ; that is, no electric charge is accumulated in the floating gate and information “1” is stored. Consider the case.

The memory transistor MTr ₁₃ is a word line WL ₁
Control gate selection signal G ₁ (power supply potential V
_{Since the} read potential is applied to ( _CC level), it is turned on, and the ground potential of the bit line BL ₃ connected to this memory transistor MTr ₁₃ is transmitted to its source via the on resistance of the memory transistor MTr ₁₃ .

When the memory transistor MTr ₁₂ is in the off state, that is, stores the information “1”, the memory transistor MTr ₁₂
The source resistance of MTr ₁₁ is about 0.67R (the reciprocal of 1 / R + 1 / 2R), and even if source metal wirings (source lines S ₁ and S ₂ ) are provided every 8 memory transistors, the source will be the same. The resistance value can be significantly reduced.
As a result, floating of the source potential can be reduced, and accurate information can be read.

In the structure in which the source metal wiring is provided every eight memory transistors in general, it can be considered that there is almost no probability that all eight memory transistors are in the OFF state, that is, information "0" is stored. , In all memory transistor blocks, if at least one of the non-selected memory transistors is in a state where no information is written, that is, if there is a memory transistor storing information “0”, the source line is By being additionally provided, the source resistance is reduced and floating of the source potential of each memory transistor is reduced.

[0022]

By the way, in such a conventional device, the Y gate selection signals Y ₁ to
Since the inverted signals / Y ₁ to / Y _n are used in addition to Y _n , the wiring area is increased due to this and there is a difficulty in achieving high integration. The present invention has been made in view of such circumstances, and an object of the present invention is to prevent floating of the source potential and perform uniform reading or writing in all memory transistors, and further It is an object of the present invention to provide a nonvolatile semiconductor memory device that can be reduced.

[0023]

According to a first aspect of the present invention, a nonvolatile semiconductor memory device has a plurality of memory cells arranged in an array in a row direction and a column direction, and each memory cell has a drain in a bit line and a control gate in a memory cell. A non-volatile semiconductor device having a structure connected to a word line, wherein each of the plurality of memory cells includes a field effect semiconductor element capable of electrically performing both data writing and data erasing, wherein the bit line Means for connecting each to a ground potential, means for inputting an inverted signal of an address signal for selecting an odd-numbered column to the connection means provided in the bit lines of the odd-numbered column, and a means for inputting the even-numbered column Means for inputting an inverted signal of an address signal for selecting an even-numbered column to the connection means provided in the bit line.

In the non-volatile semiconductor memory device according to the second invention, a plurality of memory cells are arranged in an array in the row direction and the column direction, and in each memory cell, the drain is connected to a bit line and the control gate is connected to a word line. In the nonvolatile semiconductor device having a structure, each of the plurality of memory cells includes a field effect semiconductor element capable of electrically performing both data writing and data erasing, and connecting the bit line to each source line. Means for inputting an inverted signal of an address signal for selecting an odd-numbered column to the connection means provided on the bit line of the odd-numbered column, and means provided for the bit line of the even-numbered column Means for inputting an inverted signal of an address signal for selecting an even-numbered column to the connecting means.

[0025]

In the first aspect of the present invention, means for connecting the bit lines to the ground potential and means for connecting the address signals for selecting the odd-numbered columns to the connection means provided for the bit lines in the odd-numbered columns are provided. Since it has means for inputting an inverted signal and means for inputting an inverted signal of an address signal for selecting an even-numbered column to the connection means provided on the bit lines of an even-numbered column, a non-selected bit line The bit line in which the connecting means is in the operating state is at the ground level, and the parasitic resistance of the source line is substantially reduced.

In the second aspect of the present invention, means for connecting the bit lines to the source lines respectively and address signals for selecting the odd-numbered columns are connected to the connection means provided on the bit lines in the odd-numbered columns. The selected word line includes means for inputting an inverted signal and means for inputting an inverted signal of an address signal for selecting an even-numbered column to the connection means provided on the bit lines of the even-numbered column. In addition to the non-selected memory cell connected to the memory cell, the connection means also operates so that the bit line and the source line have the same potential by the operation thereof, and the parasitic resistance of the source line is further reduced to select the selected memory cell. Therefore, the rise in the source potential of is suppressed.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. (Embodiment 1) FIG. 3 is a block diagram showing a nonvolatile semiconductor memory device according to the present invention, in which 1 is a memory cell array, 2 is a Y gate section, 3 is a decoder, 4 is a Y decoder,
Reference numeral 6 indicates a circuit including a sense amplifier, an I / O buffer and the like. The configurations of the memory cell array 1 and the Y gate portion 2 are shown in FIG.
Substantially the same as that of the conventional device shown in FIG.

The memory cell array 1 includes memory transistors MTr ₁₁ to MTr which are field effect transistors having a floating gate for storing information in a nonvolatile manner.
r _1n, ..., which are arranged to MTr _m1 ~ MTr _mn in a matrix of m rows and n columns. The memory transistors MTr ₁₁ to MTr _1n , ..., MTr _m1 to MTr _mn in each row are connected to the control gates of the X decoder 3 via word lines WL _{1 to} WL _m.
From the corresponding control gate selection signals G _{1 to} G _m .

On the other hand, the memory transistor MTr _{11 for} each column
~ MTr _m1 , ... MTr ₁₂ ~ MTr _m2 , MTr _1n ~ MTr _mn drains are commonly connected to bit lines BL ₁ ~ BL _n for each column,
The sources of the memory transistors MTr ₁₁ to MTr _mn in each row are commonly connected to n sources, and both ends of the common line are connected to the source lines S ₁ and S ₂ .

One end of each of the bit lines BL _{1 to} BL _n is shown via a circuit 6 such as a sense amplifier and an I / O buffer with one of the Y gate transistors Tr _{1 to} Tr _n of the Y gate section 2 interposed. Not connected to the circuit, and the other end is a bit line reset transistor RTr ₁ , RTr ₂ ... RTr _n each one constituting a bit line reset transistor RTr ₁ to RTr
It is grounded with _n interposed. Y gate transistor
Each of the gates of Tr _{1 to} Tr _n has the same Y as shown in FIG.
The Y gate selection signals Y _{1 to} Y _n are applied through the decoder 4 and the complementary signal generator 7, respectively.

On the other hand, a bit line resetting transistor R
Tr ₁ , RTr ₂ ... RTr _n each gate has an odd number of bit lines BL
_The address signal A ₀ is directly applied to the gates of the bit line reset transistors RTr ₁ , RTr ₃ ... Connected to ₁ , BL ₃ ... BL _n-1 and the bit lines BL ₂ , BL ₄ ... BL _{n of} even columns. Bit line reset transistor RT connected to
The address signal A is supplied to r ₂ , RTr ₄ ...
Complementary signal (inverted signal) / A _{0 0} is adapted to be respectively applied.

Next, the operation of such a nonvolatile semiconductor memory device according to the present invention will be described. If now writing information, for example, in the memory transistor MTr _11, i.e. the operation for injecting charges into the floating gate of the memory transistor MTr ₁₁ will be described.

The X-decoder 3 selects the word line WL ₁ in response to the external address signal, and writes the selected word line WL ₁ to the control gate selection signal G _{1 of the} high voltage V _PP level.
give. As a result, all the memory transistors MTr ₁₁ to MTr _1n connected to the selected word line WL ₁ are turned on.

On the other hand, Y decoder 4 for selecting the bit lines BL ₁ connected to the memory transistor MTr ₁₁ selected, in response to the internal column address signals Y gate select signals Y ₁ to write high voltage V _PP 'Set to level. As a result, the Y gate transistor Tr ₁ is turned on, and the write high voltage V _PP ′ from the write circuit is selected to the selected bit line BL ₁
Given to.

A Y gate transistor connected to the bit line BL ₁ in the memory cell array 1 in the Y gate section 2
Since it is clear from FIG. 2 that the Tr ₁ is turned on when the complementary signals (inverted signals) / A ₀ , / A ₁ and / A ₂ are set to the high level, the bit line BL ₁ odd column of the bit lines BL _1, BL ₃ ... each bit line reset transistor is connected to RTr ₁ containing, RTr ₃ ... address signal a ₀ of the low level is applied to the even rows of the bit lines BL
Bit line reset transistor R connected to _2, BL ₄ …
A high-level complementary signal (inverted signal) / A ₀ is applied to each gate of Tr ₂ , RTr _4, ...

That is, the reset transistors RTr ₁ and RTr connected to the odd-numbered columns of the bit lines BL _{1 to} BL _n.
A low-level address signal A _0, which is a column selection signal that does not select the odd-numbered bit lines BL ₁ and BL ₃ , is input to the gates of ₃ ... Therefore, the reset transistors RTr ₁ , RTr ₃ ... Connected to the odd-numbered bit lines BL ₁ , BL ₃ ... Are turned off, and the reset transistors RTr ₁ , RTr ₃ ... For the even-numbered bit lines BL ₂ , BL ₄ ... The transistors RTr ₂ , RTr ₄ ... Are turned on, and the bit lines BL ₂ , BL ₄ ... In even columns are all set to the ground potential.

In this state, the memory transistor MTr
₁₂ , the control gate of the memory transistor MTr ₁₂ is programmed with high voltage V via the word line WL _{1.
The PP} level control gate selection signal G ₁ is applied, the memory transistor MTr ₁₂ is turned on, and the bit line BL ₂ is connected to its source via the on resistance of the memory transistor MTr _12. There is.

As a result, the ground potential of the bit line BL ₂ is transmitted to the source of the memory transistor MTr ₁₂ , and regarding the memory transistor MTr ₁₁ , the source line S ₁ and the bit line BL ₂ are transmitted.
The _two source lines of BL ₂ are almost the same as those provided for the source region, and the memory transistor
Source resistance of MTr ₁₁ drops.

[0039] Similarly, reduced all the word lines WL ₁ other even-numbered memory transistor connected to MTr _12, MTr ₁₄ ... also source resistance, the memory transistor MTr ₁₁ connected to the same word line WL _1, Since the source resistances of MTr ₁₃ ... Are the same and the source lines S ₁ and S ₂ are grounded, floating of the source potential in each of the memory transistors MTr ₁₁ , MTr ₁₃ ... Is significantly reduced.

On the contrary, when the memory transistor MTr ₁₂ or the like is selected, the bit line reset transistor RTr connected to the even-numbered column of the bit lines BL _{1 to} BL _n.
The low-level address signal / A ₀ , which is a column selection signal that does not select an even number, is input to the gates of ₂ , RTr _4, ...

Next, the case of reading data will be described. Even in this case, a case where the read operation is performed on the memory transistor MTr ₁₁ will be described as an example. The read operation itself is the same as the conventional _{one, the} word line WL ₁ is selected by the output from the X decoder 3, and the selected word line WL ₁ is selected.
A control gate selection signal G ₁ of power supply potential V _CC level is applied onto WL ₁ , and the read potential from circuit 6 such as a sense amplifier and an I / O buffer is transmitted to selected bit line BL ₁ .

Similarly, the Y gate selection signal Y ₁ from the Y decoder 4 becomes the power supply potential V _CC level and the other Y gate selection signals Y _{2 to} Y _n become the low level, so that the Y gate transistor
Tr ₁ turns on. Further, among the bit line reset transistors RTr ₁ to RTr _n , the bit lines BL ₁ and B of the odd-numbered columns including the selected bit line reset transistor RTr ₁
Bit line reset transistor RT connected to L ₃ …
r ₁ , RTr ₃ ... are low-level and even column bit lines BL
Bit line reset transistor R connected to _2, BL ₄ ...
A high level complementary signal / A ₀ is applied to the gates of Tr ₂ , RTr ₄ ... And the bit lines BL ₂ , BL ₄ ... Are connected to the ground potential.

As a result, the source resistance of the memory transistor MTr ₁₁ is greatly reduced, the floating of the source potential can be reduced, and accurate information reading can be performed.

(Embodiment 2) FIG. 4 is a block diagram showing another embodiment of the present invention, in which 1 is a memory cell array and 2 is a block diagram.
Indicates a Y gate portion, and 9 indicates a grounding transistor group. Memory cell array 1 has two memory transistors each
_{MTr 11, MTr 11 '~ MTr} 1n, MTr 1n' and the number of memory cells (drawing 2 transistor 1 cell structure control gate transistor (not shown) which constitute one memory cell as a set memory cell MS ₁₁ ~ MS _1n only)
The memory cells are arranged in a matrix of rows and n columns, and are provided with a short circuit transistor group 11 for short-circuiting the bit lines BL _{1 to} BL _n and the source line S. Each of the two transistors that make up the control gate is connected to the word line WL via a control gate transistor (not shown), and the drain is connected to the bit line BL.
_{1 to} BL _n , and the source is connected to the source line S. Control gate selection signals G _{1 to} G _m are applied to each word line WL through the X decoder 3.

One end of each of the bit lines BL _{1 to} BL _n is a Y gate transistor (not shown) of the Y gate section 2 as in the first embodiment shown in FIG. 3, and the other end is a short-circuit transistor STr ₁
~ STr One short circuit transistor STr that constitutes _n group 11
₁ to STr _n and a bit line reset transistor (not shown) similar to that shown in FIG. As in the conventional device shown in FIG. 2, each Y gate transistor of the Y gate unit 2 is supplied with a Y signal through a complementary signal generator 7 and a Y decoder 4.
The gate selection signals Y ₁ to Y _n are supplied.

The drains of the short-circuiting transistors STr ₁ to STr _n are connected to the bit lines BL _{1 to} BL _n , respectively, and the sources are connected to the source line S via a common line. Then, among the short-circuit transistors STr ₁ to STr _n , the odd-numbered bit line BL
₁ , BL ₃ … BL _n-1 shorting transistor
Address signal A ₀ is applied to the gate of STr ₁ , STr ₃ ... STr _n-1.
However, the gate of the shorting transistors STr ₂ , STr ₄ ... STr _n connected to the even-numbered bit lines BL ₂ , BL ₄ ... BL _n has an inverter 10 interposed at the gate of the complementary signal / A of the address signal A _0. A ₀ is input.

Next, the operation of such a device of the present invention will be described. A case of writing to the memory transistor MS ₁₁ which is now connected to the bit line BL ₁ will be described. Memory transistors MTr ₁₁ , MTr ₁₁ ′ to MTr whose write high voltage is applied to the word line WL and whose gate is connected to the word line WL.
_1n, it is turned on to MTr _1n ', also Y gate select signals Y ₁ output from the Y decoder 4 so as to select the the bit lines BL ₁
Is set to a high level and the other Y gate selection signals Y _{2 to} Y _n are set to a low level, but the Y gate selection signal Y ₁ is set to a high level, as is apparent from FIG. 2, which are complementary signals / A ₀ and / A. ₁ , /
This is the case where A ₂ is at a high level, which causes the short-circuit transistors STr ₁ , STr ₃ connected to the odd-numbered bit lines BL ₁ , BL ₃ ... Of the short-circuit transistors STr ₁ to STr _n. Is a low-level address signal A ₀
But also to an even-numbered bit lines BL _2, BL ₄ for short ... in connected transistors STr _2, STr ₄ ... complementary signal / A ₀ high level is applied, shorting transistor STr _1,
STr ₃ … is in OFF state, short circuit transistor STr ₂ , STr ₄
... is turned on.

Similarly, in the bit line reset signal transistor group, the bit line reset transistors connected to the odd-numbered bit lines BL ₁ , BL ₃ ... Are in the off state, and the even-numbered bit lines BL ₂ , BL ₄ ... The bit line reset transistor connected to is turned on. Therefore, the even-numbered bit line reset transistors are short-circuited to the source line S via the short-circuit transistors STr ₂ , STr _4, ... And are respectively connected to the ground potential via the bit line reset transistors. As a result, the conductance between each odd-numbered bit line BL ₁ , BL ₃ ... And the source line S is reduced, and the parasitic resistance between the source of the memory cell and the ground level is also reduced.

The reading process is substantially the same as that of the first embodiment, and the description thereof is omitted. This Example 2
In this case, the memory cell and the short-circuit transistor connected to the non-selected bit line connected to the selected word line WL operate so that the bit line and the source line have the same potential, and the source line S The parasitic resistance of
The increase in the source potential of the selected memory cell will be reduced.

[0050]

As described above, in the first aspect of the present invention, the odd-numbered columns are selected as the means for connecting each bit line to the ground potential and the connecting means provided for the odd-numbered column bit lines. Means for inputting the inverted signal of the address signal for inputting the inverted signal of the address signal for selecting the even-numbered column to the connection means provided in the bit lines of the even-numbered column The bit line of which the connecting means is operating is at the ground level, the parasitic resistance of the source line is substantially reduced, and the write / read function is improved.

In the second aspect of the invention, the means for connecting each bit line to the source line and the connection means provided for the bit lines in the odd-numbered columns are connected to the address signals for selecting the odd-numbered columns. Since a means for inputting an inverted signal and a means for inputting an inverted signal of an address signal for selecting an even-numbered column to a connection means provided in the bit lines of an even-numbered column are provided, Not only the non-selected memory cells connected but also each connecting means functions so that the bit line and the source line have the same potential, the parasitic resistance of the source line is reduced, and the write / read function is improved.

[Brief description of drawings]

FIG. 1 is a flowchart showing a schematic view of a conventional device.

FIG. 2 is an enlarged plan view of a main part of a conventional device.

FIG. 3 is a schematic diagram of a nonvolatile semiconductor memory device according to the present invention.

FIG. 4 is a schematic view showing another embodiment of the present invention.

[Explanation of symbols]

 1 memory cell array 2 Y gate section 3 X decoder 4 Y decoder 6 circuits such as sense amplifier and I / O buffer 7 complementary signal generator 8 inverter 9 bit line reset transistor group 10 inverter

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[Procedure amendment]

[Submission date] February 8, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

[0021] Oite to the configuration source metal wiring in the normal memory transistor 8 every other are provided, at least one of the non-selected note <br/> Li transistor, a state in which information is not written, i.e. information If there is a memory transistor that stores "0", the source line is additionally provided to reduce the source resistance and the floating of the source potential of each memory transistor.

Front Page Continuation (72) Inventor Tomoji Futani 4-chome, Mizuhara, Itami City, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Laboratory (72) Shinichi Kobayashi 4-chome, Mizuhara Itami City, Hyogo Prefecture Mitsubishi Electric Corporation LSI Research Center

Claims (2)

[Claims] 1. A plurality of memory cells are arranged in an array in a row direction and a column direction, and the drain of each memory cell is a bit line,
In a nonvolatile semiconductor device having a structure in which a control gate is connected to a word line, each of the plurality of memory cells includes a field effect semiconductor element capable of electrically performing both data writing and data erasing, Means for connecting each of the bit lines to a ground potential; means for inputting an inversion signal of an address signal for selecting an odd-numbered column to the connection means provided in the bit line of the odd-numbered column; Means for inputting an inverted signal of an address signal for selecting an even-numbered column to the connection means provided in the bit line of the column. 2. A plurality of memory cells are arranged in an array in a row direction and a column direction, and the drain of each memory cell is a bit line,
In a nonvolatile semiconductor device having a structure in which a control gate is connected to a word line, each of the plurality of memory cells includes a field effect semiconductor element capable of electrically performing both data writing and data erasing, Means for connecting each of the bit lines to a source line; means for inputting an inversion signal of an address signal for selecting an odd-numbered column to the connection means provided in the bit line of the odd-numbered column; Means for inputting an inverted signal of an address signal for selecting an even-numbered column to the connection means provided in the bit line of the column.