JPH05197743A - Vector processor - Google Patents

Abstract

(57) [Summary] [Objective] To provide a vector processor capable of processing a plurality of different vector processor architectures. [Structure] Main memory 1, main memory control unit 2, scalar processing unit 4 for processing scalar instructions belonging to different instruction set architectures, scalar processing unit 5, and vector processing unit 3 shared by these scalar processing units. .. The vector processing unit 3 selectively processes vector processing requests from a plurality of scalar processing units. The vector processing unit state register 100 indicates which instruction set architecture is involved in the vector instruction, and the vector processing unit state changing unit 101 selects a request from the request from the scalar processing unit and the state of the vector processing unit. To do. [Effect] A vector processor system capable of processing a plurality of different vector processor architectures can be constructed with a small amount of hardware.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processor type supercomputer for scientific and technological calculation, which comprises a scalar processing unit for processing scalar instructions and a vector processing unit for processing vector instructions. The present invention relates to a system capable of executing a program written with a different instruction set architecture or a compiled load module.

[0002]

2. Description of the Related Art For the purpose of high speed processing of scientific and technological calculations,
A vector processor type super computer is used. Typical vector processors include CRAY-1 from Cray Research, Inc. and VP- from Fujitsu Limited.
200, Fujitsu VP-2000 series, Hitachi S-810, Hitachi S-820, and the like. Technologies related to these supercomputers are described in the following documents.

Clay Research's technology is described in US Pat.
128880.

Hitachi technology is described in US Pat. No. 4,541,
No. 046 and No. 4,617,625, and Nikkei Electronics December 28, 1987 page 111-1
25, "Single processor with maximum performance of 2 GFLOP
S's S-820 ".

The above-described vector processor instruction set architecture, that is, an instruction set consisting of a scalar instruction and a vector instruction, a register configuration, an I / O instruction,
In the logical structure of the computer specified by interrupt, etc.,
Scalar instructions provided in general-purpose computers and vector instructions that can process the computations between arrays frequently occurring in scientific and engineering computations at high speed are defined. The vector processor includes a scalar processing unit (hereinafter abbreviated as SPU) that processes a scalar instruction and a vector processing unit (hereinafter abbreviated as VPU) that processes a vector instruction.

The SPU and the VPU cooperate to process one program at high speed, but the instruction read by the SPU and the VPU are roughly classified into the following two types.

(1) In a mixed scalar instruction / vector instruction architecture, the SPU reads not only scalar instructions but also vector instructions. When the read instruction is a vector instruction, the vector instruction is sent to the VPU and executed by the VPU. The above-mentioned CRAY-1 or VP-200, VP-2000 series of Fujitsu Limited is a vector processor of this type.

(2) In the scalar instruction / vector instruction separation type architecture, the VPU is activated when the SPU reads and decodes the instruction for activating the vector processing. This type of vector processor is based on Hitachi's S-8
01, S-820 is a vector processor of this type. Instruction to activate VPU in SPU (S-81
In case of 0 or S-820, Execute Vector Processing
When an instruction (abbreviated as EXVP instruction) is decoded, information including the location of the vector instruction sequence designated as the operand of the instruction and the vector processing start signal are transmitted together with the V information.
Sent to PU. The activated VPU reads the vector instruction from the main memory or the buffer memory and executes it according to the activation information. When a series of vector processing is completed, the SPU is notified of that fact.

In the conventional super computer system, only one instruction set architecture is supported, and only a program written or a compiled program can be processed on the basis of the supported instruction set architecture.

[0010]

Among the programs executed by the supercomputer, there are distributed software used by many users, such as a library for structural calculation, which occupies an important position. Many of these programs are made assuming the instruction set architecture of a specific vector processor, and some are provided in the form of load modules written in machine language.

When a user who uses a supercomputer intends to use the software in distribution software, if the software is a program written assuming an instruction set architecture different from that of the supercomputer possessed by the user, You can't use it. Even if a program provided in the form of a FORTRAN language source program optimized for a certain supercomputer instruction set architecture is executed in a supercomputer having another instruction set architecture, high performance cannot be expected. This situation frequently arises as different types of supercomputers become popular and different software is developed on each machine. In addition, supercomputers will be developed in succession and successor models in line with the progress of hardware technology, but new technologies that were not known at the time of development of conventional models were incorporated into successor models, The architecture compatibility may be broken. In such a case, the software developed on the conventional model may not be executed on the succeeding model.

From the standpoint of respecting the instruction set architecture of the conventional model and the succeeding model or the user's software heritage, a plurality of instruction set architectures are provided.
The following methods are conceivable for processing by one system.

That is, a system capable of processing different architectures can be constructed by preparing respective vector processors capable of processing the respective architectures and making them tightly coupled via, for example, the main memory. For this tightly coupled technique via the main memory, a generally used multiprocessor configuration technique may be used.

However, with this method, the scale of the system becomes enormous, resulting in a system configuration with poor feasibility.
Actually, it has not been realized so far. As described above, the conventional vector processor can process only software written assuming the instruction set architecture peculiar to the processor, and the programs developed assuming the different instruction set architecture and the new vector processor can be processed. There was a problem that programs developed on conventional models could not be executed well because the architecture was not compatible with the model.

In order to solve such a problem, an object of the present invention is to provide a vector processor type supercomputer which supports a plurality of different instruction set architectures and to provide two processors which support each instruction set architecture. This is to be realized with a significantly smaller device scale.

Another object of the present invention is to provide a system capable of processing various software made assuming different vector architectures by one system.

Another object of the present invention is to provide a system having a large device scale and having a number of vector processors less than the number of supported architectures.

[0018]

In general, the number of SPU elements is considerably smaller than the number of VPU device elements. Also, in vector processing, the utilization rate of VPU is not necessarily high. With this in mind, for example, a configuration method of a dual scalar vector processor as disclosed in Japanese Patent Laid-Open No. 61-131169 has been devised. this is,
For example, when configuring a vector processor, two SPs
U shares one VPU, the VPU selectively accepts vector processing instructions from two SPUs, and attempts to multiplex two programs. Here, the two SPUs only handle the same instruction set architecture.

In the present invention, attention is focused on the following two points: (a) the device scale of the SPU is considerably smaller than that of the VPU, and (b) the VPU operation rate is not high in vector processing. In order to achieve the above-mentioned object, at least two SPUs each having the following functions
And a vector processor consisting of at least one VPU is constructed. That is, corresponding to each of the different instruction set architectures that it supports, a plurality of SPUs that process scalar instructions in those instruction set architectures, and an SPU shared by these SPUs.
Prepare a smaller number of VPUs than PUs. The VPU has the ability to handle various vector instructions belonging to different instruction set architectures.

[0020]

In a vector processor having such an SPU and a VPU, the VPU selectively accepts the vector process execution instruction or the vector command sent from a plurality of different SPUs sharing the VPU and executes the vector process. To do. That is, the VPU can function as a VPU related to the instruction set architecture according to the instruction from the SPU related to the instruction set architecture, and at the same time, to the instruction set architecture according to the instruction from the SPU related to the other instruction set architecture. It is possible to function as a VPU. The processing of one program is composed of a scalar processing for executing a scalar instruction in the SPU and a vector processing for executing a vector instruction in the VPU. In other words, it is not possible to continue using the VPU when the program is executed from the beginning to the end. Therefore, even if the VPU is shared by different SPUs, the performance is not degraded so much.

As described above, in the vector processor of the present invention, it is possible to support a plurality of different instruction set architectures with a smaller amount of hardware without preparing a pair of SPU and VPU corresponding to each instruction set architecture. Will be possible.

[0022]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 1 is a system configuration diagram of a vector processor type supercomputer which is an embodiment of the present invention. In this embodiment, a vector architecture (hereinafter, referred to as vector architecture A) that is type-classified into a scalar instruction / vector instruction separation type instruction set architecture and a vector architecture that is a scalar instruction / vector instruction mixed type instruction set architecture (hereinafter, vector architecture A) ,
A system capable of handling two instruction set architectures (referred to as vector architecture B) is shown. Here, the specifications of the scalar instruction and the vector instruction may be completely different between the vector architecture A and the vector architecture B.

The system of this embodiment comprises a main memory 1, a main memory controller 2, a vector processing unit (VPU) 3, and two scalar processing units 4 and 5. Less than,
The scalar processing unit 4 will be called SPU-A, and the scalar processing unit 5 will be called SPU-B. Main memory control unit 2
Is a scalar processing unit (SPU-A) 4, a scalar processing unit (SPU-B) 5, a vector processing unit (V
It has a function of controlling data transfer between the PU) 3 and the main memory 1.

A program written on the premise of architecture A (referred to as program a) and a program written on the premise of architecture B (referred to as program b) are stored in main memory 1.

The program a is composed of a scalar instruction sequence and a vector instruction sequence configured as a separate instruction sequence. Of these, the scalar instruction sequence is read from the main memory 1 by the scalar processing unit (SPU-A) 4 and processed there. The vector instruction sequence is read from the main memory 1 by the vector processing unit (VPU) 3 and processed there.

The program b is composed of an instruction string including a mixture of scalar instructions and vector instructions. The instruction of this instruction sequence is stored in the main processing unit 1 by the scalar processing unit (SPU-B) 5
, The scalar instruction of which is processed by the scalar processing unit (SPU-B) 5, and the vector instruction is processed by the vector processing unit (VPU) 3.

In this system, the program a and the program b may be processed sequentially or in parallel.

The instructions of the program a in the main memory are read out by the scalar processing unit (SPU-A) 4 and the vector processing unit (VPU) 3 and executed.

The instructions of the program b are read by the scalar processing unit (SPU-B) 5 and executed.

Since the scalar processing unit (SPU-A) 4 and the scalar processing unit (SPU-B) 5 can operate independently at the same time, the programs a and b may be processed at the same time.

The scalar processing unit (SPU-A) 4 is connected to the main memory control unit 2 by a signal line 201, and the main memory 1
Exchange commands and data with. Similarly, the scalar processing unit (SPU-B) 5 is connected to the main memory control unit 2 by a signal line 202 and exchanges instructions and data with the main memory 1. In this embodiment, the vector architecture A is a scalar processing unit (SPU-A).
4 and vector processing unit (VPU) 3, and vector architecture B is a scalar processing unit (SPU-
B) 5 and a vector processing unit (VPU) 3 are used.

The vector processing unit (VPU) 3 has a vector instruction control unit (VIU) 10 and a vector instruction execution unit (VEU) 20. Vector instruction execution unit (VE
U) 20 is a vector register group (VR group) 21, an addition pipe 22, a multiplication pipe 23, a load / store pipe 2
4,25. On the other hand, the vector command controller (VI
The U) 10 has a function of decoding a vector instruction and giving a necessary signal to the vector instruction execution unit (VEU) 20 to start execution of the instruction. This vector instruction execution unit 20
Both vector instructions belonging to vector architecture A and vector instructions B can be processed.

The scalar processing unit (SPU-) shown in FIG.
A) 4 has a function of processing a scalar instruction such as a vector process start instruction called an EXVP instruction peculiar to the vector architecture A, in addition to a normal general-purpose scalar operation function.

Specifically, this unit has an instruction fetch circuit 40, a cache 41, an arithmetic unit group 42, a register group 49, an instruction register 43, and an instruction decoding unit 44.

The instruction fetch circuit 40 stores the scalar instruction sequence contained in the program a from the main memory 1 into the cache 41.
Are sequentially fetched via the, and set in the instruction register 43.

The decoder 44 decodes the instruction set in the instruction register 53, and when the instruction is a normal scalar operation instruction, supplies a signal necessary for its execution to the cache 41, the operation unit group 42, and the register group 49. And execute the command. The decoded instruction is a vector processing start instruction (EX
VP command), the decoder 44 uses the signal line 47
The vector processing start signal is output to.

In FIG. 2, reference numeral 46 denotes an activation information generation unit which, when a vector processing activation signal is supplied to the line 47 from the decoder 44, (a) the start address of the vector instruction sequence included in the program a, and ( b) Vector activation information such as the vector length of the vector data to be processed by the instruction sequence is generated based on the content specified by the vector processing activation instruction EXVP and placed on the signal line 48.

Thus, the vector processing start signal and the vector processing start information output to the signal lines 47 and 48 are sent to the vector processing unit VPU3.

In the vector instruction control unit 10, the register 104 fetches the vector activation information sent by the signal line 48 in response to the timing signal 221 supplied from the state control circuit 101, and the vector via the line 222. It is supplied to the instruction fetch circuit 105. The state control circuit 101 is adapted to generate this timing signal in response to a vector processing start signal on the signal line 47, as will be described later in detail. Furthermore, this circuit 10
In response to the vector start signal on the signal line 47, 1 sets information indicating the state A for processing the vector instruction of architecture A in the state register 100. Selector 106
Is the output 2 of the vector instruction fetch circuit 105 when the state information sent from the line 224 indicates the state A.
23 will be selected. The vector instruction fetch circuit 105 reads the vector instructions from the main memory 1 one after another according to the start address of the vector instruction sequence to be read from the vector processing start information sent from the register 104 via the line 222, and stores them in the vector instruction register 102. set. The vector instruction decoding feasibility determination unit 103
Decoded the vector instruction in the instruction register 102 and checked whether the pipe required by the instruction in the pipes 22 to 25 or the vector register required by the instruction in the vector register group 21 is available. Later, when these resources are available, the decoding information of the instruction is transmitted to the vector instruction execution unit (VEU) 20, and the vector instruction execution unit (VEU) 20 executes this instruction. In this way, the vector instruction sequence designated by the vector activation instruction EXVP is executed. Information such as the vector length of the vector activation information set in the register 104 is sent to the vector instruction execution unit (VEU) 20 via a line (not shown) prior to the execution of this instruction sequence. Used when executing the column.

This instruction sequence includes an instruction called VEND indicating the end of vector processing. This instruction is a scalar instruction. If this instruction is read,
The vector instruction decoding executability determining unit 103 instructs the vector instruction fetch circuit 105 to stop reading the vector instruction, and the state changing unit 101 makes the state of the vector processing unit state holding unit 100 inactive.

Further details of the operation of each element described above can be found in US Pat. Nos. 4,541,046 and 4,617,625.
No.

The scalar processing unit 5 (SPU shown in FIG. 3)
-B) includes an instruction fetch circuit 50, a cache 51,
There are an arithmetic unit group 52, a register group 59, an instruction register 53, and an instruction decoding unit 54.

The instruction fetch circuit 50 sequentially fetches an instruction string including a scalar instruction and a vector instruction belonging to the program b from the main memory 1 via the cache 51 and sets them in the instruction register 53.

The instruction set in the instruction register 53 is
When the instruction is a normal scalar operation instruction, the instruction is processed by the same operation as shown in FIG.

When the instruction set in the instruction register 53 is a vector instruction, the decoder 54 uses the signal line 5
The vector instruction activation signal is supplied to 7, and the instruction itself (or the information obtained as a result of decoding the instruction)
Is supplied to the AND gate 56. This vector command activation signal opens the AND gate 56 and transfers the vector command to the signal line 58. The vector instruction activation signal on signal line 57 and the instruction on signal line 58 are sent to VIU 10.

In the VIU 10, the state changing unit 101 responds to the vector instruction activation signal on the signal line 57 in response to the vector instruction activation signal on the signal line 57, and outputs information indicating the state b for processing the vector architecture B at an appropriate timing. Status register 1
Set to 00. As a result, the selector 106 will select the output line 58 of the scalar processing unit 5 when the signal 224 from the state register 100 indicates the state b.

Therefore, the command output to the signal line 58 is
It is taken into the register 102 via the selector 106. The vector instruction decoding feasibility determination unit 103
After deciphering this instruction and checking whether the arithmetic pipe and vector register required by this instruction are available, the decipherment information of the instruction is used as the vector instruction execution unit (VE).
U) Tell 20. Vector instruction execution unit (VEU) 20
Executes the instruction according to the decoding information of the instruction.

Further details of the operation of the circuit elements described above are set forth in US Pat. No. 4,128,880.

Next, the scalar processing unit 4 (SPU-
A) or a method of processing vector instructions belonging to different vector architectures in the vector processing unit 3 (VPU) according to an instruction from the scalar processing unit 5 (SPU-B) will be described.

The vector instruction control unit 10 (VI) for processing vector instructions belonging to different vector architectures.
U) is constructed as follows. In FIG. 1, 100 is a V that holds the state of the vector processing unit 3 (VPU).
PU status register, 101 is a scalar processing unit 4
(SPU-A) or scalar processing unit 5 (SPU-
The vector processing unit 3 (V
PU) is a VPU state change unit that changes the state value in order to manage the current value of the state (one of three types). 102
Is a vector instruction register for holding vector instructions, 10
A vector instruction decoding unit 3 decodes the contents of the vector instruction register 103, notifies the vector instruction execution unit 20 of information necessary for executing the instruction via the signal line 210, and starts the execution of the instruction. With function. Reference numeral 104 denotes a register, which is a vector processing start information holding unit that holds vector processing start information (described above) sent from the scalar processing unit 4 (SPU-A) via the signal line 48. A vector instruction reading unit 105 has a function of reading a vector instruction from the main memory 1 based on the vector processing start information held in the register 104.
Reference numeral 106 is a selection circuit. Further, 107 is a timer circuit.

Next, the state of the VPU held in the VPU state register 100 will be described. The vector processing unit 3 (VPU) has the following three states. (A) Free. That is, the state where the vector instruction is not executed. (B) The scalar instruction / vector instruction separation type architecture, that is, the vector architecture A is being processed. (C) Scalar / vector instruction mixed architecture, that is, vector architecture B is being processed.

The software for vector architecture A does not overlap with the software for B. The vector architecture A processing state and the vector architecture B processing state are never established at the same time. 3 above
The transition of one state is performed as follows. (A) When free, a vector processing activation signal (related to vector architecture A) sent via the signal line 47, and a vector instruction sending signal (related to vector architecture B) sent via the signal line 57 ) Is acceptable. When the former is accepted, the vector architecture A processing is in process. When the latter is accepted, the vector architecture B is being processed. If both occur at the same time, the predetermined one is selected. (B) During the vector architecture A processing, the new vector processing start signal 47 and the new vector instruction transmission signal 57 are not accepted. When the started vector processing is completed, the state returns to the free state. (C) During the vector architecture B processing, the new vector processing start signal 47 is not accepted. However,
The vector command transmission signal 57 is sequentially accepted according to the flow of processing of the vector command. When there is no request for sending a vector command from the signal line 57 for a predetermined time, the state returns to the free state.

The above-mentioned state transitions are the vector processing start signal 47, the vector command transmission signal 57, and the signal line 220.
It is managed by the VPU state changing unit 101 using the value of the VPU state register 100 sent via the. The updated state is set in the VPU state register 100 again. Further, the timer circuit 107 is used during the vector architecture B processing to monitor that the vector instruction transmission signal 57 does not come for a predetermined time or longer.

The operation of the VPU state updating unit 101 will be described in more detail. FIG. 4 shows an example of the configuration of the VPU status update unit 101. 4 and FIG. 1 have the same numbers, and are the same.

In FIG. 4, the signal line 231 is the timer 10
A signal for notifying the value of 7 to the VPU state updating unit 101, a signal line 232 is a start signal for the timer 107, and a signal line 23.
Reference numeral 3 is a signal for transmitting a new VPU state value (free, processing of architecture A or processing of architecture B) to be set in the VPU status register 100.

In the vector architecture A, the signal line 234 is a VEN for instructing the end of vector processing.
This signal is notified from the decoder 103 when the D instruction is decoded.

Reference numeral 1001 denotes a decoder having a VPU state value 220. In the free state, the signal line 2001, the signal line 2002 during the vector architecture A processing, and the signal line 2003 during the vector architecture B processing are turned on.

Reference numeral 1002 denotes a zero detection circuit, which is a timer 1
When it is detected that the value of 07 is zero, the signal line 20
04 is turned on.

Next, the vector processing start detector 1003,
Functions of the vector architecture A end detection unit 1004, the vector architecture B continuation detection unit 1005, the vector architecture B end / continuation detection unit 1006, and the VPU next state calculation unit 1007 will be described with reference to FIG.

FIG. 5 is a state transition diagram showing the operation of the VPU state updating unit 101. As described above, there are three states: free state, architecture A processing, and architecture B processing.

In the free state 31, when the vector processing start signal 47 from the SPU-A is turned on, the state transits to architecture A in process 32.

On the other hand, when the vector command transmission signal 57 from the SPU-B is turned on in the free state, the state transits to the architecture B processing 33.

When the signal lines 47 and 57 are turned on at the same time, it may be decided in advance which one has priority. In this embodiment, the signal line 47 is given priority.

It is the vector process start detection unit 1003 in FIG. 4 that executes this series of processes. When both the signal lines 47 and 57 are off as a result of the detection, it is detected that the next state of the VPU is free, and the signal line 2005 is turned on. When the signal line 47 is turned on and the next state of the VPU is the processing of architecture A, the signal line 221 is turned on. When the next state of the VPU is the process of architecture B, the signal line 2006 is turned on.

When the VEND instruction for instructing the end of the vector processing is decoded during the architecture A processing, V
The next state of PU is free. The vector architecture A end detection unit 1004 detects this. Current VPU state is under architecture A processing (signal line 2002
Is turned on), the VEND instruction decode notification is sent from the signal line 47, the vector architecture A ends, the detection unit 100
4, the signal line 2007 is turned on.

When the vector instruction output signal 57 is turned on during the architecture B processing, it is an instruction to further process the vector instruction of the architecture B during the architecture B processing, so that the next state of the VPU is the architecture B.
In process. The vector architecture B detection unit 1005 processes this. The signal line 57 is turned on, and the current VPU state is under architecture B processing (signal line 200
3 on), the signal line 2008 is turned on.
Further, the start signal 232 of the timer 107 is turned on. As a result, the timer 107 starts counting down from a predetermined initial value (non-zero).

When the vector command transmission signal 57 is not turned on during the processing of architecture B, the state transition is made as follows depending on the value of the timer 107. (A) When the value of the timer 107 is non-zero Wait for further arrival of the vector command transmission signal 57 from the SPU-B.

The next state of the VPU becomes the vector instruction processing.

(B) When the value of the timer 107 is zero It is judged that there is no vector command transmission instruction for a predetermined time (until the timer is counted down from the initial value until it reaches zero), and it is judged that it will not come for a while.
The next state of U becomes free.

The vector architecture B end / continuation detecting unit 1006 performs the above processing. When the next state of the VPU is free, the signal line 2009 is turned on, and when the architecture B is being processed, the signal line 2010 is turned on.

The signal lines 2005 to 2010 and 221 are VP.
It is input to the U next state calculation unit 1007, the next state of the VPU is determined, and the signal is sent to the signal line 233. V as above
By the function of the PU state update unit 101, the scalar processing unit 4 (SPU-A) to the vector processing unit 3 (VP
U) instruction for starting vector processing, and the scalar processing unit 5 (SPU-B) to the vector processing unit 3
It is possible to selectively process the sending / execution request of the vector instruction to the (VPU).

Next, the operation of the vector instruction control unit 10 (VIU) during the scalar instruction / vector instruction separation type vector architecture A processing will be described in detail.
When the vector processing unit 3 (VPU) is in the free state and a vector processing start signal arrives from the signal line 47, the VPU state updating unit 101 causes the VPU state register 10 to operate.
A value of 0 is set during vector architecture A processing.
When the state of the vector processing unit 3 (VPU) transits to the vector architecture A processing, the signal line 221 is turned on, and the vector processing start information sent via the signal line 48 is stored in the vector processing start information holding unit 104. set. The information set in the vector processing activation information holding unit 104 is transmitted to the vector instruction reading unit 105 via the signal line 222. Vector instruction reading unit 105
Then, based on the information transmitted from the signal line 222, vector instructions are sequentially read from the main memory 1 via the signal line 230 and placed on the signal line 223. VPU status register 100
Indicates that the vector architecture A is being processed, the selection circuit 106 selects the signal line 223 according to the instruction from the signal line 224. Therefore, the vector instructions read by the vector instruction reading unit 105 are sequentially set in the vector instruction register 102. The vector instruction set in the vector instruction register 102 is decoded by the vector instruction decoding unit 103, and information necessary for execution is sent to the vector instruction execution 20 (VEU) via the signal line 210 and executed. When the decoded vector instruction is an instruction indicating the end of the vector instruction sequence, such as the VEND instruction (End of Vector Processing instruction) of S-810 of Hitachi, Ltd., the subsequent vector instruction in the vector instruction reading unit 105. Is finished and the state of the vector processing unit 3 (VPU) is set to the free state. Since this series of operations is similar to that of the conventional technique, it is not shown.

Next, the operation of the vector instruction control unit 10 (VIU) during the processing of the vector architecture B of the mixed scalar instruction / vector instruction type will be described in detail.

When the vector command transmission signal arrives from the signal line 57 when the vector processing unit 3 (VPU) is in the free state, the VPU state updating unit 101 sets the value of the VPU state register 100 during the vector architecture B processing. .. When the VPU status register 100 indicates that the vector architecture B is being processed, the selection circuit 10
6 selects the signal line 58 according to the instruction from the signal line 224. Therefore, in the vector instruction register 102, the vector instruction sent from the scalar processing unit 5 (SPU-B) via the signal line 58 is set. The vector instruction set in the vector instruction register 102 is decoded by the vector instruction decoding unit 103, and information necessary for execution is transmitted via the signal line 210 to the vector instruction execution unit 20.
Sent to (VEU) and executed. During the processing of the vector architecture B, a new vector command transmission signal transmitted from the signal line 57 is received together with the progress of the processing of the vector command described above. New vector commands sent via signal line 58 along with the vector command send signal are still processed. The timer circuit 107 operates during the processing of the vector architecture B, and if a new vector command transmission signal does not arrive from the signal line 57 even after a predetermined time has passed, it issues an instruction to the VPU state updating unit 101 to output the VPU. The status register 100 is set to the free state.

As described above, the vector processing unit 3 (VPU) shown in FIG.
The configuration is such that two small circuits, that is, the selection circuit 106 and the selection circuit 106 are added.

As described above, in this embodiment, different vector processor architectures of the scalar instruction / vector instruction separation type and the scalar instruction / vector instruction mixed type are used as the scalar processing unit and the vector processing for processing the respective architectures. It is possible to support a small-scale configuration in which a scalar processing unit dedicated to each architecture shares one vector processing unit, while avoiding increasing the scale of the device by preparing each unit individually. In the vector processor, the vector processing unit is used only when processing a vector instruction and is not constantly used. Therefore, even if one vector processing unit is shared by a plurality of scalar processing units as in this embodiment, The performance of the program of each architecture does not decrease significantly.

In the present embodiment, an example has been described in which two different vector architectures are supported by a configuration in which two different scalar processing units share one vector processing unit. Even if there are more kinds, the essence of the present invention is not impaired. For example, if three types of vector architectures are supported, at least three scalar processing units corresponding to the respective architectures, and a vector processing unit having a vector instruction control unit that selectively processes requests from those scalar processing units. It is sufficient to prepare at least one. Further, in the present embodiment, the system configuration for two completely different architectures of the scalar instruction / vector instruction separated type and the scalar instruction / vector instruction mixed type is shown. A combination of a vector architecture and another scalar instruction / vector instruction separation type vector architecture, or a combination of a certain scalar instruction / vector instruction mixed type vector architecture and another scalar instruction / vector instruction mixed type vector architecture You can use a case.

[0079]

As described above, according to the present invention,
Different vector architectures can be supported by scalar processing units corresponding to different instruction set architectures and a smaller number of vector processing units shared by the scalar processing units than the scalar processing units. One system can process software created assuming the architecture. Furthermore, since it can be realized with a number smaller than the number of architectures that support a large number of vector processing units, it is possible to construct a system that supports multiple vector architectures while significantly reducing the system size and cost. There is.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a vector processor system according to an embodiment of the present invention.

FIG. 2 shows a configuration of a scalar instruction unit of a scalar instruction / vector instruction separation type instruction set architecture and a scalar processing unit for activating vector processing, which is one of the constituent elements of the vector processor system of one embodiment of the present invention. It is a figure.

FIG. 3 is a scalar processing for sending a scalar instruction and a vector to a vector processing unit of a scalar instruction / vector instruction mixed type instruction set architecture, which is one of the constituent elements of the vector processor system of an embodiment of the present invention. It is a figure which shows the structure of a unit.

FIG. 4 is a diagram showing details of a vector processing unit according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating state transition in a state changing unit according to an embodiment of the present invention.

[Explanation of symbols]

4 ... Scalar processing unit, 5 ... Scalar processing unit, 6
... Vector processing unit, 10 ... Vector instruction control unit (VIU), 20 ... Vector instruction execution unit (VEU), 1
00 ... Vector processing unit status register, 101 ... Vector processing unit status updating unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuka Kitai 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Tadayuki Sakakibara 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory

Claims (14)

[Claims] 1. A main memory, a first and a second scalar processing unit connected to the main memory, and a vector processing unit connected to the main memory and the first and second scalar processing units. The first scalar processing unit has a first instruction fetch circuit for sequentially fetching a first instruction string, each of which is a scalar instruction, from the main memory; and the first instruction string fetched. A first scalar operation circuit that executes an operation required by a plurality of scalar instructions in the vector processing unit, and the vector processing unit in response to at least one scalar instruction in the fetched first instruction sequence. A second instruction fetch circuit for sequentially fetching a second instruction string, which is a scalar instruction or a vector instruction, from the main memory, A second scalar operation circuit that executes an operation required by a plurality of scalar instructions included in the fetched second instruction sequence, and a plurality of vector instructions in the fetched first instruction sequence A circuit for transferring to the processing unit, the vector processing unit, in response to the activation from the activation circuit, a third instruction sequence for fetching a third instruction sequence, each of which is a vector instruction, from the main memory. The fetch circuit, the processing requested by the plurality of vector instructions included in the fetched third instruction sequence, and the plurality of transferred vector instructions in response to the transfer of the plurality of vector instructions from the transfer circuit. Vector processing device having a vector processing circuit for switching and executing processing requested by the user. 2. A first and a second scalar processing unit for processing instructions fetched from storage, vector instructions received from the storage, and second vector processing instructions.
A vector processing unit for processing a vector instruction received from a scalar unit, wherein the first scalar processing unit executes an operation required by a scalar instruction fetched from the storage; and a fetch unit from the storage. Responsive to the instruction for activating the vector processing unit, the second scalar processing unit having means for activating the vector processing unit, wherein the scalar instruction of the instructions fetched from the storage is Computation means for executing the required computation, and means for sending a vector instruction of the instructions fetched from the storage to the vector processing unit, the vector processing unit, the instruction fetched from the storage Marks the end of a sequence of vector instructions Means for decrypting the completion of an instruction, in response to the activation command and the end command, the vector processor and a state change means for holding by changing the parameters. 3. The state changing means includes a free state of the vector processing unit, a state of a first instruction set architecture in which the vector processing unit accesses the storage to process a vector instruction based on the start instruction, 3. The vector processing according to claim 2, wherein the second scalar processing unit has a status register that holds a status value that distinguishes between a status of a second instruction set architecture that accesses the storage and processes a scalar instruction and a vector instruction. apparatus. 4. The vector processing unit is configured such that a vector instruction from the second scalar processing unit is for a predetermined period,
The vector processing device according to claim 2, further comprising a timer unit that detects that the state change unit has not reached, and the state change unit sets the state value to the free state value according to an output of the timer unit. 5. The timer means has a counter which starts counting by a signal indicating arrival of a vector command from the state changing means, and the state changing means detects that the output of the counter becomes zero. 4. The vector processing device according to claim 3, wherein the state value is set to the free state value. 6. The state changing means fetches a vector instruction from the storage according to the start instruction, the vector instruction from the fetch means according to the parameter, and the vector instruction from the second scalar processing unit. And a selector for selecting either of the two, and the output of the selector is sent to the decoding means.
Vector processing device described. 7. The vector processing device according to claim 6, wherein said vector processing unit has a line for giving the output of said decoding means to said state changing means. 8. A third scalar processing unit, said state means comprising: a first state in which said vector processing unit accesses said storage to process a vector instruction based on a free state of said vector processing unit and said start instruction. An instruction set architecture state, a second instruction set architecture state in which the second scalar processing unit accesses the storage to process a scalar instruction and a vector instruction, and a third scalar processing unit accesses the storage. 2. The vector processing device according to claim 1, further comprising a state register that holds a state value that distinguishes between a scalar instruction and a state of a third instruction set architecture that processes a vector instruction. 9. At least two scalar processing units, each provided according to a different instruction set architecture, for processing instructions fetched from a storage, a vector instruction received from the storage and a vector received from the scalar unit. A vector processing unit for processing instructions, one of the scalar processing units is an arithmetic means for processing a scalar instruction fetched from the storage, and an instruction fetched from the storage is the vector processing unit. The vector processing unit has decoding means for decoding that it is an instruction to activate, and the vector processing unit is connected to the at least two scalar processing units, and an instruction fetched from the storage terminates a series of vector instruction sequences. Indication And a state changing unit for changing and holding a parameter according to the start instruction and the end instruction. The state changing unit is the vector processing unit. State of the first instruction set architecture in which the vector processing unit accesses the storage to process the vector instruction based on the start instruction and the second scalar processing unit accesses the storage to perform the scalar instruction. , A vector processing device having a state register for holding a state value which distinguishably represents a state of a second instruction set architecture for processing a vector instruction. 10. The vector processing unit includes timer means connected to the state changing means for detecting that a vector command from the one scalar processing unit does not reach the state changing means for a predetermined period, 10. The vector processing device according to claim 9, wherein the state changing unit sets the state value to the free state value according to the output of the timer unit. 11. The timer means has a counter that starts counting by a signal indicating arrival of a vector command from the state changing means, and the state changing means detects that the output of the counter becomes zero, and The vector processing device according to claim 10, wherein a state value is the free state value. 12. The state changing means fetches a vector instruction from the storage according to the start instruction, the vector instruction from the fetch means according to the parameter, and the vector instruction from the second scalar processing unit. 10. The vector processing device according to claim 9, further comprising a selector that selects either of the two, and the output of the selector is sent to the decoding means. 13. A vector processing device capable of processing at least two instruction set architectures comprising a scalar instruction and a vector instruction, wherein a scalar instruction belonging to the instruction set architecture is processed corresponding to each of the two instruction set architectures. A plurality of possible scalar processing units, coupled with at least two or more of the scalar processing units, capable of executing vector instructions belonging to each of the two instruction set architectures, and selecting instructions from those scalar processing units. A vector processing unit for processing a vector instruction of the instruction set architecture corresponding to the scalar processing unit that has received the instruction and issued the instruction. 14. A state according to the processing of an instruction set architecture in which an instruction for executing a Veccle instruction sequence is placed in a scalar instruction sequence and an instruction for instructing the end of the sequence is provided at the end of the vector instruction sequence. Means for setting a value for indicating, a means for setting a value for indicating a state according to processing of an instruction set architecture including a mixture of vector instructions and scalar instructions, and for holding the state value connected to the setting means 14. The vector processing device according to claim 13, further comprising: