JPH0516175B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a bipolar transistor capable of high-speed operation and a technology for manufacturing an integrated circuit using the same.

FIG. 1 is a cross-sectional view explaining the structure of a commonly used bipolar transistor, and in the figure,
1 is a semiconductor substrate having one conductivity type; 21 and 22 are high concentration impurity regions having a conductivity type opposite to that of the substrate 1;
31 and 32 are regions having the same type of impurity as 21 and 22, 4 is an impurity region of the same type as the substrate 1, 5 is an insulating film, and 8 is a contact hole, respectively. The impurity regions 32, 4, and 31 constitute the emitter, base, and collector of the bipolar transistor, respectively, and the region surrounded by the broken line in FIG. 1 contributes to the transistor operation. Factors that limit high-speed operation of such transistors include the high base resistance, that is, the high resistance of the impurity region 4 for supplying power to the base region surrounded by the broken line in FIG. 1, and the high resistance between the base and collector. This is because the junction capacitance between the collector and the substrate is large. In order to reduce the base resistance, power is usually supplied to the impurity region 4 through a plurality of contact holes 8.
Further, in order to reduce the junction capacitance, efforts are being made to optimize the impurity concentration and miniaturize the element dimensions. However, these means cannot eliminate impurity regions other than the region surrounded by the broken line in FIG. 1 that contributes to transistor operation, and therefore there is a limit to higher speed operation.

An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates such conventional drawbacks.

According to the present invention, a first insulating layer is provided on a semiconductor substrate, the first insulating layer is selectively removed, and then a polycrystalline or amorphous layer having a first conductivity is formed. Next, the semiconductor layer is irradiated with a laser beam, an electron beam, or a similar energy beam to make the semiconductor layer into a monocrystalline layer close to a single crystal or a single crystal, and then, A region of the single crystallized layer including a portion in contact with the semiconductor substrate is selectively made into a second insulating layer or selectively removed, and then the semiconductor substrate including the surface of the single crystallized layer is A third insulating layer is provided on the surface of the third insulating layer, and then a second conductive layer made of single crystal silicon or metal silicide is provided on the surface of the third insulating layer in a region covering at least a portion of the single crystallized layer. a fourth insulating layer is selectively provided on the surface of the semiconductor substrate including at least a surface of the electrode layer; A hole in which the fourth insulating layer, the electrode layer, and the third insulating layer are sequentially selectively removed is provided in a part of the area that overlaps with the first insulating layer. By crystal-growing a single crystal semiconductor layer having conductivity, a single crystal semiconductor layer having second conductivity serving as a base region, and a single crystal semiconductor layer having first conductivity serving as an emitter region, A method for manufacturing a semiconductor device is obtained, which includes a step of forming a bipolar transistor.

This will be explained in detail below using the drawings.

FIG. 2 shows a schematic process diagram for explaining one embodiment of the present invention, and the same symbols as in FIG. 1 indicate substances having the same functions. In the figure, 51, 52, 5
3 and 54 are insulating layers, 6 is a polycrystalline or amorphous silicon layer, 65 is a near-single-crystalline or single-crystalline layer, 7 is a polycrystalline silicon layer, 81 is a window,
Reference numeral 82 indicates a contact hole, and reference numeral 30 indicates an etataxial silicon layer.

The present invention will be explained step by step, taking as an example a case where silicon is used for the single crystal substrate 1 and an npn transistor is formed.

First, an insulating layer 51 is provided on the surface of the substrate 1,
Subsequently, a part of the layer 51 is selectively removed by a conventional photoetching method to expose the surface of the substrate 1, and then a polycrystalline or amorphous silicon layer 6 is formed (FIG. 2a). The insulating layer 51 is preferably thick in order to reduce the capacitance between the substrate 1 and the polycrystalline or amorphous silicon layer 6, and preferably has a thickness of 0.3 microns or more, for example. The thickness of the polycrystalline or amorphous silicon layer 6 is preferably 0.1 to 0.5 microns, and since the layer 6 is also used as an electrode, it is necessary to contain n-type impurities at a high concentration. One method of doping is to include n-type impurities in the atmosphere during layer formation, but you are free to choose whether to include them separately in a later process without including them during layer formation. .

Next, a laser beam, an electron beam, or a similar point-like or linear heat beam is irradiated onto the surface of the polycrystalline or amorphous silicon layer 6 and moved, so that the portion where the layer 6 contacts the substrate 1 By causing recrystallization to occur, the layer 6 becomes a monocrystalline layer 65 that is close to a single crystal or is a single crystal (FIG. 2b).

Next, a region of the single crystallized layer 65 including at least a portion in contact with the substrate 1 is selectively oxidized,
This becomes an insulating layer 52 (FIG. 2c).

The selective oxidation may be performed, for example, on the silicon layer 65.
After forming an oxidation-resistant film such as silicon nitride on the surface of a desired region, oxidation may be performed in a steam atmosphere at 900 to 1100°C. The purpose of the selective oxidation is to separate the single crystallized layer 65 into island shapes, so that a portion of the single crystallized layer 65 remains on the surface of the insulating layer 51 below the insulating layer 52. must not. Further, at the time of forming such a structure, the single crystallized layer 65 may contain n-type impurities at a high concentration.

In order to separate the single crystallized layer 65 into island shapes, in addition to the method of performing selective oxidation described above, it is also possible to adopt a means of selectively removing unnecessary regions of the single crystallized layer 65. It is possible to use such selective removal means instead without detracting from the present invention. When such means are adopted, the single crystallized layer 65 described above is
Although the surface of the substrate 1 is exposed where it contacts the substrate 1, there is no problem because an insulating layer will be formed in a later step.

The portion where the single crystallized layer 65 contacts the substrate 1 is
Since the single crystallized layer 65 is unnecessary after the single crystallization is performed, such a portion can be used as a scribe line of a semiconductor device without causing any problem in achieving high integration.

Next, the surface of the single crystallized layer 65 is oxidized to form the insulating layer 53 (FIG. 2d).

It is sufficient that the thickness of the insulating layer 53 is 0.2 to 0.5 microns. The insulating layer 53 may be formed by forming a layer made of a substance such as SiO ₂ or Si ₃ N ₄ on the surface of the single crystallized layer 65 and the surface of the insulating layer 52 by means such as vapor phase growth. reach your goal.

Subsequently, a polycrystalline silicon layer 7 is selectively formed in a region covering part of the monocrystalline layer 65 and part of the surfaces of the insulating layers 52, 53 by a conventional photoetching technique (FIG. 2e). Since the polycrystalline silicon layer 7 is used as an electrode, it needs to contain p-type impurities at a high concentration, and the impurity can be doped by including it in the atmosphere when forming the polycrystalline silicon layer, or by not doping it. The doping may be carried out again after the crystalline silicon layer is formed, or even after the polycrystalline silicon layer pattern is formed as shown in FIG. 2e, the choice is free. Furthermore, it is also possible to freely control the impurity concentration in a desired region of the polycrystalline silicon layer and use it as a resistor.

Furthermore, when forming the polycrystalline silicon layer 7, it is possible to form the polycrystalline silicon layer 7 into a single crystal or a layer close to this by again using the means explained in FIGS. 2a and 2b. Needless to say, it's a good thing.

Next, an insulating layer 54 is formed on the surface of the polycrystalline silicon layer 7.
is formed, the insulating layer 54 in the region where the polycrystalline silicon layer 7 and the single crystallized layer 65 at least overlap, and parts of the polycrystalline silicon layer 7 and the insulating layer 53 are sequentially etched by a normal photo-etching technique. The surface of the single crystallized layer is selectively removed and a window 81 is formed (FIG. 2f). Insulating layer 5
4 can be easily formed by, for example, oxidizing the surface of the polycrystalline silicon layer 7, but the object of the present invention can also be achieved by depositing an insulating layer by vapor phase growth. The preferred thickness of the insulating layer 54 is 0.3 to 0.5 microns.

Next, using the single crystallized layer 65 as a seed crystal, the single crystal silicon layer 30 containing n-type impurities is epitaxially grown inside the window 81 (FIG. 2g). If the epitaxial growth is performed, for example, in a SiH ₂ Cl ₂ -H ₂ atmosphere at a temperature of 950 to 1100°C, the window 81
Silicon grows epitaxially inside,
No growth occurs on the surfaces of the insulating layers 52, 53, and 54, allowing so-called selective epitaxial growth. The epitaxially grown single crystal silicon layer 30 needs to have a thickness that reaches at least the surface of the polycrystalline silicon layer 7, and more preferably a thickness that reaches the surface of the insulating layer 54. Next, the epitaxially grown single crystal silicon layer 30 is doped with a p-type impurity and an n-type impurity in order to form an npn transistor. 32 is formed. At this time,
n at the bottom of the epitaxially grown single crystal layer 30
The type impurity region 31 becomes a collector (FIG. 2h).

This doping has the advantage that it is not necessary to newly use a photomask, and an npn transistor can be realized by simply controlling the depth of the impurity. Methods for forming the collector, base, and emitter regions include a thermal diffusion method and a method of accelerating impurity ions at a high voltage and implanting them. , p-type, and n-type impurities can be sequentially included in the atmosphere, and any method can be used freely.

P-type impurity region 4 needs to be provided so as to be at least in contact with polycrystalline silicon layer 7 and not at least in contact with single-crystal or near-single-crystal silicon layer 65. At this time, even if the impurity region 31 and the n-type impurity region 32 contact the polycrystalline silicon layer 7, only a pn junction is formed, and the transistor characteristics are not impaired, but the emitter-base and collector-base junction capacitances increase. Doing so increases the contact resistance between p-type impurity region 4 and polycrystalline silicon layer 7, which deteriorates the frequency characteristics, and is therefore not very preferable. The depth of the impurity region can be easily controlled by selecting the temperature and time of the heat treatment.

Next, the insulating layer 5 on the surface of the single-crystal or near-single-crystal layer 65 is etched using a normal photoetching technique.
3 and a portion of the insulating layer 54 are selectively removed,
A contact hole 82 is formed (FIG. 2i).

In this structure, an electrode such as Al is then formed on the surface of the impurity region 32 serving as an emitter and in a region covering the contact hole 82, thereby forming a bipolar transistor.

The planar structure of such a bipolar transistor is, for example, as shown in FIG. 3, and the portion along the line connecting X--Y in the figure has the cross-sectional structure shown in FIG. 2i. It is clear that such a transistor can operate at high speed because the base-collector and collector-substrate junction capacitances occur only in the region where the transistor operates, and are essentially small, and the base resistance and collector resistance are also small.

Note that in the above description, the impurity region 4 serving as the base
A method of supplying power by bringing the polycrystalline silicon layer 7 into contact with the polycrystalline silicon layer was adopted, but heat-resistant metals such as tungsten, titanium, platinum, molybdenum, or silicide materials thereof may be freely used in place of the polycrystalline silicon layer. This has the advantage of further reducing base resistance.

In addition, in the above explanation, the collector,
Although a bipolar transistor in which a base and an emitter are stacked is taken as an example, it is clear that the present invention can be applied to a case where an emitter and a base collector are stacked in this order.

In the above explanation, silicon was used as the constituent material of the bipolar transistor, but the emitter region could be made of a compound semiconductor such as GaP, which has a wider band gap than silicon and has n-type conductivity. It's okay. Such a semiconductor layer can be formed, for example, in an atmosphere of trimethyl gallium, PH ₃ , H ₂ S at a temperature of 700 to 800°C.

In particular, GaP has a lattice constant of 5.45 angstroms, which matches well with silicon's lattice constant of 5.43 angstroms, and a high-quality layer can be formed with a thickness of approximately 1000 angstroms. A transistor with such a structure can achieve higher speed operation because the injection efficiency of charges injected from the emitter to the base increases.

[Brief explanation of drawings]

Figure 1 is a schematic cross-sectional diagram for explaining the structure of a commonly used bipolar transistor;
The figures are diagrams for explaining one embodiment of the present invention, and show cross sections of a semiconductor device in each process diagram. FIG. 3 shows a plan view illustrating a transistor structure according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate having a first polarity, 21 and 22 are high concentration impurity regions having a second polarity, 31 and 32 are impurity regions having a second polarity, and 4 is a semiconductor substrate having a first polarity. an impurity region having 5,
51, 52, 53, and 54 are insulating layers, 6 is a polycrystalline silicon layer, 65 is a single crystal silicon layer, 7 is an electrode layer, and 30 is a single crystal silicon layer, respectively.

Claims (1)

[Claims] 1. Provide a first insulating layer on a semiconductor substrate, then:
selectively removing the first insulating layer;
A polycrystalline or amorphous semiconductor layer having a conductivity of Then, a region of the single crystallized layer including a portion in contact with the semiconductor substrate is selectively formed into a second insulating layer or selectively removed. A third insulating layer is provided on the surface of the semiconductor substrate including the surface of the single crystallized layer, and then a second insulating layer is provided on the surface of the third insulating layer in a region that at least partially covers the single crystallized layer. An electrode layer made of conductive single crystal silicon or metal silicide is selectively provided, then a fourth insulating layer is provided on the surface of the semiconductor substrate including at least the surface of the electrode layer, and then the A hole is provided in a part of the region where the single crystallized layer and the electrode layer overlap at least by selectively removing the fourth insulating layer, the electrode layer, and the third insulating layer, and then the Inside the hole, a single-crystalline semiconductor layer with a first conductivity serves as a collector region, a single-crystalline semiconductor layer with a second conductivity serves as a base region, and a single-crystalline semiconductor layer with a first conductivity serves as an emitter region. 1. A method for manufacturing a semiconductor device, comprising the step of forming a bipolar transistor by growing a crystalline semiconductor layer.