JPH0516535Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a timing signal generator.

(Prior Art) FIG. 1 is a block diagram showing an example of a main part of a semiconductor measuring device. In Figure 1, CPG is a clock pattern generator, and from this clock pattern generator CPG is a test pattern generator.
A rate signal S _R is output to TPG, a format signal S _F is output to a format circuit FMT, and a strobe signal S _S is output to a comparator CMP. The test pattern generator TPG applies pattern data PD ₁ to the format circuit FMT to output a predetermined test pattern signal, and reference pattern data PD ₂ is applied to the comparator CMP. A predetermined test pattern signal S _TP is applied to the DUT, and the semiconductor device under test is
An output pattern signal _SOP corresponding to the test pattern signal _STP is applied from the DUT to the comparator CMP. Then, in the comparator CMP, the reference pattern data PD ₂ and the output pattern signal S _OP are compared according to the strobe signal S _S , and if they do not match, the fail data D _F is transferred to the fail memory FMM.
will be output to .

By the way, in such a device, the output pattern signal S _OP corresponding to the test pattern signal S _TP may be output within the same rate period as the test pattern signal S _TP , depending on the characteristics of the semiconductor device under test DUT and the test contents. It may be output at the next rate cycle. In this case, the strobe signal S _S must be generated in the next late period.

FIG. 6 is a circuit diagram showing an example of a conventional strobe signal generator that takes these points into consideration. In Fig. 6, STG is a strobe signal generation circuit that generates a strobe signal S _S within the same rate period, and IHG is an inhibit signal _S that selectively inhibits output of a strobe signal S S within a given rate period. The inhibit signal generating circuit AG which generates _I is an AND gate to which these strobe signal S _S and inhibit signal S _I are applied.

FIG. 7 is a waveform example diagram for explaining the operation of FIG. 6, in which a shows the rate signal S _R , b shows the strobe signal S _S , c shows the inhibit signal S _I , and d shows the waveform example. It shows the output signal S _O of AND gate AG. As is clear from FIG. 7, by configuring as shown in FIG. 6, the output of the strobe signal S _S within an arbitrary rate period becomes the inhibit signal _S
will be selectively prohibited.

(Problems to be Solved by the Invention) However, with such a conventional timing signal generator, it is difficult to control the inhibit signal S _I , and the circuit configuration is complicated.

The present invention solves these conventional drawbacks, and its purpose is to realize a timing signal generator that can arbitrarily set the timing signal generation time with a relatively simple circuit configuration.

(Means for Solving the Problems) The present invention that achieves such an object includes a first set value DS that takes in a first set value DS and performs subtraction counting in accordance with a first load signal _SLS applied from the outside. a subtraction counter 6; a first zero detection circuit 10 that detects that the count value of the first subtraction counter 6 has become zero and generates a first zero detection signal; A second subtraction counter 7 takes in the second set value DN as the second load signal S _LN and performs subtraction counting, and a second subtraction counter 7 detects that the count value of the second subtraction counter 7 reaches zero and performs a second zero count. a second zero detection circuit 11 that generates a detection signal, and a predetermined time period set by the first subtraction counter 6 and the second subtraction counter 7 with respect to the first load signal _SLS as a reference. Afterwards, the zero detection signal of the second zero detection circuit 11 is outputted as a timing signal S _S to the outside.

(Example) Hereinafter, it will be explained in detail using the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention. In FIG. 2, 1 is an arithmetic processing unit (hereinafter referred to as CPU). From this CPU 1, a late signal counter 5, a same cycle counter 6, and a next signal are connected to a late signal memory 2, a same cycle memory 3, and a next cycle memory 4 through a bus B. Data DR, DS, and DN for setting the subtraction value of the cycle counter 7 are supplied, and a late start signal _SRS is supplied to the late signal counter 5 and the same cycle counter 6 via the signal line _L1 . ing. 8 is a high frequency oscillator, which connects each counter 5 via the signal line _L2 .
~7 is supplied with clock CP. Zero detection circuits 9 to 11 detect when the counts of counters 5 to 7 reach zero, respectively. A load signal for the counter 5 is sent from the zero detection circuit 9 via the signal line _L3 .
S _LR is supplied, and the late signal S _R and the load signal S _LS of the counter 7 are supplied via the signal line L ₄ , and the load signal S LN of the counter 7 is supplied from the zero detection circuit 10 via the signal line _{L 5} . is supplied, and a strobe signal S _S , for example, is supplied as a timing signal from the zero detection circuit 11 via a signal line _L6 . That is, in FIG. 2, the memory 2, counter 5, and zero detection circuit 9 generate a late signal
RSG is formed, memories 3, 4 and counter 6,
7 and zero detection circuits 10 and 11 form a strobe signal generation section SSG.

FIG. 3 is a time chart showing an example of the operation of FIG. 2, in which a indicates the clock CP, b indicates the late start signal _SRS , c indicates the load signal _SLR , and d indicates the counter 5. , e indicates the rate signal S _R , f indicates the operating state of the counter 6, g indicates the load signal S _LN , h indicates the operating state of the counter 7, and i indicates the strobe signal S _S It shows.

Each of the memories 2 to 4 in FIG. 2 stores data DR, DS, and DN for setting predetermined subtraction values, respectively, prior to the series of operations shown in FIG. 3. Then, at time _t1 , at the same time as the rate start signal _SRS rises, the counters 5 and 6
subtraction counting starts. When the count value of the counter 6 becomes zero at time t ₂ , the zero detection circuit 10 generates a load signal S _LN and supplies it to the counter 7 . As a result, the counter 7 starts subtraction counting. When the count value of the counter 5 becomes zero at time _t3 , the zero detection circuit 9 generates a load signal _SLR and supplies it to the counter 5, further generates a late signal _SR and outputs it to the outside, and also outputs the load signal _SLS. It is supplied to the counter 6 as As a result, counters 5 and 6 start subtraction counting again. When the count value of the counter 7 becomes zero at time _t4 , the zero detection circuit 11 generates a strobe signal S _S and outputs it to the outside.

With this configuration, the strobe signal _S is set by the subtraction value of the same cycle counter 6 set by the data DS and the subtraction value of the next cycle counter 7 set by the data DN from the time the late start signal _SRS rises. It will be output within the next cycle after one cycle _{TR of the late signal S R has} elapsed from the time when the time _TST added to the value has elapsed, that is, from the time when the late start signal _SRS rises.

4 and 5 are data DS for setting the subtraction value of the same cycle counter 6 and data for setting the subtraction value of the next cycle counter 7.
This is a time chart showing the relationship between the DN and the strobe signal in the same period as the rate signal S _R.
Fig _. 5 shows the case where the strobe signal S _S is output within the next cycle of _{the late signal S R ( 2T R ≧} T _ST ≧ T _R ). ing.
In either case, a value corresponding to (T _R − T _D ) is set as the subtraction value setting data DS of the counter 6, and a value corresponding to (T _R − T _{D )} is set as the subtraction value setting data DN of the _counter 7. )}. Note that T _D is the dead time from loading the subtraction value setting data to the counter until starting subtraction counting.

According to such a configuration, when calculating the time T _ST , it is only necessary to consider the subtraction value setting data DS of the counter 6 and the subtraction value setting data DN of the counter 7, and it is necessary to consider only the subtraction value setting data DS of the counter 7. There is no need to control _I , and the circuit configuration becomes simpler.

In the above embodiment, an example of a circuit that generates a strobe signal has been described, but the present invention is not limited to this and can be used as a circuit that generates various timing signals.

(Effects of the Invention) As described above, according to the present invention, a timing signal generator that can arbitrarily set the timing signal generation time can be realized with a relatively simple circuit configuration, and has great practical effects.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the essential parts of a semiconductor measuring device, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Figs. 3 to 5 are time charts explaining the operation of Fig. 2. , FIG. 6 is a circuit diagram showing an example of a conventional device, and FIG. 7 is a time chart illustrating the operation of the conventional device. 1... Arithmetic processing unit (CPU), 2... Memory for late signal, 3... Memory for same cycle, 4... Memory for next cycle, 5... Counter for late signal, 6... Counter for same cycle, 7...Next cycle counter, 8
...High frequency oscillator, 9-11...Zero detection circuit.

Claims (1)

[Claims for Utility Model Registration] A first subtraction counter 6 that takes in a first set value DS and performs subtraction counting in accordance with a first load signal _SLS applied from the outside; and a calculation of the first subtraction counter 6. a first zero detection circuit 10 that detects that a numerical value has become zero and generates a first zero detection signal; and a second set value DN that uses the first zero detection signal as a second load signal S _LN . a second subtraction counter 7 that takes in and performs subtraction counting; and a second zero detection circuit 11 that detects that the count value of the second subtraction counter 7 becomes zero and generates a second zero detection signal. After a predetermined time period set by the first subtraction counter 6 and the second subtraction counter 7 has elapsed based on the first load signal _SLS , the second zero detection circuit 11 detects zero. A timing signal generator characterized by outputting a signal to the outside as a timing signal S _S.