JPH05150763A - Image data conversion device - Google Patents

Abstract

PURPOSE:To compose the image data conversion device of a small number of circuits when picture element data are represented by the different numbers of bits, i.e., 1, 2, 4, and 8 bits and every 8 bits of the data are read out and outputted as a signal which can be displayed on a display device. CONSTITUTION:The 8-bit data read out of a frame memory are inputted, bit by bit, to AND circuits 100-114. Timing signals T1 and T2 are outputted first and bit data of the AND circuits 100 and 102 are supplied to a data converter 200 and converted into data which can be displayed on the display unit. Similarly, timing signals T3, T4, T5, T6, T7, and T8 are outputted and every two bits of the bit data are converted into picture element units. In this case, a timing control circuit 300 is constituted by longitudinally connecting eight shift registers 310-380 and timing signals generated by a 1st shift register are shifted to trailing-stage shift registers in order in picture element units; and dot data are outputted to the data converter 200 from the AND circuits 100-114 in the picture element units.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data conversion device for converting image data into a signal which can be displayed on a display device, and more particularly, to an image data conversion device used when the number of bits of image data representing each pixel differs depending on the image. The present invention relates to a suitable image data conversion device.

[0002]

2. Description of the Related Art For example, VGA (Video Graphics Array)
In an image processing system that processes an image or image data including XGA (Extended Gaphics Array) using an image processing device such as a computer, there is one that converts the image data into various gradations or color tones and displays them on a display device. Are known. In this case, the processing device represents the number of bits representing the gradation or the number of colors of one pixel by the number of bits of 2 to the nth power, and changes the number of bits to, for example, 1,2,4,8 bits. Expand to memory.

In this processing system, a colored figure or the like is written as a code of a desired color by a computer having a special function, such as a drawing function, in the memory developed in the bit map. In this case, 8
1 to 8 if a color lookup table that can express color information up to bits, that is, a so-called color packet is used
Pixel bits up to bits can be represented. For example, if one pixel is represented by 1 bit, black and white display, 2
4 color display when expressed in bits, 16 color display when expressed in 4 bits, 256 when expressed in 8 bits
Color display can be performed simultaneously. These are selected according to the function of the display or the required image. In this case, the access speed from the computer changes depending on the number of bits of one pixel. For example, if you are using a 32-bit personal computer, you can use CP
32 pixels can be drawn by U access, and 4 pixels can be drawn by one access when displaying 256 colors, which is 1 depending on the required processing speed.
The number of bits in the pixel is selected.

Conventionally, in order to change the number of bits of a pixel in such a processing system, for example, in the case of 2 bits / pixel, it is allocated as data for 4 pixels from the most significant bit side, and it is synchronized with the pixel clock, Transfer to the look-up table while sequentially expanding to 8 bits. In the color lookup table, this data is converted into predetermined color data based on this data, and this data is converted into an analog signal by the DA converter. In addition, other numbers of bits are converted into analog signals and displayed using the same process. Specifically, this processing system converts the 8-bit image data read from the image memory into, for example, 1
Each parallel-serial converter for converting into 2 bits, 4 bits, and 4 bits is provided. A bit extender for converting 1-bit, 2-bit, 4-bit data into 8-bit extension data is connected to each converter. 8 read from these extenders and image memory
Bit data is selected by a multiplexer, and the output of this multiplexer is converted into predetermined color data or gradation data by a look-up table, converted into an analog signal by a DA converter, and displayed on a display or the like.

[0005]

However, the above-mentioned conventional technique requires a plurality of converters for performing parallel-serial conversion of the image data stored in the image memory according to the number of bits thereof, and these There is a problem that a plurality of extenders for converting the data into extended 8-bits are required respectively, and the circuit becomes complicated. In particular,
A multiplexer for selecting 8-bit data from these or the image memory and outputting it to the look-up table is required.
Since one type of 8-bit data is selected from the bit parallel data, it becomes a large and expensive circuit having a 32-bit input and an 8-bit output, and a device using this becomes large and expensive. There was a problem.

The present invention solves the above-mentioned drawbacks of the prior art, can supply image data having different numbers of bits to a look-up table without using a large multiplexer, and simplifies the circuit configuration to realize a device. It is an object of the present invention to provide an image data conversion device that can be made compact and inexpensive.

[0007]

According to the present invention, in order to solve the above-mentioned problems, image data in which each pixel is represented by a predetermined number of bits is expanded and stored in a bit map in an image memory. In an image data conversion device that converts image data read in parallel from an image memory for each specific number of bits into a signal that can be displayed on a display device and outputs the signal, the device is read in parallel at a specific number of bits. Input means for inputting the image data for each bit,
Timing control means for supplying a timing signal for each pixel represented by a predetermined bit number to these input means and outputting for each pixel data, and each output by the timing signal of the timing control means from the input means And a data conversion unit that outputs predetermined data that can be displayed on the display device based on the data for each pixel, and the timing control unit shifts the timing signal for each predetermined bit to output pixels to the input unit. It is characterized by outputting a timing signal for each.

In this case, the input means is composed of two-input AND circuits, and each bit of the image data is input to one input terminal of these AND circuits, and the timing from the timing control means is input to the other input terminal. It is advisable to output the data by inputting a signal.

Further, the timing control means is formed by a plurality of shift registers, shifts the timing signal from the first shift register for generating the timing signal of the most significant bit to the shift register on the lower bit side, respectively, and Each shift register may output a timing signal to the input means based on the shifted timing signal.

In this case, the first shift register uses the blanking signal indicating the transition from the blanking period to the image display period in the display device and the dot clock indicating the pixel display timing or the timing from the shift register of the least significant bit. The first timing signal may be generated based on the signal.

Further, the data conversion means is provided with a latch means for latching pixel data of a predetermined number of bits from the input means and outputting the pixel data with a specific number of bits, and with a specific number of bits supplied from these latch means. A look-up table for inputting data as a code and outputting predetermined color data or gradation data, and a digital-analog conversion means for analog-converting the data output from the look-up table and outputting the analog-converted data.

In this case, the lookup table has a plurality of tables according to the number of bits for each pixel, and the table is selected according to the number of bits for each pixel.

[0013]

According to the image data conversion device of the present invention,
The image data read in parallel from the image memory with a specific number of bits is input to the input unit for each bit, and the pixel is generated in response to the timing signal from the timing control unit supplied to the input unit. It is output every time.
In this case, the timing control means shifts the timing signal according to the number of bits of each pixel and sequentially supplies it to the input means. Accordingly, the image data is supplied to the data conversion unit for each pixel, and the data conversion unit can convert the signal displayable on the display device for each pixel based on the input data and output the converted signal.

[0014]

Embodiments of the image data conversion apparatus according to the present invention will now be described in detail with reference to the accompanying drawings. As shown in FIG. 1, the image data conversion apparatus in this embodiment reads the image data PID0 to PID7 supplied for each 8 bits into one input terminal of the AND circuits 100 to 114 for each bit, Image data for each pixel Data converter 20
It is a data conversion device which is supplied to 0 and is output as a signal that can be displayed on a display such as a display by the data converter 200. Particularly, in the image data conversion apparatus in this embodiment, the number of bits representing one pixel is represented by a plurality of bit numbers such as 1, 2, 4, 8 bits, and the other one of the AND circuits 100 to 114 is correspondingly selected. There is provided a timing control circuit 300 for supplying timing data to the respective terminals for each pixel to perform timing control.

More specifically, the image data PID0 to PID7 supplied to the AND circuits 100 to 114 are represented in a frame memory (not shown) by the image processing device by representing one pixel as either 1, 2, 4, or 8 bits. The data is stored and stored, and when it is displayed on a display or the like, it is read out from the frame memory in units of 8 bits and supplied to the AND circuits 100 to 114 for each bit. Along with this, the blanking signal is
HBLK and dot clock DCLK are timing control circuit 30
Supplied to 0.

Timing control circuit 30 in this embodiment
0 is eight shift registers 310 to 380 connected in cascade.
Is equipped with. The first shift register 310 receives the blanking signal HBLK and the dot clock DCLK, and receives the blanking signal HBLK and the dot clock DCLK. The serial clock serves as a timing signal for sending out the control signals S0 to S6 of the second to eighth shift registers to a control circuit (not shown). It is a circuit that generates SCLK and a first timing signal T1 that is the timing data of the most significant bit PID7 and the timing data of the shift register in the subsequent stage. The first shift register 310 has an input terminal I to which a blanking signal HBLK is supplied, an input terminal C to which a dot clock DCLK is supplied, and an input terminal for receiving a timing signal T8 fed back from the eighth shift register 380. R
And an output terminal O1 for transmitting the serial clock SCLK to the control circuit of the processing device, and an output terminal O2 for transmitting the generated first timing data.

The first shift register 310 is realized by a circuit structure as shown in FIG. 2, for example. In this figure, the first shift register 310 includes three delay circuits 400.
~ 420, two AND circuits 430,440, and OR circuit 450
It has and. The delay circuit 400 uses the blanking signal H
It is a D latch circuit which receives BLK and dot clock DCLK from terminals I and C, and outputs a delayed output of blanking signal HBLK from Q output at the rise of this dot clock DCLK. The delay circuit 410 is a D-latch circuit that receives the Q output of the delay circuit 400 and further delays the blanking signal HBLK with the next dot clock DCLK to send out an inverted output from the Q-bar output. The delay circuit 420 is a D-latch circuit that receives the timing signal T7 fed back from the eighth shift register 280 from the terminal R, and outputs the delayed output of the timing signal from the Q output at the rising edge of the dot clock DCLK. The AND circuit 430 receives the Q output of the delay circuit 400, the Q output of the delay circuit 410 and the dot clock DCLK and outputs from the terminal 02 a serial clock SCLK as shown in FIG. 4 for supplying to the control circuit of the processing device. It is a logic circuit. The AND circuit 430 is a logic circuit which receives the Q output of the delay circuit 400 and the Q output of the delay circuit 410 and outputs the first timing signal T1 as shown in FIG. The first timing signal T1 is output to the AND circuit 100 and the next register 320 via the OR circuit 450. The OR circuit 450 is a logic circuit that receives the output of the delay circuit 420 or the AND circuit 440 and outputs either one from the terminal O1.

Returning to FIG. 1, the second to eighth shift registers 320 to 380 are the shift registers 310 to 310 of the preceding stage, respectively.
It is a timing circuit which receives the timing signal supplied from 370 and the control signals S0 to S6 supplied from the control circuit of the processing device, and sends the timing signals T2 to T8 to the AND circuits 102 to 114, respectively. As shown in FIG. 3, these second to eighth shift registers 320 to 370 are provided with a delay circuit 50.
0, two AND circuits 510 and 520, and nut circuit 530
And an OR circuit 540. The delay circuit 500 receives the timing data T1 (to T7) from the shift register 310 (to 370) at the previous stage via the input terminal D and delays the timing signal T2 (to T8) at the next rising edge of the dot clock DCLK. It is a D-latch circuit that outputs the output. AND circuit 510
Receives the timing signal T1 (~ T7) supplied from the shift register 310 (~ 370) at the previous stage, and when the control signal S (S6 (~ S0)) from the control circuit is "High" at this time, This is a logic circuit that outputs the timing signal T2 (to T8) at the same timing as the shift register 310 (to 370) in the previous stage. The nut circuit 530 is a logic circuit that inverts the control signal S (S6 (to S0)) from the control circuit and outputs the inverted signal to the AND circuit 520. The AND circuit 520 is a logic circuit which receives the Q output of the delay circuit 500 and outputs its timing output as an inverted signal of the control signal S (S6 (to S0)) supplied via the nut circuit 530. In this case, the timing signal is output when the control signal S is "Low". The OR circuit 540 is an AND circuit 510,52.
This is a logic circuit that outputs any signal of 0 as a timing signal T2 (to T8).

These second to eighth shift registers 320-
380 is, for example, a control signal S0 ...
When both S6 are "Low", each AND circuit 520
As shown in FIG. 4, the shift register 320 which receives the timing signal T1 of the register 310 outputs the delayed output which rises at the next dot clock C2 as the timing signal T2, and the timing from the shift register 320 in the same manner. Timing signal that rises at the next dot clock C3 from the shift register 330 that receives the signal T2
T3 is output, and thereafter, the timing signals T4, T5, T6, T7, T8 delayed by the registers 340, 350, 360, 370, 380 and the timings T3, T4, T5, T6, T7 of the previous stage are sequentially output.

Further, these second to eighth shift registers
In the case of 2 dots / pixel shown in FIG. 5, 320 to 380 are the control signal S6 "High", the control signal S5 "Low", and the control signal S4 "H".
igh "Control signal S3 is" Low ", control signal S2 is" High ", control signal
When S1 is "Low" and the control signal S0 is "High", the timing signal T1 of the shift register 310 and the timing signal T2 are output from the shift register 320 through the AND circuit 510 and the OR circuit 540 at the same time. 320
The timing signal T3 delayed by the next dot clock DCLK is output from the shift register 330 which has received the timing signal T2 from the delay circuit 500, the AND circuit 520 and the OR circuit 540, and at the same time.
The timing signal T4 is output from the 340, the timing signal T5 is similarly delayed from the shift register 350, and the timing signal T6 is output from the shift register 360 at the same timing as the shift register 350.
Timing signal T of shift register 350,360 from 0,380
Timing signals T7 and T8 delayed from 5, T6 are output.

Further, in the case of 4 dots / pixel shown in FIG. 6, these second to eighth shift registers 320 to 380 have the control signals S6 to S4 and S2 to S0 as "High" and the control signal S3 as "3". Low "
The shift register 320 to 340 to the register 310
The timing signals T2 to T4 are simultaneously output from the AND circuit 510 and the OR circuit 540 at the same time as the timing signal T1 of, and the timing signal T5 from the shift register 350 is output after being delayed from the timing signal T4 of the shift register 340.
The shift registers from the subsequent shift registers 360 to 380
Timing signals T6 to T8 at the same time as 350 timing signal T5
Is output. Furthermore, when the control signals S6 to S0 are all "High", the second to eighth shift registers 320 to 380 are timing signals at the same time as the timing signal T1 from the shift registers 320 to 380. T2 to T8 are output via the AND circuit 510 and the OR circuit 540, respectively.

Returning to FIG. 1 again, the data converter 200 is
Eight D latches 600 to 670, a color look-up table 700, and a digital-analog converter 800 are provided. D latches 600 to 670 are AND circuits 10 respectively.
These are latch circuits that receive the outputs of 0 to 114 and output them in synchronization with the dot clock DCLK. The color lookup table 700 is composed of a RAM (Randam Access Memory) that rewritably stores color data at any time. In the case of this embodiment, as shown in FIG.
1 to TB4 are written in advance. These tables TB1 to TB4 are selected by the data switching control signal SD supplied from the control circuit of the processing device. This switching signal SD has pixel data of 1 bit, 2 bits, 4 bits,
When switching 8 bits, that is, shift register 320 ~
It is supplied at the same time as the control signals S0 to S7 to the 380. For example, when the pixel data is 1 bit, the signal SD for selecting the table TB1 is supplied. In this case, there are two types of data 0 and 1, data 0 represents black display and data 1 represents white display. ing. In the case of data 1, there are seven types of address designation "01" to "80", but all of these addresses are output as white data. If the pixel data is 2 bits, table TB2 is selected. In this case, data 0 to 4
There are four types of color data, and there are four types of addressing for each color data. If the pixel data is 4 bits, table TB3 is selected. In this case, data 0-F
It has 16 types of color data, and there are two types of addressing for each color data. In case of 8 bits, table TB4 is selected, and 256 kinds of addresses specify 256 kinds of color data.

The digital-analog converter 800 is a converter which converts the color data designated by the color lookup table 700 into an analog signal and outputs it.

The operation of the image data conversion apparatus of this embodiment having such a configuration will be described below. When the image data processed by the image processing device is displayed in black and white on the display, the image processing device develops each pixel in the frame memory as 1-bit bitmap data. The data read from the frame memory for each byte (8 bits) is supplied to one input terminal of the AND circuits 100 to 114 for each bit. At the same time, the timing control circuit 300 receives the blanking signal HB
The dot clock DCLK is supplied together with LK.

The blanking signal BCLK becomes "Low" during the blanking period and becomes "High" during the display period. When the shift register 310 receives the first dot clock DCLK (C1) after the blanking signal BCLK becomes "High", it outputs the serial clock SCLK to the control circuit of the processing device as shown in FIG. Further, the first timing signal T1 is output to the AND circuit 100 and the shift register 320 of the next stage. Upon receiving the serial clock SCLK, the control circuit of the processing device supplies the control signals S0 to S7 to the shift registers 320 to 380 and the switching signal to the color lookup table 700.
Supply SD. In this case, since the display is black and white, the control signals S0 to S7 are all supplied at "Low". The table TB1 is selected in the color lookup table 700 by the switching signal SD.

Since the control signals S0 to S7 are all "Low", the timing signals T2 from the shift registers 320 to 380 are sequentially delayed by one clock from the timing signal T1 of the first shift register 310 as shown in FIG. ~ T8 is output. When the timing signal T1 of the shift register 310 is supplied to the AND circuit 100, first, the dot data PID7 input to the AND circuit 100 is output to the data converter 200. This data PID is latched by the latch circuit 600,
Next dot clock DCLK All latch circuits 600 ~
8-bit data is output from the 680 to the lookup table 700 as address data. In this case, "0" data from the latch circuits 610 to 680, that is, "Don't car
e "is output. This makes the lookup table 700
Can receive an 8-bit input represented by dot data PID7 as data and select an 8-bit output from the table TB1 for processing. In this case, since the lookup table is the table TB1 for black and white display, the output corresponding to data 0 or data 1 is performed. With this output, the first pixel data is converted to analog by the analog converter 800 and output to the display.

Next, the timing signal T2 from the second shift register 320 is supplied to the AND circuit 110, the data including this dot data PID6 is supplied to the data converter 200, and the color of this pixel is looked up. Specified in table 700, the data is D / A converted and output. Similarly, the timing signals are sequentially output from the shift registers 330 to 380.
T3 to T8 are supplied to the AND circuits 130 to 170, and the dot data PID5 to PID0 input to them are supplied to the data converter 200, respectively, and sequentially subjected to color designation and analog conversion and output.

The timing signal T8 output from the shift register 380 is fed back to the shift register 310 so that the next timing signal can be transmitted.
The data output from 0 and the 8-bit data are sequentially converted by the data converter 200 and output in the same manner as described above. This operation is repeated for every 8 bits and one horizontal scanning data is displayed on the display.

Next, when the blanking signal is supplied in the blanking period, the timing signal T1 is generated again in the shift register 310, and the shift registers 320 to 38 are generated.
The image data of one horizontal scanning line is output after shifting to 0. By repeating this, one screen of a monochrome image is displayed on the display.

Next, a case where an image developed into a bit map is represented by 2 bits for each pixel will be described. First, the serial clock SC from the first shift register 310
When LK is supplied to the control circuit, control signals S0 to S6 are supplied to the shift registers 320 to 380 from the control circuit. In this case, the control signals S0, S2, S4, S6 become "High", and the control signal S
1, S3, S5 are supplied as "Low". As a result, as shown in FIG. 6, the timing signals T1 and T2 are simultaneously supplied from the shift registers 310 and 320 to the AND circuits 100 and 110, respectively, and then the timing signals T3 and T4 are simultaneously supplied from the shift registers 330 and 340 to the AND circuits 120 and 130. , Shift registers 350, 360, shift registers 360, 37
0 and timing signals T5 to T8 are output sequentially. Further, since the control signal SD is sent from the control circuit to the look-up table 700 so as to select the table TB2 for the four-color display, the four-color data is input by the 8-bit data input via the latch circuits 600 to 670. One of these colors is specified and output to the DA converter 800. As a result, the 8-bit data read from the frame memory is output to the display as color data for 4 pixels.

Similarly, in the case of 4 bits / pixel, only the control signal S3 becomes "Low", so that the shift register 350
The timing data is shifted by and the color is designated by the look-up table 700 as data for every two pixels, DA converted, and displayed. In case of 8 bits, control signal S0 ~
When S7 becomes all "High", the timing signals T1 to T8 are simultaneously supplied to the AND circuits 100 to 114, which are simultaneously supplied to the look-up table 700 for 8 bits and displayed on the display as 256 color data.

As described above, the image data conversion apparatus according to the present embodiment reads the image data into the AND circuits 100 to 114 for each bit, and determines the number of bits of one pixel among 1, 2, 4, and 8 bits. , The timing control circuit 300 supplies timing data to the AND circuits 100 to 114, and the data converter 20 for each pixel is supplied.
Output to 0 and convert. In this case, the timing control circuit 300 can sequentially read from the upper bit to the lower bit for each pixel by shifting the timing signal T1 (to T7) from the shift registers 310 to 380 in the previous stage. In addition, the serial clock SCLK is sent from the shift register 310 to the control circuit for each blanking, and the control signals S0 to S7 to the shift registers 320 to 380 and the switching signal SD to the lookup table 700 are output. The number of bits can be changed for each line, and the color expression can be changed to display an image.

In the above embodiment, the case where the data is read from the frame memory in every 8 bits has been described. However, in correspondence with the transfer function of the processing device and the conversion function of the lookup table, every 16 bits or 32 bits, or The data may be read out for each other specific bit and the data may be converted for each pixel.

[0034]

As described above, according to the image data conversion device of the present invention, the image data input to the input means for each bit is supplied with timing data for each pixel to the data conversion means. To be done. Therefore, by switching the timing data according to the number of bits shown for each pixel, it is possible to cope with any number of bits. As a result, it is not necessary to provide a converter and an expander according to the number of bits, and a multiplexer is not required, and an excellent effect that the device can be configured with a small and inexpensive circuit is achieved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an image data conversion device according to the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a first shift register 310 in the embodiment.

FIG. 3 is a second to eighth shift register in the same embodiment.
It is a circuit diagram which shows the internal structure of 320 (-380).

FIG. 4 is a time chart showing a timing signal output when one pixel is represented by one bit in the present embodiment.

FIG. 5 is a time chart showing a timing signal output when the same pixel is represented by 2 bits.

FIG. 6 is a time chart showing a timing signal output when the same pixel is represented by 4 bits.

FIG. 7 is a diagram showing an example of a data table of a lookup table 700 in the embodiment.

[Explanation of symbols]

 100 to 114 AND circuit (input means) 200 Data converter 300 Timing control circuit 310 to 380 Shift register 400 to 420,500 Delay circuit 430,440,510,520 AND circuit 450,540 OR circuit 530 Nut circuit 610 to 670 Latch circuit 700 Color lookup table 800 Digital Analog converter DCLK Dot clock HBLK Blanking signal PID0 to PID7 Dot data SCLK Serial clock T1 to T7 Timing signal TB1 to TB4 Color table

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical display location G09G 5/18 8121-5G H04N 7/01 Z 9070-5C

Claims (6)

[Claims] 1. Image data in which each pixel is represented by a predetermined number of bits is expanded and stored in an image memory in a bit map, and image data read out in parallel from the image memory for each specific number of bits is obtained. In an image data conversion device for converting into a signal displayable on a display device and outputting the signal, the device comprises an input means for inputting image data read in parallel at a specific number of bits for each bit. Timing control means for supplying a timing signal for each pixel represented by the predetermined number of bits to the input means and outputting for each pixel data; and output from the input means by the timing signal of the timing control means. And a data conversion means for outputting predetermined data that can be displayed on the display device based on the data for each pixel. By every preparative shifts the timing signal, the image data conversion device and outputs a timing signal for each pixel in said input means. 2. The image data conversion apparatus according to claim 1, wherein each of the input means is composed of a two-input AND circuit, and each bit of the image data is input to one input terminal of the AND circuit. An image data conversion apparatus, which outputs bit data by inputting a timing signal from the timing control means to the other input terminal. 3. The image data conversion apparatus according to claim 1, wherein the timing control means is composed of a plurality of shift registers, and each of the timing signals from the first shift register that generates the timing signal of the most significant bit is supplied. Shift to the shift register on the lower bit side,
An image data conversion device, wherein each shift register outputs a timing signal to the input means based on these shifted timing signals. 4. The image data conversion device according to claim 3, wherein the first shift register indicates a blanking signal indicating a transition from a blanking period to an image display period and a pixel display timing in the display device. An image data conversion device, wherein a first timing signal is generated based on a timing signal from a dot clock or a least significant bit shift register. 5. The image data conversion device according to claim 1, wherein the data conversion means latches pixel data of a predetermined number of bits from the input means and outputs the latched pixel data with a specific number of bits. , A look-up table for inputting data supplied from the latch means in a specific number of bits as a code and outputting predetermined color data or gradation data, and analog-converting the data output from the look-up table. An image data conversion device comprising: a digital-analog conversion unit for outputting. 6. The image data conversion apparatus according to claim 5, wherein the lookup table has a plurality of tables according to the number of bits of each pixel, and the table is selected according to the number of bits of each pixel. An image data conversion device characterized by the following.