JPH04352581A - LCD drive circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0010

[Field of Industrial Application] This invention relates to a drive circuit for a liquid crystal display device, and in particular to a PA in displays such as color TVs, projections, and viewfinders.
The present invention relates to a drive circuit for a liquid crystal panel that enables L/NTSC display on the same panel.

[0020]

[Prior Art] Unlike cathode ray tubes, liquid crystal display devices can have a flat display section, and this, together with the recent integration of drive circuits using semiconductors, has greatly contributed to the miniaturization of display devices. ing. It is particularly applied to display devices of portable devices, and color TVs and the like have also become portable devices.

[0030] By the way, the drive systems for color TVs currently adopted around the world are typically the PAL system and the NTS system.
There is a C system, and although these images have the same height/width ratio of 3:4, the number of scanning lines differs, such as 625 in the PAL system and 525 in the NTSC system. Therefore, when trying to use a common liquid crystal panel for PAL and NTSC systems, NTSC, which has a small number of scanning lines,
When using a liquid crystal panel manufactured to conform to the specifications of the C system and using it in the PAL system, a part of the image is thinned out to make it compatible.

A driving circuit for displaying a PAL image using a conventional NTSC liquid crystal panel will be described below. First, an NTSC system drive circuit is shown in FIG. The liquid crystal panel 11 has pixels arranged in a two-dimensional matrix, and images are displayed by sequentially selecting pixels from this matrix of pixels using a vertical shift register 9 and a horizontal shift register 10, and supplying a video signal to the selected pixels. be done. Therefore, the liquid crystal panel is formed with a matrix of pixels compatible with the NTSC system.

A drive circuit is provided to select pixels of the liquid crystal panel 11 and supply video signals. That is, the received composite video signal a is demodulated into R, G, and B primary color signals b by a demodulator 1, and shifted to a voltage suitable for driving a liquid crystal panel by a voltage level converter 2, thereby forming a liquid crystal input video signal c. and is supplied to the liquid crystal panel 11. Further, the composite video signal a is input to a synchronization signal separator 3, and a composite synchronization signal d is extracted. This composite synchronization signal d is transmitted to the AFC circuit 4.
The horizontal synchronizing signal e is separated by the integrator 8, and the vertical synchronizing signal i is separated by the integrator 8. The horizontal synchronizing signal e is sent to the phase comparator 5.
, a PLL consisting of a voltage controlled oscillator 6 and a 1/N frequency divider 7
(Phase Locked Loop) circuit. A phase error signal f is output from the phase comparator 5 of the PLL circuit, and an oscillation clock signal g corresponding to this error signal f is formed. This clock signal g is supplied to the horizontal shift register 10 as a clock for scanning the liquid crystal panel 11 in the horizontal direction, and is frequency-divided by the frequency divider 7 to form a horizontal synchronizing pulse h. This horizontal synchronizing pulse h is fed back to the phase comparator 5 for the PLL function, and is also supplied to the horizontal shift register 10 and the vertical register 9. Here, the vertical synchronizing pulse i input to the vertical shift register 9 is a start pulse of the shift register 9, and the horizontal synchronizing pulse h is a clock signal for the shift operation. Further, the horizontal synchronizing pulse h input to the horizontal shift register 10 is a start pulse for the shift register 10, and the oscillation clock signal g becomes a clock signal for a shift operation. An image is displayed on the liquid crystal panel 11 by supplying an NTSC video signal to the liquid crystal drive circuit.

Next, a case will be described in which a PAL video signal is displayed using the same liquid crystal panel 11. For ease of understanding, the explanation will be made without taking into account overscan and blanking periods included in normal television signals. Figure 4
is a liquid crystal drive circuit for the PAL system, and the difference from the drive circuit in FIG. shift register 9
In order to perform thinning processing on vertical scanning, a circuit is provided which adds an α/β frequency divider 12 to form a new thinned horizontal synchronizing pulse j. In other words, in order to display a PAL video signal with a large number of scanning lines on the NTSC compatible liquid crystal panel 11, the PA of the PLL circuit output is
A thinned horizontal synchronizing pulse j is formed by stopping the signal at a ratio of (β-α) times to β times of the L horizontal synchronizing pulse h, and this thinned horizontal synchronizing pulse j is shifted by the vertical shift register 9. Clock. Due to this thinning horizontal synchronizing pulse j, the vertical shift register 9 shifts 625/2×α/β times during one vertical period of the PAL video signal. Therefore, α/β of frequency divider 12 is 525/2
By setting the relationship =625/2×α/β,
While the PAL video signal is being thinned out, the LCD panel 11
is displayed.

[0070]

[Problems to be Solved by the Invention] In the conventional liquid crystal drive circuit described above, when a PAL system image with a large number of scanning lines is displayed using a liquid crystal panel compatible with the NTSC system, the problem occurs as shown in FIG.
In the normal image shown in (a), the horizontal scanning lines are thinned out at a certain rate by the signal processing described above, and as a result, discontinuity occurs in the vertical direction as shown in Fig. 5 (b), and the image becomes significantly distorted. be damaged. In addition, this thinned-out line portion is more likely to cause line flicker than other portions, which is not preferable from this point of view as well. Furthermore, in the case of liquid crystal display devices such as mobile TVs and projection devices, where the purpose of the display device can be achieved with a small liquid crystal panel, PAL/NTSC is used.
Regardless of the method used, there is a need to improve productivity by sharing liquid crystal panels.

The present invention was made in view of the above-mentioned conventional problems, and provides a liquid crystal display device that can display images using NTSC video signals using a PAL compatible liquid crystal panel without degrading image quality. Provides a drive circuit.

[0090]

[Means for Solving the Problems] The present invention provides a drive circuit that enables PAL/NTSC systems with different numbers of scanning lines to be displayed on the same liquid crystal panel. A horizontal drive clock generation circuit that outputs a clock for horizontally scanning the pixels of the liquid crystal panel using an NTSC video signal with a small number of scanning lines, and a horizontal drive clock generation circuit that outputs a clock for horizontally scanning the pixels of the liquid crystal panel using an NTSC video signal with a small number of scanning lines. A liquid crystal display device comprising: a mask timing control circuit that provides a period during which no video signal is input; and a switching circuit that converts the signal level of a mask area set by the mask timing control circuit to a preset constant value and outputs the signal level. This constitutes the drive circuit of

[0100]

[Operation] According to such a configuration, in horizontal scanning of the liquid crystal panel, by speeding up the horizontal drive clock, the P
The horizontal expansion that occurs when an AL video signal is displayed on an NTSC compatible liquid crystal panel is reduced and displayed. Furthermore, in both the vertical and horizontal directions, for pixels that are not required for display, the input line of the video signal is held at a constant level, such as the black level, during the scanning period. Therefore, for a PAL compatible liquid crystal panel, display is performed using the pixel area required for displaying an image of an NTSC video signal.

[0110]

[Example] In this example, the liquid crystal panel does not necessarily have to form 625 horizontal scanning lines according to the panel dimensions, but it is designed in advance to have the number of pixels suitable for displaying PAL video signals. There is. This liquid crystal panel has an active drive structure in which a TFT is formed for each pixel. When displaying images using PAL video signals, use the normal PAL video signal.
Drive circuits such as a synchronization signal circuit and a video signal circuit are configured to correspond to the AL signal, and an image is displayed on the liquid crystal panel based on the input PAL composite video signal.

FIG. 1 shows the liquid crystal panel 2 compatible with the above PAL signal.
This is a drive circuit for displaying an image using an NTSC signal using 0, and an NTSC video signal is input as a composite video signal A. The input NTSC composite video signal A is demodulated into R, G, and B primary color signals B by a demodulator 21, adjusted to a voltage suitable for driving the liquid crystal by a voltage level converter 22, and converted into a liquid crystal input video signal C. converted. This liquid crystal input video signal C is applied to the liquid crystal panel 20 via an analog switch 23 for masking pixels in an unnecessary image area by maintaining the signal level at a constant value of the black level. The connection of the analog switch 23 is controlled by a signal input from a mask timing control circuit 24, which will be described later.

The composite video signal A is input to the sync separator 25, and the sync signal D is taken out. This synchronizing signal D is further separated into a horizontal synchronizing signal E by an AFC circuit 26 and into a vertical synchronizing signal I by an integrator 27. The horizontal synchronization signal E is transmitted through the phase comparator 28 and the voltage controlled oscillator 2.
9 and a 1/N frequency divider 30. Here, a phase error signal F is outputted from the phase comparator 28 of the PLL circuit, and an oscillation clock signal G corresponding to this error signal F is formed. This clock signal G is supplied to the horizontal shift register 32 as a clock for scanning the liquid crystal panel 20 in the horizontal direction, and
The frequency is divided by the frequency divider 30 to form the horizontal synchronizing pulse H. This horizontal synchronizing pulse H is fed back to the phase comparator 28 for the PLL function, and is also supplied to the horizontal shift register 32 and vertical register 31.

The 1/N frequency divider 30 has the input NT
Since the PAL compatible liquid crystal panel 20 is driven by the SC signal, the count number is designed to be N×625/525, which is inversely proportional to the vertical display reduction ratio between PAL and NTSC.

The vertical synchronization pulse I input to the vertical shift register 31 is a start pulse for the shift register 31, and the horizontal synchronization pulse H becomes a clock signal for the vertical shift operation. Further, the horizontal synchronizing pulse H input to the horizontal shift register 32 is a start pulse for the shift register 32, and the oscillation clock signal G becomes a clock signal for the horizontal shift operation.

[0160] The liquid crystal panel 20 of this embodiment is provided with the number of vertical and horizontal pixels adapted to PAL signals.
Unnecessary pixels occur in display where image signals other than the pixel area selected for the SC signal are not input. It is necessary to take measures to prevent such pixels from being affected by noise. For this purpose, the drive circuit of this embodiment is provided with a mask timing control circuit 24. The various synchronizing signals G, H, and I described above are input to the mask timing control circuit 24 in order to select pixels on the liquid crystal panel, and during the periods of these synchronizing signals, the video signal C is supplied to the liquid crystal panel 20.
During the period when pixels not needed for display are scanned, a mask timing signal J is outputted to control the connection state of the analog switch 23, and the signal level to the liquid crystal panel 20 is maintained at a stable black level for masking. By supplying an NTSC video signal to the liquid crystal drive circuit having the above configuration,
As shown in (a), image display is performed using the pixels 20A in the pixel area of the liquid crystal panel 20 necessary for displaying the NTSC signal. At this time, the liquid crystal panel 20
In the pixels 20B in the other areas, the signal of the liquid crystal panel is held constant by the connection state of the analog switch 23, and the signal is masked without noise. For comparison, FIG. 2(b) shows a display screen when the liquid crystal panel 20 is driven with a normal PAL video signal.

The area of the liquid crystal panel for displaying an NTSC image is not limited to the embodiment shown in FIG. 2(a), and it is desirable to set which pixel area of the liquid crystal panel is used for display. The phases of the vertical synchronizing pulse I and the horizontal synchronizing pulse H are changed, and the vertical and horizontal shift registers 3 are
The position can be selected by shifting the start timings of 2 and 31.

[0180]

As described above, according to the present invention, it is possible to display an NTSC video signal using a liquid crystal panel compatible with PAL signals, and it is possible to use a common liquid crystal panel. As a result, not only the burden of liquid crystal panel development is reduced, but also peripheral equipment such as optical systems and mechanical systems can be made common, and the development of liquid crystal TVs can be further promoted. In addition, the image displayed on the liquid crystal panel does not have discontinuity unlike the conventional drive method, and can be used even when the panel becomes larger.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device driving circuit according to the present invention.

FIG. 2 is a diagram showing the display state of the liquid crystal panel in the same embodiment.

FIG. 3 is a block diagram of a conventional liquid crystal display device driving circuit for displaying an NTSC video signal.

FIG. 4 is a block diagram of a liquid crystal display device driving circuit for displaying a PAL video signal using a conventional NTSC compatible liquid crystal panel.

FIG. 5 is a diagram showing the display state of a conventional liquid crystal panel.

[Explanation of symbols]

20 LCD panel 23 Analog switch 24 Mask timing control circuit 30 1/N frequency divider 31 Vertical shift register 32 Horizontal shift register A Composite video signal B RGB primary color signal C. LCD video signal D Composite sync signal E Horizontal synchronization signal G Oscillation clock signal H Horizontal sync pulse I Vertical sync pulse J Mask timing signal

Claims (1)

[Claims] Claim 1: A drive circuit that can display PAL/NTSC systems with different numbers of scanning lines on the same liquid crystal panel, comprising: a liquid crystal panel in which pixels are arranged in a matrix to correspond to the PAL system with a large number of scanning lines; A circuit that generates a horizontal drive clock at a speed corresponding to the horizontal ratio of both NTSC images, and a mask timing control circuit that sets a period during which no video signal is input for the NTSC video signal, which has a small number of scanning lines. and a switching circuit that receives the output of the mask timing control circuit and converts the signal level of an area where no video signal is input into a preset constant value and outputs the same. drive circuit.