JP2025021846A - Semiconductor Device - Google Patents

Abstract

[Problem] To provide a semiconductor device with high operational stability, including a laminated structure in which a metal electrode layer is laminated on a semiconductor layer made of Si. [Solution] A semiconductor device including a laminated structure exhibiting rectification properties in which a first metal electrode layer is laminated on a p-type semiconductor layer made of p-type Si, and/or a laminated structure exhibiting ohmic properties in which a second metal electrode layer is laminated on an n-type semiconductor layer made of n-type Si. A layered compound layer made of a layered compound of Sb and/or Bi with Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer, and/or between the n-type semiconductor layer and the second metal electrode layer. [Selected Figure] Figure 1

Description

The present invention relates to a semiconductor device that includes a laminated structure in which a metal electrode layer is laminated on a semiconductor layer made of Si.

When a semiconductor layer made of Si is brought into contact with a metal layer, it can either form a "diode junction (Schottky junction)" that exhibits rectification, or an "ohmic junction" that does not exhibit such rectification. This difference depends on the size of the energy barrier between the Si semiconductor layer and the metal layer, and also on whether the Si semiconductor layer is made of a p-type or n-type semiconductor, as well as the type of metal that is combined with it.

For example, Patent Document 1 discloses a semiconductor device including a merged p-i-n Schottky (MPS) structure in which Schottky diodes and pn-type diodes are alternately arranged on one surface of a semiconductor element, and Schottky junctions are provided in the n-type semiconductor region and ohmic junctions are provided in the p-type semiconductor region. This document states that the interface is not stable when a NiAl alloy is bonded to form a Schottky junction on the n-type semiconductor region using SiC as the semiconductor substrate, and that the Schottky junction layer in the n-type semiconductor region and the ohmic junction layer in the p-type semiconductor region should be formed from different materials. Specifically, it states that the ohmic junction layer is made of an alloy containing aluminum and titanium, and the Schottky junction layer is made of a metal mainly composed of molybdenum.

JP 2010-50267 A

When a semiconductor layer made of Si is brought into contact with a metal layer, whether it is rectifying or ohmic, unless the contact interface is stable, operational stability cannot be obtained. As mentioned above, it has been confirmed that even if a high-melting-point metal such as molybdenum is used, the contact interface becomes wavy and sufficient operational stability cannot be obtained.

The present invention was made in consideration of the above-mentioned circumstances, and aims to provide a semiconductor device with high operational stability, including a laminated structure in which a metal electrode layer is laminated on a semiconductor layer made of Si.

The inventors of the present application have noted that, for example, even W, a high melting point metal, does not form a sufficiently flat interface when bonded to Si, resulting in a lack of operational stability in the semiconductor device, such as rectification and ohmic properties.

That is, the semiconductor device according to the present invention is a semiconductor device including a laminated structure exhibiting rectification in which a first metal electrode layer is laminated on a p-type semiconductor layer made of p-type Si, and/or a laminated structure exhibiting ohmic properties in which a second metal electrode layer is laminated on an n-type semiconductor layer made of n-type Si, and is characterized in that a layered compound layer made of a layered compound of Sb and/or Bi and Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer, and/or between the n-type semiconductor layer and the second metal electrode layer.

This feature allows for a semiconductor device with high operational stability by interposing a layered compound layer that exhibits rectification and ohmic properties between the semiconductor layer and has a high interfacial smoothness.

In the above-mentioned invention, the layered compound layer may be characterized by including an amorphous phase. This characteristic allows for good interface smoothness and results in a semiconductor device with high operational stability.

In the above-mentioned invention, the layered compound layer may be characterized by having a thickness of 1 to 10 nm. This characteristic allows a semiconductor device with high operational stability to be obtained, regardless of the metal type of the metal electrode layer.

In the above-mentioned invention, the layered compound may be characterized in that it is composed of (Sb _x Bi _1-x ) ₂ Te ₃ (where 0<x<1). With this characteristic, it is possible to provide a semiconductor device that exhibits good rectification and ohmic properties, and also provides good interface smoothness, resulting in a high operational stability.

The p-type Si may be characterized in that it contains Ge in Si. The n-type Si may be characterized in that it contains C in Si. With these characteristics, it is possible to obtain a semiconductor device that exhibits good rectification and ohmic properties and has high operational stability.

FIG. 2 is a diagram showing a laminated structure in which a metal electrode layer is laminated on a semiconductor layer according to the present invention. FIG. 2 is a band diagram when (a) a metal electrode layer and (b) a layered compound layer are connected to an n-type Si semiconductor. 1 shows cross-sectional STEM (scanning transmission electron microscope) images of the vicinity of a connection interface when (a) a metal electrode layer and (b) a layered compound layer are respectively connected to a semiconductor layer. FIG. 2 is a cross-sectional view showing a junction between a semiconductor layer and a layered compound layer according to the present invention. FIG. 2 is a band diagram of a Si semiconductor with Sb ₂ Te ₃ and Bi ₂ Te ₃ . FIG. 2 is a diagram showing the potential barrier height for n-type Si. 1 is a graph showing the relationship between the heat treatment temperature and the potential barrier height of a layered compound layer joined to a p-type Si semiconductor (resistivity: 5 Ωcm). 1 is a graph showing the relationship between the applied voltage and the current for a junction structure of an n-type Si semiconductor (resistivity: 5 Ωcm) and a metal (W), and a junction structure in which Sb ₂ Te ₃ is formed therebetween. 1 is a graph showing the relationship between the applied voltage and the current for a junction structure of a p-type Si semiconductor (resistivity: 5 Ωcm) and a metal (W), and a junction structure in which Sb ₂ Te ₃ is formed therebetween. 1A to 1C are cross-sectional views showing a manufacturing process of a top-gate transistor according to an embodiment of the present invention. 1A to 1C are cross-sectional views showing a manufacturing process of a top-gate transistor according to an embodiment of the present invention. 1A to 1C are cross-sectional views showing a manufacturing process of a top-gate transistor according to an embodiment of the present invention. 1A to 1C are cross-sectional views showing a manufacturing process of a top-gate transistor according to an embodiment of the present invention.

Below, one embodiment of the present invention will be described in detail with reference to the drawings.

First, the manufacturing method of the semiconductor device and the resulting semiconductor device will be described with reference to FIG.

As shown in FIG. 1, first, a layered compound layer 4 made of an amorphous film made of Sb and/or Bi and Te is formed on a semiconductor layer 2. The semiconductor layer 2 is made of a Si semiconductor. The Si semiconductor is selected from either a p-type semiconductor made of p-type Si or an n-type semiconductor made of n-type Si. It may be made of a Si semiconductor containing C or Ge. Then, a metal electrode layer 3 is provided on the layered compound layer 4. As a result, a layered compound layer 4 made of a layered compound made of Sb and/or Bi and Te is interposed between the semiconductor layer 2 and the metal electrode layer 3.

There are no particular limitations on the material of the metal electrode layer 3, and examples that can be used include tungsten (W), cobalt (Co), and ruthenium (Ru).

Examples of materials for the layered compound layer 4 include Sb _x Te _1-x , Bi _x Te _1-x , and (Bi _x Sb _1-x ) ₂ Te ₃ , where 0<x<1.

Then, the amorphous film of the layered compound layer 4 is crystallized by heat treatment. The amorphous film is crystallized by heat treatment at an appropriate temperature to become a layered compound with a crystalline phase. As described below, the layered compound layer 4 may contain an amorphous phase and may not be heat treated. Also, a crystallized layered compound layer 4 can be obtained by forming the layered compound layer 4 on the semiconductor layer 2 while performing heat treatment.

The semiconductor device 1 obtained in this manner includes a laminated structure of a metal electrode layer/semiconductor layer, and compared to a case where the metal electrode layer and the semiconductor layer are directly bonded, the height of the potential barrier between these layers can be changed. This makes it possible, for example, to reduce the contact resistance or improve the on/off ratio of the diode current.

Referring now to FIG. 2(a), generally, when an n-type Si semiconductor (n-Si) is bonded to a metal electrode layer 3 (W) as the semiconductor layer 2, a diode junction with a high potential barrier height (BH) is formed due to the difference between the work function of the metal and the work function of the semiconductor layer, and due to Fermi level pinning caused by metal induced gap states (MIGS). Therefore, bonding the metal electrode layer 3 to the semiconductor layer 2 made of an n-type Si semiconductor increases the contact resistance.

2B, in the structure of the semiconductor device 1 of this embodiment, when the layered compound layer 4 made of Sb ₂ Te ₃ is joined to the semiconductor layer 2, the pinning position of the Fermi level is changed, and the potential barrier height (BH) can be lowered. This reduces the contact resistance compared to when a metal electrode layer is directly joined to the semiconductor layer, and makes it possible to form an ohmic junction that exhibits ohmic properties.

Also, as shown in FIG. 3(a), it is generally difficult to obtain a flat bonded interface when the semiconductor layer 2 and the metal electrode layer 3 are bonded. On the other hand, as shown in FIG. 3(b), in the laminated structure of this embodiment, a bonded interface that is flat at the atomic level can be obtained between the semiconductor layer 2 and the layered compound layer 4. The lower limit of the thickness of the layered compound layer 4 is about 1 nm, which is the thickness of one layer that is the smallest unit of the layered compound. In addition, the layered compound layer 4 is preferably made to have a thickness of 10 nm or less so as not to excessively increase the resistance. This upper limit of the thickness is based on the fact that the resistivity in the vertical direction of the layered compound layer 4 is about 0.01 Ωcm. For example, in order to obtain a specific contact resistivity of 10 ⁻⁸ Ωcm ² or less, the film thickness can be calculated to be 10 nm or less by setting the resistivity in the vertical direction×film thickness=specific contact resistivity. In other words, the thickness of the layered compound layer 4 is preferably within the range of 1 to 10 nm.

As shown in FIG. 4, by obtaining such an atomically flat bonding surface, a defect-free interface that is ideal as a bonding surface can be formed between the semiconductor layer 2 (Si semiconductor) and the layered compound layer 4 (Te-based layered material). This allows for a semiconductor device with high operational stability.

5, the Si used in the semiconductor layer 2 has a band gap between the highest point E _V of the valence band and the lowest point E _C of the conduction band. According to the example in the figure, for n-type Si, it is advantageous to use a layered compound layer 4 having a work function close to the lowest point E _C of the conduction band, for example, Sb ₂ Te _3. For p-type Si, it is advantageous to use a layered compound layer 4 having a work function close to the highest point E _V of the valence band, for example, Bi ₂ Te _3. In this way, the layered compound made of Sb and/or Bi and Te used in the layered compound layer 4 has a characteristic band alignment with respect to the Si semiconductor.

In particular, in a layered compound made of (Bi _x Sb _1-x ) ₂ Te ₃ , when the composition ratio is changed by changing the value of x within the range of 0 to 1, the work function changes between the work function of Sb ₂ Te ₃ and the work function of Bi ₂ Te _3. In other words, the work function of (Bi _x Sb _1-x ) ₂ Te ₃ can be adjusted within the range from near the lowest E _C of the conduction band of Si to near the highest E _V of the valence band of Si according to the composition ratio based on the value of x. Therefore, the electron barrier height due to the contact between the semiconductor layer 2 and the metal electrode layer 3 is not only changed, but can also be adjusted according to the change in this work function.

As shown in FIG. 6, in the past, no materials were found that, except for rare earth elements such as lanthanides, had a potential barrier height with n-type Si that was close to the Ec (conduction band) edge. However, the layered compounds of Sb and Te used in the layered compound layer 4 of this embodiment can make the potential barrier height with Si close to the Ec edge to a degree comparable to that of rare earth elements. As a result, the layered compound layer 4 made of SbTe-based compounds can reduce the contact resistance between the semiconductor layer 2 made of n-type Si and the metal electrode layer 3.

As shown in Fig. 7, it was found that the potential barrier height (BH) is higher when the metal layer (W) is bonded via the layered compound layer of _Sb2Te3 than when the metal layer (W) is directly bonded to the semiconductor layer ₂ made of a p-type Si semiconductor with a resistivity of 5 Ωcm (W/Si). It was also confirmed that there is almost no change in the potential barrier height of the layered compound layer when it is as-deposited as an amorphous film and when it is heat-treated at four heat treatment temperatures (annealing temperatures) of 100, 200, 300, and 400°C. In other words, it was found that the potential barrier height can be obtained in the amorphous phase as well as in the crystalline phase.

Also, as shown in FIG. 8, in the stacked structure of this embodiment using Sb ₂ Te ₃ as the layered compound layer, the current when a reverse voltage is applied is larger than that of a conventional Schottky barrier diode using an n-type Si semiconductor with a resistivity of 5 Ωcm. There is almost no difference in the current when a forward voltage is applied. In this way, compared to the conventional metal junction, a characteristic with a low on/off ratio can be obtained. In other words, a stacked structure with an ohmic junction with low contact resistance can be obtained.

On the other hand, as shown in FIG. 9, in the stacked structure of this embodiment using Sb ₂ Te ₃ in the layered compound layer, the current when a reverse voltage is applied is smaller than that of a conventional Schottky barrier diode using a p-type Si semiconductor with a resistivity of 5 Ωcm. There is almost no difference in the current when a forward voltage is applied. In this way, compared to the conventional metal junction, a high on/off ratio characteristic can be obtained. In other words, a stacked structure with a diode junction that has excellent rectification and little leakage current can be obtained.

In other words, compared to the conventional junction between a semiconductor layer and a metal electrode layer, it can be expressed as follows: When an SbTe-based thin film is used for the layered compound layer, the contact resistance can be reduced by using an n-type Si semiconductor for the semiconductor layer, and the on/off ratio of the current can be increased by using a p-type Si semiconductor for the semiconductor layer.

In addition, referring again to FIG. 5, the following is also clear when compared with the conventional junction between a semiconductor layer and a metal electrode layer. That is, when a BiTe-based thin film is used as the layered compound layer, the contact resistance can be reduced by using a p-type Si semiconductor for the semiconductor layer, and the on/off ratio of the current can be increased by using an n-type Si semiconductor for the semiconductor layer.

As described above, these embodiments allow the height of the potential barrier due to contact between the semiconductor layer and the metal electrode layer to be changed.

Next, we will explain an example of manufacturing a transistor as the semiconductor device 1.

Figures 10 to 13 show the manufacturing process of a top-gate field effect transistor (FET) as an example of a semiconductor device that uses the above-mentioned stacked structure.

As shown in FIG. 10(a), first, an insulating film 8 is formed on a semiconductor substrate 6 by atomic layer deposition (ALD). Then, as shown in FIG. 10(b), a gate electrode layer 9 is formed on the insulating film 8. Then, as shown in FIG. 10(c), a gate region is patterned by lithography, and the gate electrode layer 9 is dry etched to form a gate electrode.

Then, as shown in FIG. 11(a), the insulating film 8 is etched, and as shown in FIG. 11(b), a layered compound layer 4, which is an amorphous film made of Sb and/or Bi and Te, is deposited on the semiconductor substrate 6 to a thickness of 10 nm or less by, for example, a sputtering method. Then, as shown in FIG. 11(c), the layered compound layer 4 is removed from areas other than the source/drain regions by lithography and dry etching.

A silicon semiconductor is used as the material for the semiconductor substrate 6.

The insulating film 8 is formed of any material, and for example, an oxide film such as _{SiO2 , Al2O3} , _{HfO2 , ZrO2, Y2O3, or La2O3 can be used .}

There are no particular limitations on the material of the gate electrode layer 9, and examples of the material that can be used include tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), and alloys or laminated films containing two or more of these.

Then, as shown in FIG. 12(a), the amorphous film of the layered compound layer 4 is crystallized by heat treatment at an appropriate temperature to form a layered compound in the crystalline phase. After that, as shown in FIG. 12(b), an interlayer insulating film 10 is formed, and as shown in FIG. 12(c), a contact hole 10' is etched.

Furthermore, as shown in FIG. 13(a), a metal electrode layer 3 that will become a plug electrode is formed, and as shown in FIG. 13(b), a plug electrode is formed from the metal electrode layer 3 by lithography and dry etching. This makes it possible to obtain a FET as a semiconductor device in which a layered compound layer 4 is interposed between a semiconductor layer 2 (semiconductor substrate 6) made of a Si semiconductor and the metal electrode layer 3. This makes it possible to obtain a top-gate type field effect transistor with reduced contact resistance. The temperature of the heat treatment is preferably set, for example, in the range of 100°C or higher.

In this way, by inserting the layered compound layer 4 between the semiconductor layer 2 made of a Si semiconductor and the metal electrode layer 3, the contact resistance between the semiconductor layer 2 and the metal electrode layer 3 can be reduced.

The above-mentioned laminated structure can be applied to semiconductor devices such as transistors, Schottky diodes, light-emitting diodes, solar cells, thermoelectric conversion elements, and any other electronic or optical devices that have a junction between a metal electrode layer and a semiconductor layer made of a silicon semiconductor.

Although the present invention has been described above with reference to examples and variations thereof, the present invention is not necessarily limited to these examples. Furthermore, a person skilled in the art will be able to find various alternative embodiments and modifications without departing from the spirit of the present invention or the scope of the appended claims.

1 Semiconductor device 2 Semiconductor layer 3 Metal electrode layer (plug)
4 Layered compound layer 6 Semiconductor substrate 8 Insulating film 9 Gate electrode layer 10 Interlayer insulating film

Claims (6)

A semiconductor device including a laminated structure exhibiting rectification properties in which a first metal electrode layer is laminated on a p-type semiconductor layer made of p-type Si, and/or a laminated structure exhibiting ohmic properties in which a second metal electrode layer is laminated on an n-type semiconductor layer made of n-type Si,
A semiconductor device, characterized in that a layered compound layer made of a layered compound of Sb and/or Bi and Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer, and/or between the n-type semiconductor layer and the second metal electrode layer. The semiconductor device according to claim 1, characterized in that the layered compound layer contains an amorphous phase. The semiconductor device according to claim 1 or 2, characterized in that the layered compound layer has a thickness of 1 to 10 nm. 3. The semiconductor device according to claim 1, wherein the layered compound is made of (Sb _x Bi _1-x ) ₂ Te ₃ (where 0<x<1). The semiconductor device according to claim 4, characterized in that the p-type Si contains Ge. 5. The semiconductor device according to claim 4, wherein the n-type Si contains C.

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