JP2024171959A - Imaging device and imaging method - Google Patents

Abstract

To reduce settling time while suppressing increase in power consumption of an imaging device.SOLUTION: An imaging device comprises: a load transistor that, on the basis of a source follower operation between the load transistor and a pixel with a vertical signal line interposed therebetween, reads out a signal from the pixel; and a boosting circuit that boosts a gate voltage of the load transistor during at least part of a settling period of the vertical signal line. The imaging device may further comprise a sample-hold transistor that is connected in series to a gate of the load transistor, and a coupling capacitor that is connected in parallel to the gate of the load transistor. The imaging device may further comprise a sample-hold capacitor that is connected in parallel to the gate of the load transistor.SELECTED DRAWING: Figure 3

Description

This technology relates to an imaging device and an imaging method. More specifically, this technology relates to an imaging device and an imaging method capable of reading out signals from pixels based on source follower operation.

In solid-state imaging devices, shortening the settling time is desirable in order to increase the readout speed of pixel signals. For example, in order to shorten the settling time, a solid-state imaging device has been proposed that stops the supply of current to the vertical signal line in conjunction with the occurrence of potential fluctuations in the charge detection section (see, for example, Patent Document 1).

JP 2017-118373 A

However, in the conventional technology described above, a constant current flows through the vertical signal line during the settling period. Therefore, if the current during the settling period is increased in order to shorten the settling time, there is a risk that this will result in a large increase in power consumption.

This technology was developed in light of these circumstances, and aims to shorten the settling time while suppressing increases in power consumption of imaging devices.

The present technology has been made to solve the above-mentioned problems, and a first aspect of the technology is an imaging device that includes a load transistor that reads out a signal from a pixel based on a source follower operation between the pixel and a vertical signal line interposed therebetween, and a boost circuit that boosts the gate voltage of the load transistor during at least a part of the settling period of the vertical signal line. This provides the effect of shortening the settling time without increasing power consumption outside the settling period.

In addition, in the first aspect, the boost voltage applied to the gate voltage from the boost circuit may be variable. This provides the effect of making the settling time adjustable.

In the first aspect, the device may further include a sample-and-hold transistor connected in series to the gate of the load transistor, and a coupling capacitance connected in parallel to the gate of the load transistor. This provides the effect of boosting the gate voltage of the load transistor based on capacitive coupling.

In the first aspect, the coupling capacitance may be variable. This provides the effect of making it possible to adjust the gate voltage of the load transistor.

In the first aspect, the coupling capacitance may also serve as a sample-and-hold capacitance that is sampled and held by the sample-and-hold transistor. This provides the effect of sample-and-holding by the coupling capacitance while capacitively coupling the gate of the load transistor and the boost circuit via the coupling capacitance.

In the first aspect, the device may further include a sample and hold capacitor connected in parallel to the gate of the load transistor. This provides the effect of biasing the gate of the load transistor based on the sample and hold voltage.

In the first aspect, the pixel may include a photodiode, a transfer transistor that transfers the charge stored in the photodiode to a floating diffusion, a reset transistor that resets the floating diffusion, an amplifier transistor that outputs a signal according to the potential of the floating diffusion, and a selection transistor connected between the amplifier transistor and the vertical signal line. This provides the effect of forming a source follower between the pixel and the load transistor when a signal is read from the pixel.

In the first aspect, the settling period may be a period from when the potential of the floating diffusion is applied to the vertical signal line until the potential of the vertical signal line converges. This provides the effect of setting the settling period based on the potential fluctuation of the vertical signal line.

In the first aspect, the settling period may include a period from after the reset period to the P-phase AD conversion period. This provides the effect of stabilizing the potential of the vertical signal line during the P-phase AD conversion.

In addition, in the first aspect, the boost circuit may set the gate voltage of the load transistor during the settling period higher than the gate voltage of the load transistor during the reset period. This provides the effect of shortening the settling period without increasing the power consumption during the reset period.

In the first aspect, the settling period may include a period from after the signal readout period to the D-phase AD conversion period. This provides the effect of stabilizing the potential of the vertical signal line during the D-phase AD conversion.

In addition, in the first aspect, the boost circuit may set the gate voltage of the load transistor during the settling period higher than the gate voltage of the load transistor during the signal readout period. This provides the effect of shortening the settling period without increasing the power consumption during the signal readout period.

In addition, in the first aspect, a pixel array section may be provided in which the pixels are arranged in a matrix in the row and column directions, the coupling capacitance may be provided for each column, and the boost circuit may be shared by a plurality of columns. This provides the effect of boosting the gate voltage of the load transistor while suppressing an increase in the circuit size of the boost circuit.

The second aspect is an imaging device that includes a load transistor that reads out a signal from a pixel based on a source follower operation between the pixel and a vertical signal line interposed therebetween, and a boost circuit that boosts the gate voltage of the load transistor outside the signal readout period from the pixel. This has the effect of reducing the settling time while suppressing an increase in power consumption during the signal readout period.

In the second aspect, the boost period of the gate voltage of the load transistor may be set separately from the signal read period from the pixel. This provides the effect of boosting the gate voltage of the load transistor outside the signal read period from the pixel.

The third aspect is an imaging method in which a signal is read from a pixel based on a source follower operation between the pixel and a load transistor via a vertical signal line, and the gate voltage of the load transistor is boosted during at least a part of the settling period of the vertical signal line. This provides the effect of shortening the settling time without increasing power consumption outside the settling period.

In the third aspect, the gate voltage of the load transistor may be boosted via a coupling capacitance. This provides the effect of boosting the gate voltage of the load transistor based on capacitive coupling.

In addition, in the third aspect, a sample and hold transistor connected to the gate of the load transistor may be turned on, a charge that generates a bias voltage to be applied to the gate of the load transistor may be stored in a sample and hold capacitance, and after the sample and hold transistor is turned off, the gate voltage of the load transistor may be boosted via the coupling capacitance. This reduces the load imposed on boosting the gate voltage of the load transistor.

1 is a block diagram illustrating an example of a configuration of an imaging device according to a first embodiment. 1 is a block diagram illustrating an example of a configuration of a solid-state imaging device according to a first embodiment. 4 is a diagram illustrating a configuration example of a signal readout circuit for one column according to the first embodiment; FIG. 5 is a timing chart showing an example of waveforms at various parts during signal readout of the solid-state imaging device according to the first embodiment. 2 is a diagram illustrating a configuration example of a signal readout circuit for a plurality of columns according to the first embodiment; FIG. FIG. 13 is a diagram illustrating a configuration example of a signal readout circuit for one column according to a second embodiment. FIG. 13 is a diagram illustrating a configuration example of a signal readout circuit for one column according to a third embodiment. FIG. 13 is a diagram illustrating a configuration example of a signal readout circuit for one column according to a fourth embodiment. FIG. 13 is a diagram illustrating a configuration example of a signal readout circuit for one column according to a fifth embodiment. FIG. 23 is a perspective view showing an example of a stack of a pixel array unit according to a sixth embodiment; 1 is a block diagram showing a schematic configuration example of a vehicle control system; FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit.

Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described in the following order.
1. First embodiment (example of boosting the gate voltage of a load transistor via a coupling capacitance during the settling period of a vertical signal line)
2. Second embodiment (example of boosting the gate voltage of a load transistor via a coupling variable capacitance during the settling period of a vertical signal line)
3. Third embodiment (example in which the boost voltage for boosting the gate voltage of the load transistor via the coupling capacitance during the settling period of the vertical signal line is made variable)
4. Fourth embodiment (an example in which the gate voltage of a load transistor is boosted via a coupling capacitance also used as a sample and hold capacitance during the settling period of a vertical signal line)
5. Fifth embodiment (an example in which the gate voltage of a load transistor is boosted via a coupling variable capacitance also used as a sample and hold capacitance during the settling period of a vertical signal line)
6. Sixth embodiment (example in which pixel array sections are stacked)
7. Examples of applications to moving objects

1. First embodiment
FIG. 1 is a block diagram showing an example of the configuration of an imaging apparatus according to the first embodiment.

In the figure, the imaging device includes an optical system 11, a solid-state imaging device 12, a controller 13, an optical system driving unit 14, and an LCD (Liquid Crystal Display) 15. The imaging device also includes a storage medium 16, a flash memory 17, an SDRAM (Synchronous Dynamic Random Access Memory) 18, and an operation unit 19. The imaging device may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, or an EV (Electric Vehicle) or a drone.

The optical system 11 forms an optical image on the imaging surface of the solid-state imaging device 12. The optical system 11 includes a focus lens 21, a zoom lens 22, and an aperture 23. The focus lens 21 adjusts the focus position on the imaging surface of the solid-state imaging device 12. The zoom lens 22 adjusts the magnification of the subject image formed on the imaging surface. The aperture 23 adjusts the amount of light incident on the imaging surface of the solid-state imaging device 12.

The solid-state imaging device 12 detects the optical image formed on the imaging surface for each pixel, converts it into an electrical signal, and digitizes and outputs the pixel signal corresponding to the amount of light in the optical image. The solid-state imaging device 12 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

The controller 13 performs overall control of the entire imaging device. The controller 13 may include a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). The processor may be a single-core processor or a multi-core processor. The controller 13 may include a hardware circuit such as an accelerator that performs part of the processing (e.g., an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit)).

The controller 13 includes an image processing unit 31, an imaging control unit 32, an optical system control unit 34, an LCD driver 35, a storage medium control unit 36, a flash memory control unit 37, and an SDRAM control unit 38. The controller 13 also includes an AE (Auto Exposure) processing unit 61, an AF (Auto Focus) processing unit 62, a sequence control unit 63, and a compression/decompression unit 64. The image processing unit 31, the imaging control unit 32, the optical system control unit 34, the LCD driver 35, the storage medium control unit 36, the flash memory control unit 37, the SDRAM control unit 38, the AE processing unit 61, the AF processing unit 62, the sequence control unit 63, and the compression/decompression unit 64 are connected to each other via a bus 39.

The image processing unit 31 performs image processing based on pixel signals generated by the solid-state imaging device 12. The image processing unit 31 includes a luminance/color signal generation unit 101, a luminance gamma unit 102, a luminance gain unit 103, a WB (White Balance) correction unit 104, a color gamma unit 105, a color difference conversion unit 106, and a color difference gain unit 107.

The luminance/color signal generation unit 101 performs a matrix operation based on the pixel signals generated by the solid-state imaging device 12 to generate a luminance signal and a color signal. The luminance signal can indicate, for example, the luminance value of each pixel. The color signal can indicate, for example, the magnitude of the RGB components of each pixel.

The luminance gamma unit 102 corrects the luminance of the luminance signal according to the display characteristics of the image. For example, the luminance gamma unit 102 can correct the luminance of the luminance signal according to the luminance characteristics of the LCD 15. The luminance gain unit 103 performs gain processing of the luminance signal.

The WB correction unit 104 corrects the white balance of the color signal. The color gamma unit 105 corrects the color tone of the color signal according to the display characteristics of the image. For example, the color gamma unit 105 can correct the color tone of the color signal according to the color characteristics of the LCD 15. The color difference conversion unit 106 converts the color signal of RGB composition into a color difference signal based on a matrix operation. The color difference gain unit 107 performs gain processing of the color difference signal.

The imaging control unit 32 controls the imaging of the solid-state imaging device 12. The imaging control unit 32 includes an exposure control unit 181, a WB control unit 182, a gamma control unit 183, and a gain control unit 184.

The exposure control unit 181 controls the exposure of the solid-state imaging device 12. At this time, the exposure control unit 181 can control the exposure time, exposure amount, shutter timing, and the like of the solid-state imaging device 12 based on, for example, the processing result of the AE processing unit 61. The exposure control unit 181 can use the AE evaluation value as the processing result of the AE processing unit 61.

The WB control unit 182 controls the gain amount for each RGB component of the WB correction unit 104 based on the input information input via the operation unit 19. The gamma control unit 183 controls the gamma characteristics of the luminance gamma unit 102 for the luminance signal and the gamma characteristics of the color gamma unit 105 for the color signal based on the input information input via the operation unit 19. The gain control unit 184 controls the gain of the luminance gain unit 103 for the luminance signal and the gain of the color difference gain unit 107 for the color difference signal based on the input information input via the operation unit 19.

The optical system control unit 34 controls the drive of the optical system drive unit 14 based on the processing results of the AE processing unit 61 and the processing results of the AF processing unit 62. The optical system control unit 34 includes an AF control unit 191, a zoom control unit 192, and an aperture control unit 193. The AF control unit 191 drives the AF motor 41 based on the processing results of the AF processing unit 62. The AF control unit 191 can use the AF evaluation value as the processing result of the AF processing unit 62. The zoom control unit 192 drives the zoom motor 42 based on the zoom operation of the operation unit 19. The aperture control unit 193 drives the aperture motor 43 based on the processing results of the AE processing unit 61. The aperture control unit 193 can use the AE evaluation value as the processing result of the AE processing unit 61.

The LCD driver 35 drives the LCD 15. The LCD driver 35 converts the image data processed by the image processing unit 31 and the image data expanded by the compression/expansion unit 64 into a video signal, and causes the LCD 15 to display an image based on this video signal.

The storage medium control unit 36 controls the reading and writing of data from the storage medium 16. The flash memory control unit 37 controls the reading and writing of data from the flash memory 17. The SDRAM control unit 38 controls the reading and writing of data from the SDRAM 18.

The AE processing unit 61 calculates an AE evaluation value for each predetermined area of the image data generated by the solid-state imaging device 12. The AF processing unit 62 calculates an AF evaluation value for each predetermined area of the image data generated by the solid-state imaging device 12.

The sequence control unit 63 systematically controls the processing of the imaging device. At this time, the sequence control unit 63 can control a series of flows from when the image data generated by the solid-state imaging device 12 is image-processed to when it is displayed on the LCD 15. The sequence control unit 63 can also control a series of flows from when the image data generated by the solid-state imaging device 12 is image-processed to when it is compressed by the compression/expansion unit 64 to when it is stored in the storage medium 16. The sequence control unit 63 can also perform interrupt processing based on the operation of the operation unit 19.

The compression/expansion unit 64 compresses and expands the image data processed by the image processing unit 31 using a compression method such as the JPEG (Joint Photographic Experts Group) method.

The optical system driving unit 14 drives the optical system 11 based on control from the optical system control unit 34. The optical system driving unit 14 includes an AF motor 41, a zoom motor 42, and an aperture motor 43. The AF motor 41 moves the focus lens 21 in the optical axis direction based on control from the AF control unit 191. The zoom motor 42 moves the zoom lens 22 in the optical axis direction based on control from the zoom control unit 192. The aperture motor 43 adjusts the opening diameter of the aperture 23 based on control from the aperture control unit 193.

The LCD 15 displays captured images and various information that supports the imaging operation.

The storage medium 16 stores images captured by the imaging device. The storage medium 16 may be removable. The storage medium 16 may be, for example, a memory card or a USB (Universal Serial Bus) memory.

The flash memory 17 stores various control programs executed by the controller 13 and parameters used to execute the various control programs.

SDRAM 18 temporarily stores data generated by the processing of controller 13. SDRAM 18 may also include a buffer memory that stores one frame's worth of image data.

The operation unit 19 provides a user interface for operating the imaging device. The operation unit 19 may include, for example, buttons, dials, and switches provided on the imaging device. The operation unit 19 may be configured as a touch panel together with the LCD 15. Note that, depending on the form of the camera, some of the above-mentioned functions may not be included, and conversely, the camera may further include functions that are not disclosed.

Figure 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment.

In the figure, the solid-state imaging device 12 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel 120 can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel 120 is connected to a horizontal drive line 131 for each row, and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel 120 for each row when reading out a signal from each pixel 120. The vertical signal line 132 transmits a potential based on a current flowing when reading out a signal from the pixel 120 to the column signal processing unit 114 for each column.

The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured using a vertical register.

When reading out a signal from each pixel 120, the column readout circuit 113 can form a source follower with each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120.

The column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output the imaging signal Gout.

The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read out from the pixel 120 and the reference signal.

The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.

Figure 3 shows an example of the configuration of a signal readout circuit for one column according to the first embodiment.

In the figure, the pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion 126. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion 126 via the transfer transistor 122. The floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123. The power supply Vdd is connected to the vertical signal line 132 via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion 126.

A transfer signal TG is applied to the gate of the transfer transistor 122. A reset signal RT is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TG, reset signal RT, and selection signal SEL can be transmitted to each pixel 120 via the horizontal drive line 131 in FIG. 2.

The amplification transistor 124 is connected to the vertical signal line 132 via the selection transistor 125. In addition, a capacitance 133 is added to the vertical signal line 132. This capacitance 133 may be a parasitic capacitance of the vertical signal line 132, or may be a capacitive element connected to the vertical signal line 132.

A load transistor 142 is also connected to the vertical signal line 132. The load transistor 142 can form a source follower between the pixel 120 and the vertical signal line 132. The load transistor 142 can set a current I0 flowing through the vertical signal line 132 based on the source follower formed between the pixel 120 and the load transistor 142. At this time, the potential of the vertical signal line 132 changes according to the current I0 flowing based on the source follower formed between the pixel 120 and the load transistor 142. For example, a MOS transistor can be used as the load transistor 142. A gate voltage VG is applied to the gate of the load transistor 142.

The vertical signal line 132 is also connected to the inverting input of the comparator 148. At this time, the potential VSL of the vertical signal line 132 is applied to the inverting input of the comparator 148. A reference signal RAP is input to the non-inverting input of the comparator 148. The reference signal RAP is, for example, a ramp signal.

The comparator 148 also receives an auto-zero signal AZ. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. In the auto-zero operation, the charge stored in the capacitance of the comparator 148 can be controlled so that the non-inverting input and the inverting input are balanced. The comparator 148 can be provided for each column in the column ADC unit 114A.

The sample and hold transistor 144 causes the sample and hold capacitance 145 to sample and hold the charge that generates the bias voltage applied to the gate of the load transistor 142. The sample and hold transistor 144 may be a MOS transistor. A sample and hold signal SH is applied to the gate of the sample and hold transistor 144. The sample and hold capacitance 145 generates a sample and hold voltage. At this time, the sample and hold capacitance 145 sets a bias voltage to be applied to the gate of the load transistor 142 based on the sample and hold voltage, and applies it to the gate of the load transistor 142. The sample and hold transistor 144 is connected in series to the gate of the load transistor 142. The sample and hold capacitance 145 is connected in parallel to the gate of the load transistor 142. Here, the charge that generates the bias voltage applied to the gate of the load transistor 142 is sampled and held in the sample and hold capacitance 145, and then the bias voltage is applied to the gate of the load transistor 142, thereby preventing horizontal noise during AD conversion.

The boost circuit 146 is connected to the gate of the load transistor 142 via a coupling capacitance 147. The boost circuit 146 boosts the gate voltage VG of the load transistor 142 during at least a part of the settling period of the vertical signal line 132. At this time, the boost circuit 146 outputs a boosted voltage VIN during at least a part of the settling period, and can add it to the bias voltage set by the sample and hold capacitance 145 and apply it to the gate of the load transistor 142. The settling period is the period from when the potential of the floating diffusion 126 is applied to the vertical signal line 132 until the potential of the vertical signal line 132 converges.

Alternatively, the boost circuit 146 may boost the gate voltage VG of the load transistor 142 outside the signal readout period from the pixel 120. In this case, the boosting period of the gate voltage VG of the load transistor 142 can be set separately from the signal readout period from the pixel 120.

Here, by boosting the gate voltage VG of the load transistor 142, it is possible to increase the current I0 flowing through the vertical signal line 132, thereby shortening the settling time. This settling time Ts can be given by the following equation.
Ts=Cv/I0+Cv/gm
Here, Cv is the capacitance value of the capacitor 133 , and gm is the mutual conductance of the load transistor 142 .

Here, gm can be given by the following formula:
gm=(2・I0・β) ^1/2
Here, β is a value corresponding to the driving force of the load transistor 142 .

Therefore, an increase in the current I0 flowing through the vertical signal line 132 contributes to both the first and second terms of the equation for the settling time Ts, and can contribute to an increased effect of shortening the settling time.

The gate of the load transistor 142 is connected to the gate of the mirror transistor 141 via the sample-and-hold transistor 144. The mirror transistor 141 may be a MOS transistor. The mirror transistor 141 generates a mirror current based on a current mirror operation. At this time, the mirror transistor 141 operates as the mirror source of the current mirror circuit, and the load transistor 1421 can operate as the mirror destination of the current mirror circuit. A current source 143 is connected in series to the mirror transistor 141. The gate of the mirror transistor 141 is connected to the drain of the mirror transistor 141.

When the gate voltage VG of the load transistor 142 is boosted, the sample and hold transistor 144 can be turned off. At this time, the gate of the load transistor 142 is separated from the gate of the mirror transistor 141. Therefore, the load on the boost circuit 146 can be reduced when the gate voltage VG of the load transistor 142 is boosted, and the effect of shortening the settling time can be increased while suppressing an increase in the circuit size of the boost circuit 146.

Figure 4 is a timing chart showing an example of waveforms at various parts during signal readout of the solid-state imaging device according to the first embodiment.

In the figure, when the sample and hold transistor 144 is turned on, the charge that generates the bias voltage applied to the gate of the load transistor 142 is sampled and held in the sample and hold capacitor 145.

Next, the reset signal RT rises (t1), and the reset period K11 begins. At this time, the reset transistor 123 turns on, and the floating diffusion 126 is reset. In addition, the selection signal SEL rises, and the selection transistor 125 turns on. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the power supply potential Vdd is applied to the gate of the amplification transistor 124.

In addition, during the reset period K11, the sample and hold transistor 144 is turned off. At this time, the gate of the load transistor 142 is disconnected from the gate of the mirror transistor 141 while a bias voltage is applied to the gate of the load transistor 142 via the sample and hold capacitance 145. Here, during the reset period K11, the boost voltage VIN is set to 0V, and only the bias voltage set by the sample and hold capacitance 145 is applied to the gate of the load transistor 142. At this time, the increase in the gate voltage VG of the load transistor 142 is suppressed, and the increase in the current I0 flowing through the vertical signal line 132 via the load transistor 142 is also suppressed. As a result, the increase in power consumption during the reset period K11 can be suppressed.

Next, the reset signal RT falls (t2), and the P-phase settling period K12 begins. At this time, the reset transistor 123 turns off, and the potential VSL of the vertical signal line 132 is set based on the source follower operation when the reset level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.

The boost voltage VIN also rises (t2), is added to the bias voltage set by the sample-and-hold capacitor 145, and is applied to the gate of the load transistor 142. At this time, the gate voltage VG of the load transistor 142 rises compared to the reset period K11, and the current I0 flowing to the vertical signal line 132 via the load transistor 142 also rises. Therefore, compared to when the boost voltage VIN is not applied (PV1), the potential VSL of the vertical signal line 132 converges faster (PV2), and the P-phase settling period K12 is shortened.

Next, the auto-zero signal AZ rises (t3), and charge is accumulated in the capacitance of the comparator 148 so that the non-inverting input and the inverting input of the comparator 148 are balanced.

Next, the P-phase setting signal PT falls in a spike shape (t4), and the reference signal RAP rises. Then, the P-phase AD enable signal rises (t5), and a ramp signal is supplied to the comparator 148 as the reference signal RAP. Then, in the comparator 148, the potential VSL of the vertical signal line 132 corresponding to the reset level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is output as the comparison result VO. At this time, the reset level read out from the pixel 120 is AD converted based on the counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.

Next, the P-phase AD enable signal falls (t6), completing the P-phase AD conversion process and ending the P-phase settling period K12.

The boost voltage VIN also falls (t6), and only the bias voltage set by the sample and hold capacitor 145 is applied to the gate of the load transistor 142. At this time, the gate voltage VG of the load transistor 142 is set to be equal to the gate voltage VG of the reset period K11, and the current I0 flowing through the vertical signal line 132 via the load transistor 142 is also set to be equal to the current I0 of the reset period K11.

Next, the transfer signal TG rises (t7) and the readout period K13 begins. At this time, the transfer transistor 122 turns on and the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126. In addition, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124. Here, in the readout period K13, the boost voltage VIN is set to 0V, and only the bias voltage set by the sample hold capacitance 145 is applied to the gate of the load transistor 142. At this time, the increase in the gate voltage VG of the load transistor 142 is suppressed, and the increase in the current I0 flowing through the vertical signal line 132 via the load transistor 142 is also suppressed. Therefore, the increase in power consumption during the readout period K13 can be suppressed.

Next, the transfer signal TG falls (t8) and transitions to the D-phase settling period K14. At this time, the transfer transistor 122 is turned off, and the potential VSL of the vertical signal line 132 is set based on the source follower operation when the signal level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.

The boost voltage VIN also rises (t8), is added to the bias voltage set by the sample and hold capacitance 145, and is applied to the gate of the load transistor 142. At this time, the gate voltage VG of the load transistor 142 rises compared to the read period K13, and the current I0 flowing to the vertical signal line 132 via the load transistor 142 also rises. Therefore, compared to when the boost voltage VIN is not applied (DV1), the potential VSL of the vertical signal line 132 converges faster (DV2), and the D-phase settling period K14 is shortened.

Next, the D-phase setting signal DT falls in a spike shape (t9), and the reference signal RAP rises. Then, the D-phase AD enable signal rises (t10), and a ramp signal is supplied to the comparator 148 as the reference signal RAP. Then, in the comparator 148, the potential VSL of the vertical signal line 132 corresponding to the signal level is compared with the reference signal RAP, and the timing when the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 is output as the comparison result VO. At this time, the signal level read out from the pixel 120 is AD converted based on the counting operation until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132.

Next, the D-phase AD enable signal falls (t11), the D-phase AD conversion process is completed, and the D-phase settling period K14 ends. The boost voltage VIN also falls (t11), and only the bias voltage set by the sample-and-hold capacitance 145 is applied to the gate of the load transistor 142.

Figure 5 shows an example of the configuration of a signal readout circuit for multiple columns according to the first embodiment.

In the figure, vertical signal lines 132-1 to 132-3 and comparators 148-1 to 148-3 are provided for each column. In addition, pixels 120-1 to 120-3 are connected to each of the vertical signal lines 132-1 to 132-3, respectively.

In addition, load transistors 142-1 to 142-3 are connected to the vertical signal lines 132-1 to 132-3, respectively. Each of the load transistors 142-1 to 142-3 can form a source follower between each of the pixels 120-1 to 120-3 via the vertical signal lines 132-1 to 132-3, respectively.

Furthermore, each of the vertical signal lines 132-1 to 132-3 is connected to the inverting input of each of the comparators 148-1 to 148-3. At this time, the potentials VSL1 to VSL3 of each of the vertical signal lines 132-1 to 132-3 are applied to the inverting input of each of the comparators 148-1 to 148-3. A reference signal RAP is input to the non-inverting input of each of the comparators 148-1 to 148-3. Furthermore, an auto-zero signal AZ is input to each of the comparators 148-1 to 148-3.

In addition, sample and hold transistors 144-1 to 144-3 are connected in series to the gates of the load transistors 142-1 to 142-3, respectively. A sample and hold signal SH is applied to the gates of the sample and hold transistors 144-1 to 144-3. In addition, sample and hold capacitors 145-1 to 145-3 are connected in parallel to the gates of the load transistors 142-1 to 142-3, respectively.

The boost circuit 146 is connected to the gates of the load transistors 142-1 to 142-3 via coupling capacitances 147-1 to 147-3, respectively. The boost circuit 146 can boost the gate voltages of the load transistors 142-1 to 142-3 during at least a portion of the settling period of each of the vertical signal lines 132-1 to 132-3. In this case, the boost circuit 146 can be shared by multiple columns.

The gates of the load transistors 142-1 to 142-3 are connected to the gate of the mirror transistor 141 via the sample-and-hold transistors 144-1 to 144-3, respectively. The mirror transistor 141 is connected in series to the current source 143. In this case, the mirror transistor 141 and the current source 143 can be shared by multiple columns.

Here, the coupling capacitances 147-1 to 147-3 may be accommodated by changing the capacitance ratio of the sample and hold capacitances 145-1 to 145-3. In this case, the gate voltage of each of the load transistors 142-1 to 142-3 can be boosted based on the area increase of one wiring, and an increase in the chip size of the solid-state imaging device can be suppressed.

In this way, in the first embodiment described above, the gate voltage VG of the load transistor 142 is boosted via the coupling capacitance 147 during the P-phase settling periods K12 and K14 of the vertical signal line 132. This makes it possible to reduce the current I0 during the reset period K11 and read period K13 compared to the current I0 during the settling periods K12 and K14 without affecting the settling time. Therefore, it is possible to shorten the settling periods K12 and K14 while suppressing an increase in power consumption of the signal read circuit.

2. Second embodiment
In the above-described first embodiment, the gate voltage VG of the load transistor 142 is boosted via the coupling capacitance 147 during the P-phase settling periods K12 and K14 of the vertical signal line 132. In this second embodiment, the gate voltage VG of the load transistor 142 is boosted via the coupling variable capacitance 247 during the P-phase settling periods K12 and K14 of the vertical signal line 132.

Figure 6 shows an example of the configuration of a signal readout circuit for one column according to the second embodiment.

In the figure, this imaging device has a variable coupling capacitance 247 instead of the coupling capacitance 147 of the first embodiment described above. The rest of the configuration of the imaging device of the second embodiment is the same as the configuration of the imaging device of the first embodiment described above.

The coupling variable capacitance 247 has a variable capacitance value. The coupling variable capacitance 247 is connected between the gate of the load transistor 142 and the output of the boost circuit 146. Here, by changing the capacitance value of the coupling variable capacitance 247, the boost amount of the gate voltage VG of the load transistor 142 can be changed. For example, when the frame rate of the imaging device is increased, the boost amount of the gate voltage VG of the load transistor 142 may be increased, and when the power consumption of the imaging device is reduced, the boost amount of the gate voltage VG of the load transistor 142 may be decreased. The imaging device may change the capacitance value of the coupling variable capacitance 247 according to the usage environment and imaging conditions, or may change the capacitance value of the coupling variable capacitance 247 based on an external setting.

In this manner, in the second embodiment described above, the coupling variable capacitance 247 is connected between the gate of the load transistor 142 and the output of the boost circuit 146. This makes it possible to change the amount of boost of the gate voltage VG of the load transistor 142, thereby optimizing the priority between shortening the settling time and reducing power consumption.
3. Third embodiment
In the above-described first embodiment, the gate voltage VG of the load transistor 142 is boosted via the coupling capacitance 147 during the P-phase settling periods K12 and K14 of the vertical signal line 132. In this third embodiment, the boost voltage VIN that boosts the gate voltage VG of the load transistor 142 via the coupling capacitance 147 during the P-phase settling periods K12 and K14 of the vertical signal line 132 is made variable.

Figure 7 shows an example of the configuration of a signal readout circuit for one column according to the third embodiment.

In the figure, this imaging device has a variable boost circuit 346 instead of the boost circuit 146 of the first embodiment described above. The rest of the configuration of the imaging device of the third embodiment is the same as the configuration of the imaging device of the first embodiment described above.

The variable boost circuit 346 has a variable voltage boost amount. The variable boost circuit 346 is connected to the gate of the load transistor 142 via the coupling capacitance 147. The variable boost circuit 346 boosts the gate voltage VG of the load transistor 142 during at least a part of the settling period of the vertical signal line 132. Here, the boost amount of the gate voltage VG of the load transistor 142 can be changed by changing the voltage boost amount of the variable boost circuit 346. For example, when the frame rate of the imaging device is increased, the voltage boost amount of the variable boost circuit 346 may be increased, and when the power consumption of the imaging device is reduced, the voltage boost amount of the variable boost circuit 346 may be decreased. The imaging device may change the voltage boost amount of the variable boost circuit 346 according to the usage environment and imaging conditions, or may change the voltage boost amount of the variable boost circuit 346 based on an external setting.

In this manner, in the above-described third embodiment, the variable boost circuit 346 is connected to the gate of the load transistor 142 via the coupling capacitance 147. This makes it possible to change the boost amount of the gate voltage VG of the load transistor 142, thereby optimizing the priority between shortening the settling time and reducing power consumption.
4. Fourth embodiment
In the above-described first embodiment, the gate voltage VG of the load transistor 142 is boosted via the coupling capacitance 147 during the P-phase settling periods K12 and K14 of the vertical signal line 132. In this fourth embodiment, the gate voltage VG of the load transistor 142 is boosted via the coupling capacitance 447 that also serves as a sample and hold capacitance during the P-phase settling periods K12 and K14 of the vertical signal line 132.

Figure 8 shows an example of the configuration of a signal readout circuit for one column according to the fourth embodiment.

In the figure, this imaging device has a coupling capacitance 447 instead of the coupling capacitance 147 of the first embodiment described above. In addition, this imaging device does not have the sample-and-hold capacitance 145 of the first embodiment described above. The rest of the configuration of the imaging device of the fourth embodiment is the same as the configuration of the imaging device of the first embodiment described above.

The coupling capacitance 447, which also serves as the sample-and-hold capacitance 145, capacitively couples the gate of the load transistor 142 with the boost circuit 146. The coupling capacitance 447 is connected between the gate of the load transistor 142 and the output of the boost circuit 146.

When the sample and hold transistor 144 is turned on, the coupling capacitance 447 samples and holds the charge that generates the bias voltage applied to the gate of the load transistor 142. When the sample and hold transistor 144 is turned off, the coupling capacitance 447 capacitively couples the gate of the load transistor 142 with the boost circuit 146 and applies a bias voltage to the gate of the load transistor 142.

In this manner, in the above-described fourth embodiment, the coupling capacitance 447 is connected between the gate of the load transistor 142 and the output of the boost circuit 146. This makes it possible to shorten the settling periods K12 and K14 while suppressing an increase in power consumption of the signal readout circuit, and also makes it possible to remove the sample-and-hold capacitance 145. This makes it possible to control the balance between shortening the settling time and reducing power consumption while suppressing an increase in the circuit scale.
<5. Fifth embodiment>
In the above-described first embodiment, the gate voltage VG of the load transistor 142 is boosted via the coupling capacitance 147 during the P-phase settling periods K12 and K14 of the vertical signal line 132. In the fifth embodiment, the gate voltage VG of the load transistor 142 is boosted via the coupling variable capacitance 547 that also serves as a sample and hold capacitance during the P-phase settling periods K12 and K14 of the vertical signal line 132.

Figure 9 shows an example of the configuration of a signal readout circuit for one column according to the fifth embodiment.

In the figure, this imaging device has a variable coupling capacitance 547 instead of the coupling capacitance 147 of the first embodiment described above. The rest of the configuration of the imaging device of the fifth embodiment is the same as the configuration of the imaging device of the first embodiment described above.

The coupling variable capacitance 547 capacitively couples the gate of the load transistor 142 with the boost circuit 146 while also serving as the sample-and-hold capacitance 145. The coupling variable capacitance 547 has a variable capacitance value. The coupling variable capacitance 547 is connected between the gate of the load transistor 142 and the output of the boost circuit 146. Here, by changing the capacitance value of the coupling variable capacitance 547, the boost amount of the gate voltage VG of the load transistor 142 can be changed. For example, when the frame rate of the imaging device is increased, the boost amount of the gate voltage VG of the load transistor 142 may be increased, and when the power consumption of the imaging device is reduced, the boost amount of the gate voltage VG of the load transistor 142 may be decreased. The imaging device may change the capacitance value of the coupling variable capacitance 547 according to the usage environment and imaging conditions, or may change the capacitance value of the coupling variable capacitance 547 based on an external setting.

When the sample and hold transistor 144 is turned on, the coupling variable capacitance 547 samples and holds the charge that generates the bias voltage applied to the gate of the load transistor 142. When the sample and hold transistor 144 is turned off, the coupling variable capacitance 547 capacitively couples the gate of the load transistor 142 with the boost circuit 146 and applies a bias voltage to the gate of the load transistor 142.

In this manner, in the above-described fifth embodiment, a coupling variable capacitance 547 is connected between the gate of the load transistor 142 and the output of the boost circuit 146. This makes it possible to change the boost amount of the gate voltage VG of the load transistor 142 and to eliminate the sample-and-hold capacitance 145. This makes it possible to optimize the priority of shortening the settling time and reducing power consumption while suppressing an increase in circuit size.

6. Sixth embodiment
In the first embodiment described above, the gate voltage VG of the load transistor 142 is boosted via the coupling capacitance 147 during the P-phase settling periods K12 and K14 of the vertical signal line 132. In this sixth embodiment, semiconductor chips each having a pixel array portion in which pixels are arranged in a matrix are stacked.

Figure 10 is a perspective view showing an example of the stacking of a pixel array unit according to the sixth embodiment.

In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on semiconductor chip 921.

A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the periphery of the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. The column readout circuit 925 may be provided with a signal readout circuit according to any one of the first to fifth embodiments described above.

The semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding may be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on a Cu-Cu connection. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

In this manner, in the sixth embodiment described above, the semiconductor chip 922 in which the pixel array section 923 is formed is stacked on the semiconductor chip 921 in which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of the semiconductor chip in which the solid-state imaging device is formed.

<7. Examples of applications to moving objects>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

Figure 11 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 11, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, the functional configuration of the integrated control unit 12050 includes a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device for generating a drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.

The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020. The body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.

The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

The microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

The microcomputer 12051 can also perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

The microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.

The audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of FIG. 11, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

Figure 12 shows an example of the installation position of the imaging unit 12031.

In FIG. 12, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

In addition, FIG. 12 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer 12051 can extract, as a preceding vehicle, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster) by calculating the distance to each three-dimensional object within the imaging range 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set the distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on the driver's operation.

For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

An example of a vehicle control system to which the technology disclosed herein can be applied has been described above. The technology disclosed herein can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, the imaging device of the above-mentioned embodiment can be applied to the imaging unit 12031. By applying the technology disclosed herein to the vehicle control system 12000, it is possible to control the balance between shortening the settling time and reducing power consumption.

The above-described embodiment shows an example for realizing the present technology, and there is a corresponding relationship between the matters in the embodiment and the matters specifying the invention in the claims. Similarly, there is a corresponding relationship between the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name. However, the present technology is not limited to the embodiment, and can be realized by making various modifications to the embodiment without departing from the gist of the technology. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

The present technology can also be configured as follows.
(1) a load transistor that reads out a signal from a pixel based on a source follower operation between the pixel and a vertical signal line;
a boost circuit that boosts the gate voltage of the load transistor during at least a part of a settling period of the vertical signal line.
(2) The imaging device according to (1), wherein the boost voltage applied to the gate electrode from the boost circuit is variable.
(3) a sample-and-hold transistor connected in series to the gate of the load transistor;
The imaging device according to (1) or (2), further comprising a coupling capacitance connected in parallel to a gate of the load transistor.
(4) The imaging device according to any one of (1) to (3), wherein the coupling capacitance is variable.
(5) The imaging device according to (3) or (4), wherein the coupling capacitance also serves as a sample-and-hold capacitance that samples and holds in the sample-and-hold transistor.
(6) The imaging device according to (3) or (4), further comprising a sample and hold capacitance connected in parallel to the gate of the load transistor.
(7) The pixel is
A photodiode;
a transfer transistor that transfers the charge stored in the photodiode to a floating diffusion;
a reset transistor that resets the floating diffusion;
an amplifying transistor that outputs a signal according to the potential of the floating diffusion;
The imaging device according to any one of (1) to (6), further comprising a selection transistor connected between the amplification transistor and the vertical signal line.
(8) The imaging device according to (7), wherein the settling period is a period from when a potential of the floating diffusion is applied to the vertical signal line until the potential of the vertical signal line converges.
(9) The imaging device according to (8), wherein the settling period includes a period from after a reset period of the pixel has elapsed until a P-phase AD conversion period.
(10) The imaging device according to (9), wherein the boost circuit makes the gate voltage of the load transistor higher during the settling period than the gate voltage of the load transistor during the reset period.
(11) The imaging device according to any one of (8) to (10), wherein the settling period includes a period from after a signal readout period from the pixel has elapsed to a D-phase AD conversion period.
(12) The imaging device according to (11), wherein the boost circuit makes the gate voltage of the load transistor higher during the settling period than the gate voltage of the load transistor during the signal readout period.
(13) A pixel array section in which the pixels are arranged in a matrix in row and column directions,
the coupling capacitance is provided for each of the columns,
The imaging device according to any one of (1) to (12), wherein the boost circuit is shared by a plurality of columns.
(14) A load transistor that reads out a signal from the pixel based on a source follower operation between the pixel and a vertical signal line;
a boost circuit that boosts the gate voltage of the load transistor outside a period in which a signal is read from the pixel.
(15) The imaging device according to (14), wherein a boosting period of the gate voltage of the load transistor is set separately from a signal readout period from the pixel.
(16) reading out a signal from the pixel based on a source follower operation between the pixel and a load transistor via a vertical signal line;
The imaging method includes boosting the gate voltage of the load transistor during at least a part of a settling period of the vertical signal line.
(17) The imaging method according to (16), wherein the gate voltage of the load transistor is boosted via a coupling capacitance.
(18) turning on a sample-and-hold transistor connected to the gate of the load transistor, and storing charges in a sample-and-hold capacitor to generate a bias voltage to be applied to the gate of the load transistor;
The imaging method according to (17), further comprising the steps of: turning off the sample-and-hold transistor; and boosting the gate voltage of the load transistor via the coupling capacitance.

REFERENCE SIGNS LIST 111 pixel array section 112 vertical scanning circuit 113 column readout circuit 114 column signal processing section 115 horizontal scanning circuit 116 control circuit 121 photodiode 122 transfer transistor 123 reset transistor 124 amplifying transistor 125 selection transistor 126 floating diffusion 131 horizontal drive line 132 vertical signal line 141 mirror transistor 142 load transistor 143 current source 144 sample hold transistor 145 sample hold capacitance 146 boost circuit 147 coupling capacitance 148 comparator

Claims (18)

a load transistor for reading out a signal from the pixel based on a source follower operation between the pixel and the vertical signal line;
a boost circuit that boosts the gate voltage of the load transistor during at least a part of a settling period of the vertical signal line. 2. The image pickup device according to claim 1, wherein the boosted voltage applied to the gate electrode from the boost circuit is variable. a sample and hold transistor connected in series to the gate of the load transistor;
The imaging device according to claim 1 , further comprising a coupling capacitance connected in parallel to the gate of the load transistor. The imaging device according to claim 1 , wherein the coupling capacitance is variable. 4. The image pickup device according to claim 3, wherein the coupling capacitance also serves as a sample-and-hold capacitance for sampling and holding by the sample-and-hold transistor. The imaging device according to claim 3 , further comprising a sample and hold capacitor connected in parallel to the gate of the load transistor. The pixel is
A photodiode;
a transfer transistor that transfers the charge stored in the photodiode to a floating diffusion;
a reset transistor that resets the floating diffusion;
an amplifying transistor that outputs a signal according to the potential of the floating diffusion;
The image pickup device according to claim 1 , further comprising a selection transistor connected between the amplification transistor and the vertical signal line. The image pickup device according to claim 7 , wherein the settling period is a period from when the potential of the floating diffusion is applied to the vertical signal line until the potential of the vertical signal line converges. The imaging device according to claim 8 , wherein the settling period includes a period from after a reset period of the pixel has elapsed until a P-phase AD conversion period. The imaging device according to claim 9 , wherein the boost circuit makes the gate voltage of the load transistor higher during the settling period than the gate voltage of the load transistor during the reset period. The imaging device according to claim 8 , wherein the settling period includes a period from after a signal readout period from the pixel has elapsed until a D-phase AD conversion period. The imaging device according to claim 11 , wherein the boost circuit makes the gate voltage of the load transistor higher during the settling period than the gate voltage of the load transistor during the signal readout period. a pixel array section in which the pixels are arranged in a matrix in a row direction and a column direction;
the coupling capacitance is provided for each of the columns,
The imaging device according to claim 3 , wherein the boost circuit is shared by a plurality of columns. a load transistor for reading out a signal from the pixel based on a source follower operation between the pixel and the vertical signal line;
a boost circuit that boosts the gate voltage of the load transistor outside a period in which a signal is read from the pixel. The imaging device according to claim 14 , wherein a boosting period for the gate voltage of the load transistor is set separately from a signal readout period from the pixel. reading out a signal from the pixel based on a source follower operation between the pixel and a load transistor via a vertical signal line;
The imaging method includes boosting the gate voltage of the load transistor during at least a part of a settling period of the vertical signal line. The imaging method according to claim 16, wherein the gate voltage of the load transistor is boosted via a coupling capacitance. A sample and hold transistor connected to the gate of the load transistor is turned on, and a charge that generates a bias voltage to be applied to the gate of the load transistor is stored in a sample and hold capacitor;
18. The imaging method according to claim 17, further comprising the step of: boosting the gate voltage of the load transistor via the coupling capacitance after the sample-and-hold transistor is turned off.

Images