JP2024046239A - Memory system and control method - Google Patents

Abstract

To provide a memory system capable of maintaining data such as a previously written low-order page even when an instantaneous interruption occurs in the middle of a program during writing of high-order pages of a multi-value memory and the like, and a control method.SOLUTION: A memory system comprises: a non-volatile storage unit configured by arranging a plurality of memory cells which include a plurality of pages and which can store multi-value data; a correction processing unit which can error-correct the data stored in the storage unit in units of pages; and a controller which writes multi-value data in the storage unit and reads the written multi-value data from the storage unit. The controller manages the storage positions of the multi-value data stored in the storage unit, detects only the lowest-order pages in which data is stored among the plurality of pages, causes the correction processing unit to generate an error correction code which treats all the detected pages as one frame, and writes an error correction code in a page which can be written following a page constituting one page among the lowest-order pages.SELECTED DRAWING: Figure 5B

Description

This embodiment relates to a memory system and a control method.

Non-volatile memory is used for data storage in memory systems such as solid state drives (SSDs). For example, NAND-type flash memory, known as a non-volatile memory, is capable of storing two or more bits of data (multi-value storage) in one memory cell. However, in order to achieve multi-value storage, it is necessary to control each of multiple threshold distributions (four threshold distributions in the case of four values) corresponding to multiple multi-value data (two-bit data "00", "01", "10", and "11" in the case of four values) so that they fall within a predetermined range. For this reason, as the number of bits to be stored increases, it is necessary to control the threshold distribution corresponding to one piece of data within a narrower range.

For example, when writing to a memory cell that stores four values, writing is performed to the lower page and then to the upper page, storing two bits (four values) of data. In this series of program operations from the lower page to the upper page, if writing is interrupted during writing to the upper page due to an abnormal power interruption (hereinafter also referred to as a momentary power outage), the data in the lower page that was written earlier may also be destroyed as a result. Data destruction due to a momentary power outage like this can also occur in other multi-value storage methods such as 8-value storage and 16-value storage.

U.S. Pat. No. 10,110,255

An embodiment of the present invention provides a memory system and a control method that can maintain the data of the lower page written earlier even if an instantaneous power failure occurs in the middle of a program such as writing an upper page of a multilevel memory. provide.

According to an embodiment of the present invention, a non-volatile memory unit having multiple pages and configured with multiple memory cells capable of storing multi-value data is provided, a correction processing unit capable of error correcting data stored in the memory unit on a page-by-page basis, and a controller that writes multi-value data to the memory unit and reads the multi-value data written from the memory unit. The controller manages the storage location of the multi-value data stored in the memory unit, detects a page in which data is stored only in the lowest page of the multiple pages, causes the correction processing unit to generate an error correction code with all the detected pages as one frame, and writes the error correction code to a page that can be written to following the page that constitutes one frame of the lowest page.

FIG. 1 is a block diagram showing a configuration of a memory system according to an embodiment. FIG. 2 is a block diagram showing a configuration of an encoder/decoder unit of a memory system according to an embodiment. FIG. 3 is an equivalent circuit diagram showing the configuration of a memory block of a NAND flash memory chip of the memory system according to the embodiment. 7 is a flowchart for explaining the operation of the memory system according to the embodiment. FIG. 3 is a diagram for explaining a page-by-page write operation in the memory system according to the embodiment. FIG. 3 is a diagram for explaining a page-by-page write operation in the memory system according to the embodiment. 7 is a flowchart showing the operation of a memory system of a comparative example. 11 is a diagram for explaining a page-by-page write operation in a memory system of a comparative example. 11 is a diagram for explaining a page-by-page write operation in a memory system of a comparative example.

(Configuration of embodiment)
Hereinafter, an example of a memory system according to an embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, error correction is performed on a written lower block that is susceptible to data destruction during writing of an upper block (including immediately before or during writing). This makes it possible to restore data even if an instantaneous power failure occurs during writing, such as an abnormal power cutoff, and the data is destroyed as a result of the lower block being affected.

FIG. 1 shows the configuration of an example of a memory system 1 applicable to an embodiment of the present invention. In the example of FIG. 1, the memory system 1 includes a host interface (I/F) 10, a buffer memory 11, a memory controller 12, and a flash memory unit 13.

The host interface 10 is an interface between the memory system 1 and a host 14 connected to the memory system 1. The host 14 is, for example, an information processing device such as a personal computer (PC). Examples of the host interface 10 include SCSI, Serial Attached SCSI (SAS), ATA, Serial ATA (SATA), PCI Express (PCIe) (registered trademark), Ethernet (registered trademark), Fiber channel, NVM Express (N VMe)( (registered trademark) etc. may be used.

The buffer memory 11 includes a write buffer 11A that temporarily holds write data input from the host 14 via the host interface 10, and a write buffer 11A that temporarily holds write data input from the host 14 via the host interface 10, and a write buffer 11A that temporarily holds write data input from the host 14 via the host interface 10, and a write buffer 11A that temporarily holds write data input from the host 14 via the host interface 10. It has a read buffer 11B that holds data. The memory controller 12 includes, for example, a CPU (Central Processing Unit) (not shown), controls the host interface 10 and the buffer memory 11, writes data to the flash memory section 13, and writes data from the flash memory section 13. Perform reading.

The memory controller 12 may receive a command requesting flush processing (hereinafter referred to as a "flash command") from the host 14. The flash process is a process in which the host 14 requests the memory system 1 to make data nonvolatile, and is executed by a flash command from the host 14. When the memory system 1 receives a flash command from the host 14, it executes a process (also called non-volatile process) of writing unwritten data stored in the write buffer 11A to the NAND flash memory chip 23. The data up to the end of the unwritten data stored in the write buffer 11A when the flash command is issued becomes the target data of the non-volatile process corresponding to this flash command.

The flash memory section 13 includes a NAND flash controller (controller) 20 and a plurality of NAND flash memory chips (storage section) 23, and a plurality of encoders and decoders corresponding to each NAND flash memory chip 23. 22 (hereinafter referred to as the E/D section 22). The flash memory section 13 further includes a Reed-Solomon code encoder and decoder (hereinafter referred to as an RS-E/D section) 21. The NAND flash memory chip 23 writes bit data to a large number of memory cells arranged three-dimensionally within the chip, reads written data, or erases written data in blocks. It is configured so that it can be used.

The NAND flash controller 20 controls writing, reading, and erasing of the data in each NAND flash memory chip 23. Further, the NAND flash controller 20 controls the operation of each E/D section 22 and RS-E/D section 21. The NAND flash controller 20 can detect and manage data storage locations and pages where data is valid or invalid.

For example, when a predetermined amount of data (original data) is held in the write buffer 11A, the NAND flash controller 20 supplies data for a storage unit of the NAND flash memory chip 23 from the write buffer 11A to the E/D section 22. The write data is error-correction coded there, and stored in the NAND flash memory chip 23 under the control of the NAND flash controller 20. In addition, the NAND flash controller 20 executes writing to the NAND flash memory chip 23 when the memory controller 12 receives a flash command from the host 14.

When writing data, the RS-E/D unit (correction processing unit) 21 uses a Reed-Solomon code (hereinafter abbreviated as RS code) for input data (original data) input from the write buffer 11A. Perform error correction encoding. Further, when reading data, the RS code accompanying the data stored in the NAND flash memory chip 23 is decoded, and error correction is performed on the data. In this way, the RS-E/D unit 21 performs error correction encoding, error correction, etc. using data to be encoded and decoded. Note that in this embodiment, a Reed-Solomon code is generated to implement error correction, but the present invention is not limited to this. Since the error correction code only needs to be capable of erasure correction, XOR or the like may be used, for example. The RS code generated by the RS-E/D section 21 is supplied to the E/D section 22 under the control of the NAND flash controller 20.

When writing data, the E/D unit 22 generates a CRC (Cyclic Redundancy Check) code for the input data (original data) read from the write buffer 11A, and also generates a CRC (Cyclic Redundancy Check) code for the original data and the generated CRC code. Then, error correction encoding is performed using a systematic code such as a BCH (Bose-Chaudhuri-Hocquenghem) code. Further, when reading data, the BCH code accompanying the data stored in the NAND flash memory chip 23 is decoded to perform error correction, and the CRC code is decoded to find the error position. In this manner, the E/D unit 22 performs error correction encoding, error correction, etc. using data to be encoded and decoded, respectively.

Further, the E/D unit 22 generates a CRC code for the RS code generated by the RS-E/D unit 21, generates a BCH code for the RS code and the CRC code, and performs error correction encoding. .

Note that the code used for error correction encoding performed by the E/D unit 22 is not limited to the BCH code, but may be any other code as long as it is a systematic code. For example, an RS code or an LDPC (Low-Density Parity-Check) code may be used. Further, the CRC code is not limited to this, and other codes such as checksums may be used as long as they have sufficient error detection ability.

NAND flash memory chip 23 has a memory cell array. The memory cell array has a plurality of memory cells arranged in a matrix. The memory cell array of the NAND flash memory chip 23 includes a plurality of blocks (physical blocks). This block is a unit for erasing data. Each of the multiple blocks includes multiple pages. Each page is a unit for writing and reading data.

FIG. 2 shows an example of a detailed configuration of one E/D section 22 in the flash memory section 13. E/D section 22 includes a CRC encoder 26 and a BCH encoder 27, and a BCH decoder 28 and a CRC decoder 29.

When writing data, input data (original data) input to the E/D unit 22 for encoding is supplied to a CRC encoder 26 and a BCH encoder 27, respectively.

The CRC encoder 26 calculates the CRC of the supplied original data, and generates a CRC code, which is an error checking code, from the calculation result. The CRC code is supplied to the BCH encoder 27. The BCH encoder 27 generates a BCH code, which is an error correction code, from the original data and the CRC code supplied from the CRC encoder 26, and performs error correction encoding on the original data and the CRC code. The BCH code, original data, and CRC code are output from the E/D unit 22 and stored as data in a specified area of the NAND flash memory chip 23.

On the other hand, when reading data, the data that has been error correction coded using the BCH code is read from the NAND flash memory chip 23 and input to the BCH decoder 28 of the E/D unit 22. The BCH decoder 28 decodes the BCH code of the input data and corrects errors that can be corrected using the code correction capability of the BCH code. The CRC decoder 29 decodes the CRC code included in the output of the BCH decoder 28 to perform error checking. The output of the BCH decoder 28 and the error check result are output from the E/D unit 22 to the NAND flash controller 20.

The operation when reading data from the NAND flash memory chip 23 is roughly as follows. Data read from each NAND flash memory chip 23 is supplied to each E/D section 22. In the E/D unit 22, a BCH decoder 28 decodes the BCH code for the supplied data, performs error correction on the original data and the CRC code, and a CRC decoder 29 decodes the CRC code included in the output of the BCH decoder 28. Decode the code and perform error checking. The error-corrected original data and the error check results are supplied to the NAND flash controller 20 and the RS-E/D unit 21, respectively.

The RS-E/D unit 21 decodes the RS code, and performs error correction using the RS code on the original data that has been error-corrected using the BCH code output from the E/D unit 22 and on the RS code itself. administered. At this time, it is selected whether to perform normal error correction or erasure correction, depending on conditions regarding the number of errors, which will be described in detail later. If erasure correction is selected, the error-corrected original data is supplied to the NAND flash controller 20 as output data.

On the other hand, when it is selected to perform normal error correction, each E/D section 22 further applies a BCH code to the original data that has been subjected to error correction using an RS code by the RS-E/D section 21. Error correction will be performed. When all errors are corrected by this error correction, the error-corrected original data is supplied to the NAND flash controller 20 as output data. If all errors have not been corrected, error correction is performed again in the RS-E/D section 21 and each E/D section 22.

The NAND flash controller 20 completes a series of error corrections, details of which will be described later, and finally writes the data supplied from each E/D unit 22 and RS-E/D unit 21 to the read buffer 11B.

(Memory chip configuration)
Next, the configuration of a NAND flash memory chip will be briefly described. A NAND flash memory chip is composed of a plurality of memory blocks BLK, which are units for erasing data. The configuration of a memory block BLK will be described with reference to FIG.

Figure 3 is a diagram showing an example of the configuration of a NAND flash memory chip 23 according to an embodiment of the present invention. One block BLK (here, BLK0) may include string units St0 to St3. These string units St0 to St3 have the same configuration, so here, the configuration of string unit St0 will be described.

String unit St0 is connected to multiple word lines WL0 to WL7 and multiple bit lines BL0 to BL(L-1). String unit St0 includes multiple NAND strings STR. Each NAND string STR includes one selection gate transistor ST0, a plurality (for example, eight) of memory cell transistors MT0 to MT7, and one selection gate transistor DT0. The selection gate transistor ST0, memory cell transistors MT0 to MT7, and selection gate transistor DT0 are connected in series between the source line CELSRC and one bit line BL in this order.

Each memory cell transistor MT functions as a memory cell. Each memory cell transistor MT includes a control gate and a charge storage layer. Control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gate of the selection gate transistor ST0 is connected to the selection gate line SGSL0. The gate of selection gate transistor DT0 is connected to selection gate line SGDL0.

For example, in string unit St0, a set of memory cell transistors MT (e.g., MT7) connected to the same word line WL (e.g., WL7) is called a page. When the NAND flash memory chip 23 is a TLC-NAND flash NAND (TLC), the sets of memory cell transistors MT connected to the same word line WL function as three pages (Lower Page, Middle Page, and Upper Page).

Further, the plurality of word lines WL are commonly connected to string units St0 to St3. Therefore, for one word line, the set of memory cell transistors MT connected to this word line is divided into four groups (that is, a group of memory cell transistors MT belonging to string unit St0, a group of memory cell transistors MT belonging to string unit St1). a group of memory cell transistors MT belonging to string unit St2, a group of memory cell transistors MT belonging to string unit St3). One group is used as one writing unit.

The control circuit in the NAND flash memory chip, which includes a sense amplifier and a voltage generating circuit (not shown), is configured to write data supplied to the NAND flash memory chip to the memory cell transistor MT and to output data stored in the memory cell transistor MT to the outside of the NAND flash memory chip.

As described above, in the NAND flash memory chip, one memory block BLK includes a plurality of pages. Further, a plane is configured by a plurality of memory blocks BLK. Different planes within one NAND flash memory chip can be accessed in parallel. On the other hand, different blocks within one plane cannot be accessed in parallel.

Using Figures 4, 5A, and 5B, the error correction coding during data writing according to this embodiment will be described. Figure 4 is an example of a flowchart of the error correction coding. Figures 5A and 5B are diagrams for explaining how the memory controller 12 receives a flash command and the NAND flash controller 20 writes data to multiple pages of a memory block BLK in the NAND flash memory chip 23.

5A and 5B represent the page states of word lines WL0 and WL1 in a certain memory block A. In the figure, St0 to St3 represent strings of word lines, and "L", "M", and "U" represent lower pages, middle pages, and upper pages, respectively. In the case of a multilevel memory, a series of data writes are performed to a lower page, a middle page, and an upper page. On the other hand, the host 14 may request the memory system 1 to perform a flush process in order to cope with the above-mentioned momentary power outage.

For example, the memory system 1 may receive a flush request from the host after writing to a lower page has finished and before writing data from the middle page to the upper page has finished. In this case, invalid data from the unwritten middle page and upper page must be written to the memory chip 23, which reduces write efficiency. Furthermore, if a large amount of invalid data is written, the response time until the flush process is completed increases, resulting in a deterioration in the performance of the entire system including the host 14. In this embodiment, when performing flush processing to deal with a momentary interruption, write control is performed as described below. Figure 5A shows the state of the page before flushing is performed, and Figure 5B shows the state after flushing is performed.

The word line WL0 includes a lower page L, a middle page M, and an upper page U. Furthermore, the lower page of the word line WL0 includes four pages _P00L to _P03L corresponding to the four strings St0 to St3, respectively. Similarly, the middle page includes pages _P00M to _P03M corresponding to the strings St0 to St3, respectively, and the upper page includes pages _P00U to _P03U corresponding to the strings St0 to St3, respectively. Similarly, the lower page, middle page, and upper page of the word line WL1 include pages _P10L to _P13L, pages _P10M to _P13M , and pages _P10U to _P13U corresponding to the strings St0 to St3, respectively.

In Figures 5A and 5B, each box represents a page unit, and the numbers written within the box indicate the order in which the pages should be written. Boxes with diagonal lines slanting downwards to the left indicate pages that have been written and contain valid data. Blank boxes are pages that have not been written to.

The E/D unit 22 obtains a predetermined amount (for example, 512 bytes) of input data (original data) held in the write buffer 11A via the NAND flash controller 20 (S100). At this time, the RS-E/D section 21 also acquires the original data.

In the E/D unit 22, the CRC encoder 26 calculates the CRC for every 8 bits of the original data and generates a CRC code (S110). In this example, a 4-byte CRC code is generated from 512 bytes of original data. The CRC code is supplied to the BCH encoder 27.

Next, the BCH encoder 27 generates a BCH code for every 8 bits of the original data, and also generates a BCH code for every 8 bits of the CRC code generated in step S110 (S120). In this example, a 26-byte BCH code is generated from 512-byte original data and a 4-byte CRC code.

Then, the NAND flash controller 20 stores the original data, the CRC code generated from the original data, and the BCH code generated from the original data and the CRC code in one page of a plane of the NAND flash memory chip 23 (S130).

The NAND flash controller 20 determines whether a specified number of data processes have been performed (S140). If it is determined that the predetermined amount of data has not been processed yet (No in S140), the process returns to step S100, and the next predetermined amount of original data is acquired. Through the processing of steps S100 to S140, writing is performed in the order of pages P _00L , P _01L , . . . in FIG. 5A. The NAND flash controller 20 may determine that a predetermined number of data processes have been performed when the host 14 issues a flash programming instruction.

Here, pages P _02L , P _03L , P _10L , and P _11L to which only the lower page is written before flash execution (the lowest page among multiple pages with no writing on the upper side) are the second stage programs. is in an incomplete state. Therefore, pages P _02L , P _03L , P _10L , and P _11L are affected by unauthorized power interruption when writing to the corresponding middle page or upper page (for example, pages P _02M and P _03M ) on the higher level side. There is a risk that the data will be destroyed as a result of this. Therefore, the memory system of the embodiment further executes the processing from step S150 onwards.

When it is determined in step S140 that a prescribed number of data processes have been performed (or a flash command has been received), the NAND flash controller 20 detects pages for which the second stage program is incomplete (S150). In the example shown in Fig. 5B, pages higher than the lowest written pages _P02L , _P03L , _P10L , and _P11L have no written data, so these pages are detected.

The NAND flash controller 20 sets the detected pages _P02L , _P03L , _P10L , and _P11L in the RS frame (S160). In Fig. 5B, the RS frame is shown surrounded by a thick black frame.

The RS-E/D unit 21 generates an RS code for the data of the set RS frame (S170). The RS-E/D unit 21 traverses the data block from the acquired data, extracts data in units of 8 bits (1 symbol) that correspond to positions within the data block, and generates an RS code.

The NAND flash controller 20 writes the generated RS code to the next writable page (page _P12L in FIG. 5A) of the NAND flash memory chip 23 (S180). That is, the RS code etc. is written to page _P12L as the RS parity of pages _P02L , _P03L , _P10L , and _P11L in FIG. 5B. The boxes indicated by diagonal lines slanting downwards to the right indicate pages that have been written and for which RS parity exists.

As described above, in the memory system of this embodiment, data is read from pages in which only lower pages are written in the flash (pages where collateral damage may occur due to unauthorized power shutoff), and the memory system is configured by a group of pages. RS frames are configured to be used, and RS parity is generated. The generated RS parity is added to the next writable page. According to such a configuration, an unauthorized power shutoff occurs when writing a page on the upper side of a page (for example, pages P _02M , P _03M , P _10M , P _11M ) in which data is written only in the lower page, and page P _02L is written. , P _03L , P _10L , or P _11L is destroyed, the NAND flash controller 20 can correct an error by using page P _12L in which RS parity is written when reading data. become.

Here, using Figures 6, 7A, and 7B, we will explain the error correction encoding when writing data in the comparative example. Figure 6 is an example of a flowchart of the error correction encoding in the comparative example. Figures 7A and 7B are diagrams for explaining how the memory controller 12 receives a flash command in the comparative example, and the NAND flash controller 20 writes data to multiple pages of a memory block BLK in a NAND flash memory chip 23.

7A and 7B also show the page states of word lines WL0 and WL1 in a certain memory block A. In the figure, St0 to St3 represent strings for each word line, and "L", "M", and "U" represent lower page, middle page, and upper page, respectively. page). In the comparative example as well, in the case of a multilevel memory, a series of data writing is performed to the lower page, middle page, and upper page. On the other hand, the host 14 may request the memory system 1 to perform a flush process in order to cope with the above-mentioned momentary power outage. In this comparative example, when performing flash processing in response to a momentary power outage, write control as described below is performed. FIG. 7A shows the state of the page before flushing, and FIG. 7B shows the state after flushing.

Word line WL0 includes a lower page L, a middle page M, and an upper page U. Further, the lower page of the word line WL0 includes four pages P _00L to P _03L corresponding to the four strings St0 to St3, respectively. Similarly, the middle page includes pages P _00M to P _03M corresponding to the strings St0 to St3, respectively, and the upper page includes pages P _00U to P _03U corresponding to the strings St0 to St3, respectively. Similarly, the lower page, middle page, and upper page of word line WL1 include pages P _10L to P _13L, pages P _10M to P _13M , and page P _10U corresponding to strings St0 to St3, respectively. ~P _13U is included.

In FIGS. 7A and 7B, one frame represents a page unit, and the numbers written within the frame indicate the order of pages to be written. A frame indicated by a diagonal line downward to the left indicates a page that has been written and contains valid data. Blank frames are unwritten pages. The dot-patterned frames, that is, pages P _12L , P _13L , P _03M , and P _03U are pages that have been written and have no valid data.

The E/D unit 22 acquires a predetermined amount (for example, 512 bytes) of input data (original data) held in the write buffer 11A via the NAND flash controller 20 (S100). At this time, the RS-E/D section 21 also acquires the original data.

In the E/D unit 22, the CRC encoder 26 calculates a CRC for each 8 bits of the original data, and generates a CRC code (S110). In this example, a 4-byte CRC code is generated from 512-byte original data. The CRC code is supplied to the BCH encoder 27.

Next, the BCH encoder 27 generates a BCH code for every 8 bits of the original data, and also generates a BCH code for every 8 bits of the CRC code generated in step S110 (S120). In this example, a 26-byte BCH code is generated from 512-byte original data and a 4-byte CRC code.

Then, the NAND flash controller 20 stores the original data, the CRC code generated from the original data, and the BCH code generated from the original data and the CRC code in one page of the plane of the NAND flash memory chip 23 (S130). .

The NAND flash controller 20 determines whether a specified number of data processes have been performed (S140). If it is determined that the predetermined amount of data has not been processed yet (No in S140), the process returns to step S100, and the next predetermined amount of original data is acquired.

Here, the pages _P02L , _P03L , _P10L , and _P11L , in which only the lower page is written before the flush is _executed (the lowest page among the multiple pages with no writing on the upper side), are in a state where the second stage program is incomplete. Therefore, if an illegal power interruption or the like occurs when writing to the corresponding middle page or upper page on the upper side, there is a risk that the data of the pages _P02L , _P03L , _P10L , and P11L will be involved and destroyed. Therefore, in the memory system of the comparative example, the process from step S145 onwards is further executed.

If it is determined in step S140 that a prescribed number of data processes have been performed (or a flash command has been received), the NAND flash controller 20 writes some of the valid data from pages _P02L , _P03L , _P10L , and _P11L , for which the second stage program is incomplete, to the middle and upper pages, which are on the higher side, and also writes invalid data (dummy data) to the middle and upper pages as necessary, thereby eliminating the state in which valid data exists in lower pages where the upper pages are not written (S145).

Specifically, the NAND flash controller 20 detects pages for which the second stage program is incomplete. In the example shown in FIG. 7A, since there is no data that has been written to pages higher than the lowest pages _P02L , _P03L , _P10L , and P11L, these pages are detected. Next, among the detected pages _P02L , _P03L , _P10L , and _P11L , data of pages _P10L and _P11L is written to pages _P02M and _P02U , and data of the original pages _P10L and _P11L is invalidated (FIG. 7B). As a result, data of pages _P10L and _P11L is moved to pages _P02M and _P02U . Furthermore, dummy data is written _to pages _P03M and _P03U , which are higher than page _P03L . At this time, dummy data is also written to the lower pages _P12L and _P13L according to the write order. _P03M , _P03U , _P12L , and _P13L indicated by dotted frames indicate pages that have been written but do not contain valid data (invalid data).

Through this process, all the valid data in the page to which only the lower page has been written is moved, and all the valid data exists in the page to which writing has been completed up to the upper page. As a result, even if power is cut off during writing to a middle page or an upper page, valid data will not exist in the lower pages that are destroyed thereby.

In the memory system of this embodiment, whose operation is shown in Figures 5A and 5B, an RS frame is made up of a group of pages (which cannot be programmed simultaneously) belonging to different strings in one block, and the RS parity is added to the page following the group of pages. This configuration creates a state in which multiple lower pages in the RS frame are not simultaneously destroyed, making it possible to restore data that was written and programmed before the flash command by adding a minimum number of pages, even if the data is destroyed by an unauthorized power interruption.

On the other hand, in the memory system of the comparative example of the operation shown in Figures 7A and 7B, every time a flash command is executed, a page movement (write + invalidation) occurs that may cause collateral damage, and there is also a possibility that a dummy page may be written.

Comparing this embodiment with the comparative example, in the embodiment of the operation shown in Fig. 5B, after the flash command is executed, it is necessary to read pages _P02L , _P03L , _P10L , and _P11L , write page _P12L to which the RS code is written, and perform the first stage program. On the other hand, in the comparative example of the operation shown in Fig. 7B, it is necessary to read pages _P10L and _P11L , write pages _P02M and _P02U , write pages _P03M and _P03U , and perform the first stage program and the second stage program. Therefore, the memory system of this embodiment can realize recovery from collateral data destruction with a shorter response time by minimizing page reads, writes, and programs.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

1... memory system, 10... host interface, 11... buffer memory, 12... memory controller, 13... flash memory section, 20... NAND flash controller, 21... RS-E/D section, 22... E/D section, 23... NAND flash memory chip.

Claims (6)

a non-volatile storage unit configured by arranging a plurality of memory cells each having a plurality of pages and capable of storing multi-level data;
a correction processing unit capable of error correcting data stored in the storage unit in units of pages;
A controller that writes the multi-value data to the storage unit and reads the multi-value data written from the storage unit,
The controller includes:
managing a storage location of the multivalued data stored in the storage unit;
detecting a page in which data is stored only in the lowest page among the plurality of pages;
causing the correction processing unit to generate an error correction code that includes all of the detected pages as one frame;
A memory system in which the error correction code is written to a writable page following the page constituting the one frame among the lowest pages. The memory system of claim 1, wherein the controller restores a page constituting one of the frames using the error correction code when the page constituting one of the frames is destroyed. The memory system according to claim 1, wherein the correction processing unit generates a redundant code of a Reed-Solomon code. a non-volatile storage unit including a plurality of memory cells arranged in a plurality of rows and each of which has a plurality of pages and is capable of storing multi-value data;
a correction processing unit capable of correcting errors in the data stored in the storage unit on a page-by-page basis;
A control method for a memory system having a controller that writes the multi-value data to the storage unit and reads the written multi-value data from the storage unit, comprising:
managing a storage location of the multi-valued data stored in the storage unit;
detecting a page having data stored only in a lowest page among the plurality of pages;
generating an error correction code in which all of the detected pages are one frame in the correction processing unit;
A control method for writing the error correction code into a page that can be written into subsequent to a page that constitutes one of the frames among the lowest pages. The control method according to claim 4, wherein the controller restores a page constituting one of the frames using the error correction code when the page constituting one of the frames is destroyed. The control method according to claim 4, wherein the correction processing unit generates a redundant code of a Reed-Solomon code.

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