JP2018502485A - Method and apparatus for controlling, monitoring, and communicating with tunable optical devices and subassemblies - Google Patents

Abstract

An apparatus for controlling, monitoring, and communicating with an optical device, photonic integrated circuit, or subassembly is provided. The apparatus includes a field programmable device including an optical device or subassembly and a programmable hardware gate coupled to the optical device or subassembly. A field programmable device can be configured to implement multiple functions at the gate level to control, monitor, and / or communicate with an optical device or subassembly, each of the multiple functions being micro- It is configured to execute as parallel processing without the use of a processor or microcontroller. Furthermore, a programmable optical device such as a programmable optical transmitter, optical subassembly, or transceiver based on a tunable laser having a control system centered on a field programmable device, characterized by software operation Presents a wide range of real-time control and monitoring functionality, for example, based on actual traffic. [Selection] Figure 1A

Description

This patent application is entitled “Methods and Apparatus for Controlling Tunable Optical Devices and Subsembles” and is filed on November 20, 2014. No. 082,545, the entire disclosure of which is hereby incorporated by reference in its entirety.

  Today's fiber optic-based networks serve as an interface between electronic equipment and optical signals propagating over the fiber, and at other points in the network that convert information between electronic and optical forms. Use a transceiver.

  Optical devices, including optical, photonic, and optoelectronic devices and components, are used to transmit, encode, receive, and decode optical data for transmission over optical fibers. Optical devices are used to control devices and components, as well as interface with electronic forms of data on the transmitting and receiving sides, encoding and decoding electronic data, and clock recovery and error correction. Of interface optics and circuits used to implement other functions such as temperature, wavelength and other tunable laser functions, and fully functional tunable lasers and tunable subassemblies Interfaces to various electronic circuits used to implement the functions required to control the environment of the circuit, including the functions.

  Programmable optical devices, such as transmitters, optical subassemblies, and transceivers, based on tunable lasers, support many tunable laser functions and many to support control, monitoring, and communication functionality Requires a control system. Widely tunable lasers include multiple sections, typically including a gain section, a tunable phase section, and a tunable mirror section, and some designs also include a tunable filter section. Tuning the physical parameters of these sections results in tuning of the output laser wavelength. Other parameters of tunable lasers, whether integrated or non-integrated, include optical data modulators and power control, wavelength locking, line narrowing and control, modulation control, higher order modulation, or similar Other features, such as those, can be used to enhance these capabilities using the present disclosure.

  Examples of prior art references include "Control of Widely Tunable SSG-DBR Lasers for Dense Wavelength Division Multiplexing", Journal of Lightwave Technology, Vol. 4, No. 8, 2000, Vol. 8, No. 4, 2000, No. 8, 2000. 6,788,719, 6,690,693, and US Patent Application No. 2004/0120372, the entire disclosures of which are hereby incorporated by reference in their entirety.

  However, known conventional programmable wavelength tunable transmitters such as transmitter optical subsystem assembly (TOSA), transceivers, and other communication optical subassemblies are not programmable in real time. Therefore, the flexibility and responsiveness in the optical layer is lacking. In addition, like existing devices that lack real-time programmability, there is a high cost associated with planning, building, operating and maintaining a data center network.

  It should be understood that the foregoing general description and the following detailed description are exemplary and are intended to further describe the technology or the disclosure as described.

  The present disclosure relates generally to optical devices and subassemblies such as integrated electronics and photonic integrated circuits, and optical transceivers, modules and subassemblies, and laser transmitters and receivers using combinations thereof. Optical devices and subassemblies are extensively integrated on the same substrate as many components, such as optical modulators and semiconductor optical amplifiers, non-integrated optical and optoelectronic components, and other metrology and control devices and components. Built-in tunable semiconductor laser.

  In one aspect, an apparatus for controlling, monitoring, and communicating with an optical device, photonic integrated circuit, or subassembly for optical communication is provided. The apparatus includes a field programmable device including an optical device or subassembly and a programmable hardware gate coupled to the optical device or subassembly. The field programmable device is configured to implement multiple functions at the gate level to control, monitor, and / or communicate to the optical device or subassembly, each of the multiple functions being a microprocessor or a micro It is configured to execute as parallel processing without using a controller.

  In one aspect of the present disclosure, an optical communication system includes an optical modulator and a semiconductor optical amplifier, an optical device or subassembly comprising a tunable laser integrated on the same substrate as non-integrated optical and optoelectronic components, and A field programmable device including an optical device or subassembly and a programmable hardware gate coupled to a laser transmitter and receiver. The field programmable device is configured to implement multiple functions at the gate level to control, monitor, and / or communicate to the optical device or subassembly, each of the multiple functions being a microprocessor or a micro It is configured to run as parallel processing without using a controller. A field programmable device of an optical communication system includes one or more field programmable gate arrays (FPGAs) or programmable logic devices (PLDs). Further, the field programmable device of the optical communication system may be configured to include an application programming interface (API) for real-time control and monitoring of the optical device and subassembly based on actual traffic. Can do. Also, the plurality of functions can be configured to run with different clock signals within the field programmable device. In addition, field programmable devices are graphical users that allow control, monitoring, and / or communication of tunable lasers integrated on the same substrate as optical modulators and semiconductor optical amplifiers, non-integrated optical and optoelectronic components. A communication interface may be provided that includes one or both of a socket to an interface (GUI) or an application programming interface (API).

  In another aspect, the present disclosure comprises optical devices and subassemblies that are programmable in real time, such as wavelength tunable transmitters (eg, TOSA), transceivers, and other communication optical subassemblies. In accordance with the present disclosure, features operable by software accessible via an application programming interface (API) present a wide range of real-time control and monitoring of optical devices and subassemblies, for example, based on actual traffic To do. Programmability means unprecedented levels of flexibility and responsiveness in the optical layer by scaling bandwidth in real-time and transmitting separately, higher bandwidth from a given fiber optic installation Enables extraction and reduction of complexity and associated costs associated with planning, building, operating and maintaining a data center network.

  In one aspect of the present disclosure, a programmable system, method and device includes a tunable laser, a tunable transmitter, a detachable sub-assembly of a tunable transceiver, and a tunable attached to a substrate. Provided to control, monitor, and communicate to a complete transceiver and spare integrated or non-integrated optics, optoelectronics, and / or electronics. The systems, methods and devices described herein are designed to function fully tunable lasers, tunable transmitters, tunable transceivers, detachables, subassemblies, or substrates that attach to a substrate, Realize functions to build, produce and manufacture. The present disclosure is directed to a tunable laser, transceiver, module, or optical sub-field in a field programmable device that includes a field programmable gate array (FPGA) or programmable logic device (PLD) circuit architecture, or a combination of microprocessors or microcontrollers. Implement monitoring, control, and communication functions for the assembly.

  Both FPGA and PLD circuits are reconfigurable circuits that can be programmed / reprogrammed after manufacture, in the field, and / or in real time. According to the present disclosure, the control functions of the optical device or subassembly can be implemented without a microcontroller or microprocessor. For example, various functions including control functions can be embedded in the FPGA or PLD. By way of example, functions embedded within an FPGA or PLD include soft state machines, electronic filters, control and feedback loops implemented by embedding parallel processing within the combination of FPGA, PLD or programmable logic and microprocessor, Including but not limited to decision circuits, communication interfaces, etc. The present disclosure has advantages over existing technologies that utilize microprocessors or microcontrollers for control and programmable logic devices, such as FPGAs or PLDs, to store calibration and other data for search operations. There is a point.

  Other advantages of the present disclosure are described in further detail below. By way of example, control, monitoring, and communication functions for assembling and operating tunable transmitters, tunable lasers, tunable transceivers, detachables, or subassemblies are within hardware gates within the FPGA. Using firmware, each runs at its own clock speed and is implemented in modules. Parallelism, modularity, and the ability to run processing at different clock speeds can provide advantages over existing technologies for reduced cost, complexity, power consumption, and other benefits.

The present disclosure provides control, monitoring for a tunable laser / transmitter / receiver that can be programmed, firmware updated, and fully FPGA controlled (no microprocessor or microcontroller required), Including but not limited to communication methods and apparatus. Embodiments of the present disclosure include, but are not limited to, the following.
-A round-trip communication interface with the client or host or fiber communication channel,
・ Storage and management of wavelength of tunable laser,
Programmable read only memory (PROM) for external erasable programmable read-only memory (EPROM) —Serial peripheral interface (SPI) flash
Set currents and all control and monitoring functions for tunable lasers, modulators, optoelectronics, electronics, sensors, and other control and monitoring contacts interfaced via voltage and current Voltage,
Monitoring of optical, electronic and photonic integrated circuits (PICs);
-Boxcar averaging device and other signal processing functions,
・ Automatic optical power control,
・ Wavelength locking,
Line width narrowing algorithm and circuit (for example, Pound Dever Hall (PDH)),
Temperature monitoring and control,
Alarm and monitoring control and communication,
• Application programming interface (API), and • Fully calibrated stand-alone, ready to be integrated into a detachable or on-board-digital control / monitoring / data-on-board calibrated EPROM.

  According to one aspect of the present disclosure, a control system and method are provided for rapidly controlling an optical device and / or subassembly. Control systems and methods include tunable lasers, internal and external optical and optoelectronic monitoring and control functions, internal and external electronic monitoring and control functions, signal processing functions, and transceivers, optical modules and / or Functionality to control parts of the optical device or subassembly, such as related functions within the optical subassembly.

  Another aspect of the present disclosure is a combination of a stand-alone or microcontroller and / or a combination of analog to digital converting (ADC) and digital to analog converting (DAC) circuits. Implementing an embodiment of a control system and method according to the present disclosure in a field programmable device, such as an FPGA, PLD, or the like, where the FPGA, PLD, or the like is data storage Beyond the simple use of today's FPGAs and PLDs, such as lookup tables for tunable lasers alone, it is used for control functions as part of the first embodiment. Thus, this embodiment of the present disclosure is for tunable lasers and others accessed by other processing modules for monitoring, control and processing, but not for control systems and methods as described herein. The present invention provides various advantages over existing technologies that utilize FPGAs and / or PLDs with limited capacity to store data regarding the present embodiment.

  In one aspect of the present disclosure, the field programmable device is at least one of moving based on the measured temperature and between tables stored in the field programmable device, or extrapolating between temperature wavelength maps. Thus, the laser control current of the tunable laser can be automatically adapted to the measured temperature in order to reduce the load on the thermoelectric cooler (TEC).

  An advantage of using a field programmable device such as an FPGA, PLD, or the like as part of a control system and method according to the present disclosure is that code and processing can be modular and / or parallel processing. Each can run at different unique clock speeds within the same device, can be reprogrammed, and can handle all control, monitoring, and communication embodiments. Thus, in one aspect of the present disclosure, sub-modules of one or more systems may be replaced, modified, programmed and / or reprogrammed without affecting other modules / sub-modules. it can. Thus, the benefits of running optical device and subassembly control, monitoring and communication systems in a gate level programmable manner are reduced power consumption, reduced costs, wider use across a broader class of applications, and It can involve introducing various types of new control modules (filters, analog circuits, state machines, etc.) within a common programmable architecture.

  According to another aspect of the present disclosure, the methods and systems described herein are disclosed in the United States, published July 10, 2014, as WO 2014/10537, which is incorporated herein by reference in its entirety. It can be used with multiple faceted laser architectures as described in patent application No. 14/146717. As described in WO 2014/107537, two or more facets of a tunable laser can be used for output and can be connected to a novel modulator structure. The control and monitoring described in this disclosure may have, in some forms, additional advantages over the prior art when combined with the invention described in WO2014 / 105373.

  According to one aspect, the present disclosure can be used with optical devices and subassemblies that use an FPGA-centric architecture. Examples of devices and subassemblies include U.S. Patent No. 8,644,713, and U.S. Patent Application No. 14 / 171,480 entitled "Programmable Optical Subsembles and Modules", "Optical Network Interface Module A Hardware Amminga Amminga Amminga Amm. 12 / 945,470 entitled “Optical Network” and 13 / 942,519 entitled “Control Systems for Optical Devices and Subsembles”, which are incorporated herein by reference in their entirety. Incorporated herein by reference. An FPGA-centric architecture uses an internal FPGA to run all control, monitoring, communication, and algorithms without using a microprocessor or microcontroller in these optical devices and subassemblies. Can do.

  According to the present disclosure, the laser can be configured using the same firmware for an external FPGA to significantly increase the calibration speed, where the resulting calibration data then controls the tunable laser. The same control and control as the FPGA technology and firmware across all embodiments using wavelength tunable lasers, from manufacturing to network introduction, calibrated during manufacturing Recalibrate or reprogram. Thus, the technology can significantly reduce the cost of manufacturing and ownership and performance improvements.

  According to another aspect of the present disclosure, the communication interface is as described in US patent application Ser. No. 12 / 945,470, and related patents and patent applications, which are incorporated herein by reference in their entirety. It can also be integrated in a field programmable device (eg, FPGA). The communications interface includes a software layer that interacts with the tunable laser through a field programmable device (eg, FPGA or PLD, or the like) to implement one of any of the fast wavelength calibration algorithms. Can be equipped with a socket for a graphical user interface (GUI) and / or an application programming interface (API) that allows software to control, monitor and calibrate a complete tunable laser for ease of use, manufacturing Performance, speed of calibration, and integration into other manufacturing, system integration, and network operations systems, significantly reducing costs and flexibility compared to any existing method . Depending on the speed of the calibration routine, recalibration can be done in the field or in real-time using an application layer interface via field programmable devices (eg, FPGA, PLD, or the like) in a matter of minutes I can even do that.

  In another aspect of the present disclosure, the field programmable device is configured via a wireless communication from a GUI coupled to the field programmable device or other device installed at a remote site on an optical communication link. Can be configured to receive one or more control signals from.

  Another significant advantage of the present disclosure is that all the functions required to improve the performance of tunable lasers and transmitters using firmware, such as coherent communication as two of many examples, In addition to controlling and monitoring the interface, field programmable devices (e.g., narrowing the laser linewidth to reduce laser linewidth noise and reducing relative intensity noise (RIN)) , FPGA, PLD, or the like) can also be included. These processes can be run in parallel with all other processes for tunable lasers, transmitters, transceivers, modules, or subassemblies and are often used for other functions Hardware can be reused.

  A more detailed understanding can be obtained from the following description in conjunction with the accompanying drawings.

FIG. 3 is a block diagram conceptually illustrating components for a control system centered on a field programmable device, according to one aspect of the present disclosure. FIG. 6 illustrates an example field programmable device according to one aspect of the present disclosure. It is the figure which showed the example of the method by which a function is mounted in a field programmable device as a parallel and independent process. FIG. 2 illustrates an exemplary implementation of tunable laser or transceiver control, monitoring, and communications using a microprocessor or microcontroller based architecture. FIG. 7 illustrates an example implementation of a register write operation according to one aspect of the present disclosure. FIG. 3 shows an example block diagram of a tunable modulator of a photonic integrated circuit (PIC). FIG. 6 illustrates an example block diagram of an external control function or loop using field programmable device technology, according to one aspect of the present disclosure. FIG. 6 illustrates an example gain voltage map obtained by tuning the laser mirror current of a tunable laser at three different temperatures, according to one aspect of the present disclosure. FIG. 3 is an example of an approximation of tuning for two laser mirror currents at wavelengths 1542.02 nm and 1577.16 nm versus temperature. FIG. 6 illustrates an example of a graphical user interface (GUI) configured to communicate through a process that runs within a field programmable device. FIG. 6 illustrates an example of a graphical user interface (GUI) configured to communicate through a process that runs within a field programmable device. FIG. 6 illustrates an example of a graphical user interface (GUI) configured to communicate through a process that runs within a field programmable device. FIG. 6 illustrates an example of a graphical user interface (GUI) configured to communicate through a process that runs within a field programmable device. FIG. 2 illustrates an exemplary implementation of an analog PDH control system. FIG. 6 illustrates an example implementation of a PDH feedback loop according to one aspect of the present disclosure. FIG. 3 illustrates an example implementation of a PDH algorithm according to one aspect of the present disclosure. FIG. 3 illustrates an example implementation of a PDH algorithm according to one aspect of the present disclosure. FIG. 6 illustrates an example equation for power detected from an optical signal reflected by an etalon, according to one aspect of the present disclosure. FIG. 3 illustrates an example implementation of a PDH algorithm according to one aspect of the present disclosure. FIG. 6 illustrates an example block diagram of firmware control of field programmable devices and other devices, according to one aspect of the present disclosure. FIG. 5 illustrates an example of a reflected and transmitted response of a general etalon, according to one aspect of the present disclosure. FIG. 3 is a diagram illustrating an example block diagram illustrating an example implementation of a wavelength locking algorithm, according to one aspect of the present disclosure. FIG. 4 illustrates an example diagram of one embodiment of a temperature control process according to one aspect of the present disclosure. FIG. 6 illustrates a block diagram of a symbol model of one channel of a boxcar filter, according to one aspect of the present disclosure. FIG. 23A is a diagram illustrating an example address space of a flash memory according to one aspect of the present disclosure. FIG. 23B is a diagram illustrating an example of a wavelength definition table according to one aspect of the present disclosure. FIG. 7 illustrates an example implementation of one or more processing systems according to one aspect of the present disclosure.

  In accordance with the present disclosure, optical devices such as programmable optical transmitters, optical subassemblies, and transceivers are described. As an example, a programmable optical device has a control system centered on a field programmable device that supports various functions of a tunable laser (eg, centered on an FPGA or centered on a PLD) and controlled. Based on a tunable laser that supports monitoring, and communication functionality. The present disclosure comprises a real-time programmable wavelength tunable transmitter, such as a transmit optical subassembly (TOSA), a transceiver, and other communication optical subassemblies.

  FIG. 1A shows a block diagram conceptually illustrating components for a control system centered on a field programmable device (eg, centered on FPGA / PLD). The system 100 shown in FIG. 1 includes a host controller 101, a field programmable device 103 (eg, FPGA, PLD, or the like), laser control electronics 105, a tunable laser 109, and a storage 111. The host controller 101 can be configured to communicate with the field programmable device 103 for various functions and can be configured to receive data related to the operation of the tunable laser 109. In this example, the field programmable device 103 can drive the laser control electrode 105 through the field programmable device 103 and a digital / analog converter (DAC) 107 interfaced to the tunable laser 109. Further, the field programmable device 103 can be coupled to the wavelength tunable laser 109 through an analog / digital converter (ADC) 117 for communication and control to the wavelength tunable laser 109.

  In addition, the field programmable device 103 has a round-trip communication interface with the client or host for fiber communication channels, wavelength storage and management of tunable lasers, PROM-SPI flash interface to external memory, voltage and current. Current and voltage settings for all control and monitoring functions, optic and electronic and photonic integrated circuits (PICs) for tunable lasers, modulators, optoelectronics, sensors, and other control and monitoring contacts that interface ) Monitoring, boxcar averaging device and signal processing function, automatic optical power control, wavelength locking, line narrowing function, temperature monitoring and control, alarm and monitoring control And various components, modules, or processes (such as those shown in the figure), such as communication and application programming interface (API), and many other functions for implementing various aspects of the methodology described herein. 1A, but will be described in detail herein). Further, the field programmable device 103 may be an internal storage (not shown) such as storage coupled to the field programmable device 103 or memory 111 for storing various parameters including parameters for implementing various aspects of the present technology. ) And / or external storage. In one aspect of the present disclosure, the memory 111 may include one or more data lookup tables related to implementing various aspects of the technology described herein.

  Further, in one aspect of the present disclosure, an architecture centered on a field programmable device (e.g., centered on FPGA, PLD, or the like) can be implemented as follows. The host controller 101 can be a high-level programming language (eg, C code, or the like) in an embedded software processor, or a hardware description language (eg, HDL code, or the like) for further efficiency and speed. Code for one or more algorithms, modules, processes or functions, such as The host controller 101 can also be connected to the field programmable device 103 through a standard interface, i.e., a universal serial bus (USB) connection. As described above, in accordance with various aspects of the present technology, the field programmable device 103 is configured to deliver current to various components including the laser mirror of the tunable laser 109 while performing various aspects of the present technology. Can communicate directly with the DAC 117 and communicate with an ADC 107 configured to monitor the electrode voltage and / or power detector to collect data from the tunable laser 109. Alternatively and / or in addition, the field programmable device 103 can monitor the tunable laser 109 thermistor and send the current control input to the tunable laser 109 TEC controller to provide a laser temperature transient. The state can be controlled. Further, the field programmable device 103 may perform various functions, methods, algorithms, or methodologies in accordance with aspects of the present disclosure, regardless of whether the field programmable device 103 is internal or external to the field programmable device 103. Data associated with controlling, monitoring, and communicating with the tunable laser 109 in one or more storage devices such as can be buffered or stored.

  In one aspect of the present disclosure, the technology may be viewed as an architecture centered on a field programmable device (eg, FPGA, PLD, or the like) for an optical communication system. Accordingly, one or more implementations of the present technology can be optimized for the hardware architecture and methodology or the algorithm itself, and in processing various aspects of the present technology within the field programmable device 103, Data transfer to and from the concatenated ADC 107, DAC 117, and storage 111 can be very efficient.

  In another aspect, the present disclosure provides a software operable feature accessible via an application programming interface (API), eg, one or more modules or processes based on actual traffic Presents a wide range of real-time control and monitoring. Such programmability is an unprecedented level of flexibility and responsiveness in the optical layer by scaling bandwidth in real time and transmitting separately, higher from a given fiber optic installation It provides bandwidth extraction and reduced complexity and associated costs associated with planning, building, operating and maintaining a data center network. Rapid control over all aspects of a tunable laser where two or more facets are optically available, or an integrated transmit photonic that combines a tunable laser and modulator, or optical transceiver or optical subassembly An integrated circuit (PIC) assembly is provided. That is, the present disclosure can provide fast and reprogrammable control in a modular, parallel and independent process, and thus can handle all control, monitoring, and communication aspects. Within, any sub-module of the system can be exchanged, modified and programmed without affecting other modules or processes. In other words, in one aspect, the control, monitoring, and communication system can comprise modular independent and / or parallel processing configured to run within the field programmable device, each of the processing Can be configured to run on different clocks. Benefits of running all control, monitoring, and communication in a gate-level programmable manner, reducing power, reducing costs, wider use across a wider class of applications, and a common programmable architecture Various types of new control modules (filters, analog circuits, state machines, etc.) can be introduced.

  Thus, the present disclosure uses internal field programmable devices, such as FPGAs, PLDs, or the like, without the use of a microprocessor or microcontroller to implement control, monitoring, communications, and algorithms. Alternatively, the same firmware can be used for an external FPGA that can be provided and used to calibrate the tunable laser, thereby significantly speeding up the calibration of the tunable laser. The resulting calibration data can then be transferred to a wavelength-controlled FPGA that is used to control the tunable laser, all about calibration during manufacturing, as well as the use of the tunable laser from manufacturing to network introduction. The same control and recalibration or reprogramming with the field programmable device-based technology and firmware described herein, over this aspect, significantly reduces manufacturing and ownership costs, and improves performance.

  In one aspect of the present disclosure, the communication interface to the field programmable device 103 is one of any of the algorithms described herein, including gate level general programming, as well as fast wavelength calibration algorithms. A graphical user interface (GUI) that allows software control, monitoring, and calibration of a fully tunable laser using a software layer that interacts with the tunable laser through a field programmable device 103 to implement one And / or an interface to an application programming interface (API) that can provide ease of use, manufacturability, speed of calibration, and other manufacturing, system integration, and Allowing integration into network operation system, significantly lowering the cost and flexibility as compared with any conventional existing techniques. Calibration routine speed is in minutes, allowing field or real-time recalibration using field layer devices (eg, FPGA, PLD, or similar) using application layer interface You can even

  The advantages of the present disclosure may include, but are not limited to, many significant advantages over existing technologies that use a microcontroller or microprocessor as the primary control and primarily use the FPGA as a data storage and search device. . In the past, performance as a function of footprint and power consumption of field programmable devices such as FPGAs has been addressed by microprocessors to handle various functions required for real-time data and to control tunable laser applications. Was not considered competitive. In recent years, however, field programmable device technology, including FPGA, PLD, or similar technology, has made significant progress, controlling, monitoring, and more than many microcontroller or microprocessor based solutions. It has become a preferred and more flexible method and apparatus for communicating.

  As an example, as shown in FIG. 1B, a field programmable device such as an FPGA is an integrated circuit that can be programmed in the field after manufacture or in real time, unlike some integrated circuits such as a hard-core microcontroller or microprocessor. is there. That is, an FPGA is a semiconductor device based on programmable / configurable logic blocks connected via programmable interconnects or wiring circuits, thereby requiring a desired application or functionality after manufacture. For matters, the FPGA can be reprogrammable. In other words, an FPGA is a device based on gate and device interconnections that is loaded into the FPGA to operate on data and signals at the input to generate the output. In one implementation, the field programmable device 103 comprises a plurality of configurable logic blocks (CLBs) 133, a plurality of input / output (I / O) ports 135, a programmable interconnect 137, and others. , FPGA, PLD, or the like. Each configurable logic block 133 (CLB) can include various components such as carry logic, input lookup tables, flip-flops, and the like. The operation of the FPGA and the clock speeds of the different processes running on the FPGA can be changed in real time, so a wide variety of control, monitoring, feedback, communication, and other functions are available at the hardware level performance within the FPGA. Can be realized. Thus, by way of example, according to one aspect of the present disclosure, an architecture based on a field programmable device (e.g., FPGA, PLD, or the like) is incorporated into a tunable laser or a tunable laser based module. In contrast, parallel control, monitoring, and communication processing can be enabled.

  Further, as shown in FIG. 1C, different areas of FPGA circuitry can be assigned or used to implement all the different data and / or control functions within individual devices. By way of example, in FIG. 1C, multiple data and / or control functions or modules may be located in one or more PLBs, eg, wavelength locking 151, wavelength mapping and search 153, TEC control 155, automatic power control (APC: (automatic power control) 157, PHD line width control 159, communication I / O 161, etc. can be implemented, each with a different clock signal, eg, clock 1, 2,. . . Run at 6. In addition, new modules or processes such as PDH line width (LW) control 159 with a clock signal (eg, clock 5) can be added in real time.

In one aspect of the present disclosure, some functions that can be achieved by various aspects of the present technology can include, but are not limited to:
Control of the optical properties of the data-modulated tunable laser, including the chirp of the transmitted optical signal and adjusting the control based on the output wavelength of the tunable laser and other parameters;
Temperature monitoring and control for temperature sensitive components (eg lasers, etalons, etc.),
Control and / or adjustment on laser output power (eg by adjusting gain section and voltage controlled attenuator),
Control of the wavelength of a tunable laser by controlling mirrors, resonators, phase sections, and other wavelength tunable components by embedding a current-wavelength control map that can also be a function of temperature,
• Control and monitoring of wavelength locker circuits and functions. The internal mapping can also be changed in real time in response to tunable laser calibration and recalibration using a wavelength locker,
The ability to require a larger FPGA memory capacity, similar to the state size, as compared to a microcontroller or microprocessor;
Can operate independently of each other, at a given clock speed, leading to higher performance compared to serial finite state microprocessors, higher fault tolerance, by turning processing on and off individually The ability to manage power, as well as parallel processing with separate update processes that do not require rewriting and recompiling the complete code,
Continuous operation in the event of a host failure (eg, a control interface that allows the unit to continue to operate if the host fails),
Corrective action (eg if the laser output power is reduced or the laser wavelength is shifted, the FPGA can take corrective action according to the rocker and other mechanisms), and Other functions that can be programmed. Thus, a single chip or a smaller subset of electronic chips can be used across a wide variety of applications and PICs, switches, or transmitter and receiver subassemblies, increasing production, reducing costs, and Ultimately, power consumption and size are reduced.

As noted above, some examples of programmable firmware features that can be implemented in the field programmable device 103, such as an FPGA, PLD, or the like, can include, but are not limited to: It is not limited (the following functions or examples can be implemented alone or in combination with others).
・ Host communication interface and memory map,
Wavelength storage and management,
Programmable read-only memory (PROM) to external erasable programmable read-only memory (EPROM) —Serial peripheral device interface (SPI) flash interface;
・ Set current and voltage,
Monitoring of optical and electronic and photonic integrated circuits (PIC),
・ Box car averaging device,
・ Automatic output control,
・ Wavelength locking,
-An algorithm for narrowing the line width (such as pounded hole (PDH)),
Temperature monitoring and control,
• Alarm and monitoring control and communication, and • Application programming interface.

  As described above, FIG. 1C shows a typical implementation of tunable laser or transceiver control, monitoring, and communication using a microprocessor or microcontroller based architecture, as shown in FIG. FIG. 6 illustrates examples of some of the functions that can be implemented as parallel modular processing while providing advantages over existing technologies using microcontrollers and / or serial state machines. As shown, the microprocessor or microcontroller intentionally performs functions, modules, or processes in a sequential manner, eg, wavelength mapping and searching 153, wavelength locking 151, APC 157, TEC control 155, and communication I. / O161 is executed. Furthermore, if new features such as PDH LW control 159 are added (in 103), the code will need to be redesigned for the microprocessor or microcontroller.

  However, as described above, according to one aspect of the present disclosure, the technology is implemented as a parallel and independent module or process configured to run with different clock signals without the use of a microprocessor or microcontroller. Provides a field programmable device 103 (eg, FPGA, PLD, or the like) that can implement various functions, modules, or processes related to control, monitoring, and communication of a tunable laser or transceiver .

Host Communication Interface and Memory Map In one aspect of the present disclosure, the field programmable device 103 is an inter-IC bus (I2C) and / or serial peripheral interface (SPI), or other proprietary protocol, such as A slave controller that can implement a standard serial protocol can be included. An advantage of the present technology over any microprocessor / microcontroller or system-on-chip (SoC) based system is that the slave controller of the present disclosure is not hard-core and therefore field programmable. It can be easily modified to meet the requirements of the host interface in the device 103.

  By way of example, in one aspect of the present disclosure, a register map architecture is implemented with two dual-port random access memories (RAMs) that can be implemented in (or externally coupled to) the field programmable device 103. One for the register map and one for the wavelength table data. In addition, host reads and writes to the register map can be addressed directly to one port of the register table RAM, while the upload / download of wavelength table data includes parameters for entry of individual wavelength tables. This is accomplished through a series of registers that redirect this data to the appropriate location in the wavelength table RAM. The second RAM port updates digital / analog (DAC) data from RAM, reads analog / digital (ADC) monitoring data to RAM, and when the wavelength changes or when the system is commanded Can be used to update the laser / modulator control parameters from the wavelength table RAM. Dedicated control logic can perform RAM to ADC / DAC transactions without the use of a microcontroller or microprocessor. The logic circuit implemented in the field programmable device 103 can be further optimized for transfer efficiency, tailored to favor transactions that have predictable latency and require very low latency. be able to.

  In another aspect of the present disclosure, the registered memory map of the field programmable device 103 can be implemented in the field programmable device 103 and can be controlled via a host communication interface. The registered memory map can determine the current state of the control system, which specifies the wavelength and output power of the tunable laser assembly. The state of the control system is the result of electrode current, bias voltage, device operating temperature, and various configurable settings associated with the tunable laser, such as, for example, the TEC PID control loop and wavelength locker. there is a possibility. All of these individually configurable modules or processes can be changed by writing to the appropriate registers in the registered memory map of the field programmable device 103 without using a microprocessor or microcontroller. Or by reading from the appropriate register.

  As an example, FIG. 3 shows an example of implementation of a register write operation via UART. In this embodiment, UART can be used to communicate to the I2C device. As shown in FIG. 3, the field programmable device 103 receives a command from the host or the host controller 101 via a UART character string (for example, UART Tx from the host to the field programmable device). Echoed back to the controller (eg, UART Rx from the field programmable device to the host), then the command is translated, and the I2C command is entered into the register interface on the I2C bus coupled to the field programmable device 103. Thereafter, the UART sends back a character string together with the written data. In this embodiment, it can take approximately 1.2 ms for a single register write cycle.

Automatic output control (APC)
In one aspect of the present disclosure, automatic output control (APC) functions or loops can be implemented in the field programmable device 103 as parallel independent modules or processes. The APC control function or loop dynamically maintains the laser output power at the commanded level while also maintaining the current ratio of the semiconductor optical amplifier (SOA) in the tunable laser (eg, U-laser). However, the tunable laser maintains the balance of photocurrent in the Mach Zehnder type modulator section required for proper modulation. FIG. 4 shows the tuning of a PIC, as described in US patent application Ser. No. 61 / 748,415, published Jul. 10, 2014, as WO 2014/107537, with components that enable APC and APC loops. FIG. 2 shows a block diagram of an example of a possible modulator. In addition, an example of a block diagram of an external control function or loop using field programmable device technology such as FPGA, PLD, or similar technology is also shown in FIG.

  In one aspect of the present disclosure, a field programmable device 531 (similar to the field programmable device 103 shown in FIG. 1A) may include an averaging filter 533, a SOA balance 535, a loop filter 537, and a DAC control 539. . In an example, the averaging filter 533, the SOA balance 535, the loop filter 537, and the DAC control 539 may all be digitally implemented in the field programmable device 531 as one or more parallel independent modules or processes. it can. Field programmable device 531 (eg, FPGA or PLD, or similar technology) is configured to allow these functions to be performed optimally and with low constant latency and high noise immunity. . Further, in the example, the current DAC 551 and the current ADC 559 can be installed on the field programmable device 531 in an externally coupled manner, and the field programmable device 531 can be connected to the laser through an external current DAC (eg, the current DAC 551). The SOA current is sent to a tunable laser (eg, U-laser 553). The optical power detected from the two sections of the Mach-Zehnder type modulator 555 via the detector 557 can be digitized by the external ADC 559 and input to the field programmable device 531. The response of the detected optical power is leveled through the averaging filter 533, and the noise picked up by the analog path is filtered.

  The filtered detected power is input to SOA balance 535, which starts with a default SOA current provided from a wavelength table (not shown), then measures the detected power and outputs the balanced MZM output To maintain a proper ratio of SOA currents. This ratio is sent to the loop filter 537 together with the Tx power that is the power from section 1 of the Mach-Zehnder modulator 555 and the total power that is the sum of the power of the two sections of the modulator. The linear loop filter 537 can be configured to adjust the SOA1 and SOA2 currents in certain steps while maintaining the ratio of SOA1 and SOA2 currents until the desired Tx power is reached. The magnitude of the larger first step of SOA1 or SOA2 can be incremented to 1000 μA. When the output power is in the range of one increment of 1000 μA, the step size can be reduced to 125 μA, and the final “vernal” search should be done until the output power is in the range of one step 125 μA. Can do. If the measured power changes by more than 2 counts, ie 250 μA, the vernier search is continued again. However, if the tunable laser is reinitialized (eg, turned off and then on), the main scale search can be resumed following the vernier search.

  It should also be noted that logically, the SOA current can affect the tuning and stability of the laser wavelength through the electrical and thermal effects of the SOA current. As the SOA current changes, the SOA control circuitry can affect the circuitry that controls the laser gain, laser phase, and mirror sections, and thus can affect wavelength tuning and stability. There is sex. Furthermore, changes in the SOA current can affect the temperature stability around the mirror, which affects mirror performance, and similarly, changes in the SOA current affect wavelength tuning and stability. Effect.

  In one implementation of the APC function in the field programmable device 531, the power of the SOA can be adjusted proportionally for each wavelength using a real-time control loop to maintain the output power. Data measurements showed that small incremental adjustments in the SOA may not significantly affect the wavelength because the APC and wavelength locker modules operate in concert.

In one aspect of the present disclosure, wavelength and power stability can be summarized as an example as follows.

Automatic wavelength mapping (AWM)
One of the limiting factors in reducing the power consumption of optical laser modules is that the laser temperature needs to be stabilized during operation in order to maintain the lasing wavelength within a certain accuracy range That is. Typically, the laser needs to be stable within a range of ± 0.05 ° C, especially in extreme regions of the temperature range (typical temperature range is -5 ° C to 70 ° C). Thermoelectric coolers (TECs) that are configured to facilitate can consume significant amounts of power to meet this baseline value. For example, when the laser needs to be at a temperature of 20 ° C. and the environment is 70 ° C., this means that the laser package is between 80 ° C. and 85 ° C., and the TEC has a temperature gap in the range of 60 ° C. to 65 ° C. It is necessary to straddle.

  In one aspect of the present disclosure, the means for reducing the load on the TEC, and in some instances the means for completely removing the load, are provided by the laser instead of keeping the laser control current constant and stabilizing the laser. The control current can be provided by automatically adapting to the temperature. Further, to illustrate the embodiment, instead of operating the laser at 20 ° C., the laser may be operated at 60 ° C., so the gap from the laser temperature to the laser package temperature is between 20 ° C. and 25 ° C. Can be reduced. This is based on measured temperature and by moving between tables pre-stored in a field programmable device (531 or 103) such as FPGA, PLD or the like, or some algorithms and This can be done “dynamically” by extrapolating between temperature wavelength maps using a fitting function. The effect of dynamic temperature setting of the wavelength tunable laser is that (i) the temperature delta (ie, the difference) between the wavelength tunable laser and the optical transmitter case temperature is set as the change in case temperature. By adjusting the temperature, it can be kept as small as possible, so it can include an overall reduction in the power consumption of the optical transmitter, and (ii) the operating temperature range of the optical transmitter can vary the laser temperature It can be expanded compared to existing technologies that set the temperature value.

  6A-6C show examples of gain voltage maps obtained by tuning the laser mirror current of a tunable laser at three different temperatures (eg, 20 ° C., 30 ° C., and 40 ° C.). In the present disclosure, these three different temperatures can be referred to as calibration temperatures. In one aspect, the tuning point or wavelength is one or more, such as the algorithms described in US Patent Application No. 62 / 073,713 and the corresponding utility patent application, which are incorporated herein by reference in their entirety. Multiple calibration algorithms are used to identify for each map and load into the FPGA.

  For example, FIG. 6A shows an example of a gain voltage map obtained by tuning the laser mirror current of a tunable laser having two mirrors at a temperature of 20 ° C. In the example, the gain voltage map is generated by observing the optical output power as the two mirror current values change. Furthermore, all the minimum values of the gain voltage map can be identified as the point at which the tunable laser is outputting maximum power through various processes, and thus the associated wavelengths can be extracted. This extracted wavelength (or peak of lasing wavelength) can be used to tune and calibrate the tunable laser process. Similarly, at temperatures of 30 ° C. and 40 ° C., corresponding gain voltage maps can be generated as shown in FIGS. 6B and 6C, respectively. Note that in the example, the gain voltage map varies based on the temperature value.

  In one aspect of the present disclosure, the automatic wavelength mapping process can be implemented as a parallel independent module or process within the field programmable device 103 or 531 and configured to allow the control loop to use the data at different calibration temperatures. can do. Adjustment of the tuning current for the laser mirror can be done using one or more algorithms, and points from the tuning map (or gain voltage map) are described in more detail below, as well as in FIGS. Shown in FIG. 7B. The temperature dependence of the mirror current can be estimated from the gain voltage map, and an analytical approximation can be derived. Next, the temperature dependence of the mirror current can be derived from no more than three gain voltage maps at different temperatures given detailed knowledge of the tunable laser itself.

As an example, the characteristic of the mirror current, I _mirror , as a function of temperature t can be approximated accurately by a second order polynomial as shown below.
I _mirror (t) = at ² + bt + c
Where a, b, and c are constants that may or may not be singular for a given wavelength, and t is the temperature of the laser. Thus, each channel may or may not require additional parameters for the channel to accurately apply the mirror current with varying temperatures.

  As described above, FIGS. 7A and 7B provide examples of tuning approximations for two laser mirror currents at wavelengths 1542.02 nm and 1577.16 nm versus temperature. In the example of the mirror current, a continuous current over 30 ° C. on the left curve, and one mirror current exceeds the maximum allowable current as shown at the bottom of FIG. The situation can be observed. The latter may not be desirable in some cases, so the example of a continuous current on the left curve may be the only viable option to use. Thus, with the two options, two options that can avoid the “wraparound” situation are: (i) performing a gain voltage scan generally finds each wavelength many times, and therefore Some of the wraparound channels can be removed, and (ii) the mirror can have a higher current limit and there may be an option to remove the remaining wraparound channels. In general, the latter can fully tolerate wraparound when the temperature is constant (in this case, the current changes only when the channel changes, and a significant current change is acceptable), thus reducing power consumption. To avoid. When the temperature is not constant, the mirror current can increase and therefore the power consumption of the PIC also increases as the cost of power is minimized compared to the amount that saves TEC power.

  Furthermore, as can be seen from FIGS. 6A-6C, it should be noted that different gain voltage maps are observed at different temperatures. As described herein, various aspects of automatic wavelength mapping, tuning, and calibration of a tunable laser are implemented in field programmable device 103 or 531 as one or more parallel independent modules or processes. Can then be configured to use data (eg, data relating to lasing wavelength, etc.) at different calibration temperatures. Furthermore, in one aspect of the present disclosure, the gain voltage map observed at different temperatures can be used to identify the lasing wavelength of the tunable laser at different temperatures. Also, the temperature of the tunable laser can be controlled in the field, via one or more currently running processes in the field programmable device, or through one or more graphical user interfaces described below. Can be adaptively changed. Alternatively, the laser mirror current can be automatically adapted at different temperatures based on the gain voltage map (also referred to herein as laser mirror current adaptation).

  In one aspect of the present disclosure, the remote operator communicates the laser current and temperature settings of the tunable laser through a process embedded in the field programmable device 103 or 531 (eg, FPGA or PLD, or the like). The parameter settings of the tunable laser can be fully controlled through various graphical user interfaces (GUIs) configured to do this. For example, the remote operator can change various parameter settings at different temperature settings and observe the spectrum of light output. In the example, FIGS. 8A-11B are configured to control the laser current and temperature settings at 23 ° C., 30 ° C., and 40 ° C., along with their respective output spectra, under operator control via the GUI. It shows the GUI that can.

  In one implementation, the functionality of the GUI is a field programmable device connected to the system via one or more wireless techniques, or connected to the system via an optical transmission line from a remote site or location, Or it can be integrated into a system containing field programmable devices. Specifically, GUI control functions can be performed in the system via one or more communication interfaces including API, I2C, GPIO, or others of the optical transmitter (or transceiver). Also, the one or more control signals may be a system GUI, a GUI connected to the system via one or more radio techniques, or another system at a site where one or more control signals are far away. Can be supplied from a GUI connected to the system via an optical transmission line. In addition, when one or more control signals come from another system's GUI at a remote site, the system's optical receiver reads and decodes the input signal directly to control the system's wavelength. be able to. Alternatively, one or more control signals from another system's GUI at a remote site can be received and decoded by a host coupled to the system, and then 1 to control the wavelength of the system. One or more commands can be issued.

  As an example, FIG. 8A shows the laser current and temperature settings from the GUI control 831 for a temperature value of 23 ° C., with the laser mirror current being adaptable, and FIG. 8B shows the corresponding optical spectral output 833. . FIG. 9A shows the laser current and temperature settings from the GUI control 931 for a temperature value of 30 ° C. with no laser mirror current adaptation, and FIG. 9B shows the corresponding optical spectral output 933. FIG. 10A shows the laser current and temperature settings from the GUI control 1031 for a temperature value of 30 ° C., with the laser mirror current being adaptable, and FIG. 10B shows the corresponding optical spectral output 1033. FIG. 11A shows the laser current and temperature settings from the GUI control 1131 for a temperature value of 40 ° C., with the laser mirror current being adaptable, and FIG. 11B shows the corresponding optical spectral output 1133.

  As described above, for the temperature values 23 ° C. and 40 ° C., only the state in which the current correction function is possible is shown, while for 30 ° C., the state with and without current correction is shown. Examples of laser current settings and spectra for both states are shown. At 30 ° C., the optical spectrum output is concentrated at 1577.160 nm when the laser mirror current is adaptable, while the optical spectrum output is at 1578.040 nm when the laser mirror current is not adaptable. Note that it is concentrated. Accordingly, the present disclosure runs in parallel within a field programmable device, as well as various parameter settings of the tunable laser, via one or more GUIs as shown in FIGS. 8A, 9A, 10A and 11A. Extended capabilities to control operational parameters for one or more processes can be provided to an operator at a remote location (eg, at a host device).

Linewidth Reduction Algorithm—Digital Signal Processing In one aspect of the present disclosure, the linewidth reduction algorithm is implemented as a parallel independent module or process within the field programmable device 103 or 531, such as an FPGA, PLD, or the like. Can be implemented digitally. As an example, linewidth reduction algorithms such as the pounded hole (PDH) technique are widely used and powerful to stabilize the frequency of light from a tunable laser by locking against a stable cavity. It is a technique. The range of applications for PDH techniques is broad and can include interferometric gravitational wave detectors, atomic physics, and time measurement standards, many of which also use related techniques such as frequency modulation spectroscopy.

  FIG. 12 shows an exemplary implementation of an analog PDH control system. The emitted light from the laser 1201 is separated by a splitter 1211 in several ratios, one part being phase modulated using an external clock source 1213. The phase-modulated signal is sent through a circulator 1215 to a Fabry-Perot filter 1217, and the reflected light from the Fabry-Perot filter 1217 is detected by a photodetector 1221 and then generates an error signal 1223. Therefore, it is mixed with the original clock source signal. The error signal 1223 is then signal processed and used on the laser to correct phase aberrations and thus reduce the line width of the signal. As described above, in one aspect of the present disclosure, as shown in FIG. 13, the PDH feedback loop is implemented as a parallel, independent module or process in a field programmable device for high bit rate coherent communication. can do.

  In one aspect of the present disclosure, an example of a system using a 100 Gbps transmitter that uses a wavelength locker system as a light detection system is shown in FIG. The advantage of the present disclosure for line narrowing or reduction required for coherent communications and other high bit rate communications (as well as spectrally efficient communications systems) is the clock speed independent of other control loop processing. That the control circuit can be implemented as an independent module or process in parallel in a field programmable device 103 or 531 such as an FPGA, PLD, or the like that runs on and optimized for the desired line width Can be included. Further, in one implementation, the same optical elements, optoelectronics, analog electronics, and analog / digital circuits used for other purposes, eg, wavelength locker 1323, are line narrowing, eg, PDH circuits Can be used in duplicate for 1325, thereby reducing the cost, complexity, size, weight and power of a small linewidth transceiver or transmitter that can be implemented according to one aspect of the present disclosure. Reduce. Thus, using the techniques described herein, all of the analog PDH control system building blocks shown in FIG. 12 can be implemented in a reprogrammable hardware gate in the field programmable device 103 or 531. it can. A diagram of a PDH linewidth control system that reuses (duplicates) the components of the wavelength locker is shown in FIG.

  Traditionally, the PDH algorithm uses analog electronics to form the filtering, demodulation, and feedback portions of the noise reduction loop. These functions can be problematic for running in a microprocessor or microcontroller due to some requirements regarding a constant low latency in the path from the detector to the laser phase modulator. is there. However, the advantage of the present technology is that the field programmable device 103 or 531 can implement a digital signal processing (DSP) function as a fixed dedicated module or process, and control the waiting time accurately. Can be offered to enable. Thus, the implementation of the PDH feedback loop according to the present disclosure greatly simplifies calibration and optimization of analog noise and electromagnetic interference (EMI) immunity from sources, and feedback loop characteristics and linewidth reduction performance. Can be programmed.

  FIG. 14 is a block diagram illustrating one embodiment illustrating the connection of a field programmable device (eg, FPGA or PLD, or the like) to an ADC, DAC, laser, and optical path, according to one aspect of the present disclosure. An example is shown. FIG. 15 illustrates an example block diagram illustrating an implementation of a filtering function embedded in a field programmable device for a PDH loop, according to one aspect of the present disclosure. In the example, the detected optical power from the reflected etalon optical path is digitized and fed into a field programmable device such as FPGA 1531, which filters and demodulates the PDH algorithm to provide a photonic integrated circuit (PIC). ) Configured to generate an error cancellation signal that drives the laser phase modulator in 1535. Similarly, the FPGA 1531 is configured to generate a reference modulation frequency for driving the phase modulator of the etalon input optical signal through the DAC, as shown in FIG.

  In another aspect of the present disclosure, in the example of FIG. 15, the equation for the power detected from the optical signal reflected by the etalon, expressed as a function of the difference between the reference modulation frequency and the typical unwanted frequency component, is 16 can be derived and used as shown in FIG. In this equation, the detected power (P) includes three components: a DC term 1601, a component at the modulation frequency (error signal 1603), and a component at twice the modulation frequency (diagnosis 1605). The double (2x) modulation frequency component (diagnostic 1605) can be used for system testing and calibration. In one example implementation of the PDH algorithm, the amplitude of the component at the modulation frequency (error signal 1603) can be derived from any external source by modulating the laser wavelength such that side lobes occur at the large slopes of the resonator response. Is proportional to the difference between the frequency component and the modulation frequency and reacts in the opposite direction to positive and negative phase perturbations, thus producing the desired error signal.

  Further, in one implementation of the PDH algorithm, as shown in FIG. 17, an error signal can be extracted and returned to the phase modulator in the tunable laser to cancel out unwanted components. Here, the logic circuit of the ADC interface receives the digitized power signal from the detector of the reflected path of the etalon. A digital FIR bandpass filter concentrated on the modulation frequency removes the DC and 2x modulation frequency components from the detected power signal. The bandpass output is then multiplied by the modulation frequency reference generated by the DDS. The calculation result is a demodulated error signal including an unnecessary 2 × modulation frequency component. As a result, an FIR low-pass filter with a cutoff at approximately the modulation frequency removes unnecessary 2x modulation frequency components while leaving any error components up to the modulation frequency. The resulting error signal passes through the gain and offset block, provides the proper amplitude and DC offset to drive the laser phase modulator, and then formats and sends the data to the DAC for DAC logic. go to. The designed latency in the example path shown between the detected power from the etalon and the laser phase electrode, including external ADC and DAC, is less than 500 ns, the main contribution is from the FIR filter . The optimization of the algorithm described above may result in even lower latency. The reference DDS makes a phase adjustment of the modulator reference signal sent to both the demodulator and the reference phase modulator so that the response can be null for initial calibration. Gain and offset adjustments are also made to the reference modulation output. FIR filter coefficients, reference frequency, and phase, gain, and offset are all programmable by the host to facilitate optimization, tuning and calibration of tunable laser algorithms associated with the tunable laser and system. To do. Thus, in one aspect of the present disclosure, the line width reduction algorithm may be digitally implemented as a parallel and independent module or process within a field programmable device 103 or 531 such as an FPGA, PLD, or the like. it can.

Real-time monitoring of parameters Many parameters in the tunable laser / modulator require real-time monitoring and feedback to the dynamic control loop. Parameters also require measurements at many operating points for calibration and analysis purposes, and the speed at which these measurements can be performed can be important to enable large scale production of tunable lasers. .

  In one aspect of the present disclosure, the technology enables the production of such large scale tunable lasers. In other words, a parallel architecture that can be created using field programmable devices such as FPGAs or PLDs, or the like, allows for monitoring of critical parameters and allows parameters to be multiplexed into multiple control loops simultaneously with minimal latency. Again, the microprocessor or microcontroller needs to process and distribute all of the information in a continuous and / or sequential manner.

As described above, a mounting form centered on a field programmable device (for example, a mounting form centered on an FPGA / PLD) can be described as one embodiment of the present disclosure. Of parameter monitoring, field programmable devices (103, 531, etc.) allow multiple ADC channels to be fully programmable with respect to the order and frequency per channel, although channel readout occurs with minimal overhead. For example, it can be configured to control the read cycle to 24 ADC channels. This aspect of the present disclosure makes it possible to monitor parameters that are important to a real-time control loop frequently enough to provide data for real-time control such as wavelength locking, power control and temperature control. Can do. Table 1 below lists some of the real-time control and calibration algorithms, along with representative parameters and sample rates that need to be monitored for each.

  As can be seen from Table 1 above, there are two things: (i) that some parameters need to be supplied by more than one function, and (ii) some parameters are others You can notice that it needs to be sampled much faster than this parameter. Accordingly, one or more implementations based on field programmable devices according to aspects of the present disclosure maximize efficiency and allow all processing to obtain the required data at a sufficient rate simultaneously. Allows for the flexibility to design monitoring functions.

  For example, FIG. 18 shows a block diagram example of firmware control of a field programmable device 1831, eg, FPGA / PLD firmware, and associated ADC and DAC 1833 used to monitor parameters. In the example, all real-time control loops are configured to run in parallel at independent rates, eg, independent clock rates (eg, 10 kHz, 6.25 kHz, 100 MHz, 1 kHz, and 20 MHz in FIG. 18). Can do. The parameters required for the real-time control loop are monitoring and control logic 1835 that can be configured to access the parameters through one or more SPI buses 1837 interfaced to ADCs, DACs, and other devices. Can be supplied by. In addition, field programmable devices 1831, eg, FPGA, PLD, or the like, can build multiple SPI interfaces, each with a different protocol, for devices that need to be accessed with high priority. And at the same time maximize bandwidth and run with near zero overhead on the SPI interface shared by multiple devices. In addition, parameters required by multiple control loops can be distributed to all required functions simultaneously, while parameters required by some functions at high bandwidth but not required by other functions are necessary. Depending on the number of monitoring devices.

  As a result, in one aspect of the present disclosure, real-time control functions can be implemented in the field programmable device 1831 as one or more parallel and independent processes in the field programmable device 1831, and thus monitoring and control The parameters received from logic circuit 1835 can be analyzed and used to generate alarms and status that are returned to the host via host or register interface 1841 and / or discrete 1843. Further, in the example, generated alarms can include (i) laser temperature yellow and red alarms, (ii) laser power yellow and red alarms, (iii) laser on, and (iv) stable lambdas. . Further, in another aspect, the field programmable device 1831 can also run the calculation and determination process for alarms in parallel, minimizing the latency to report abnormal conditions to the host.

Wavelength Locking The wavelength locking algorithm is based on the Fabry-Perot etalon's response and dynamically tunes the laser wavelength to maintain the laser wavelength at an accurate set point with respect to changing operating conditions. Typically, etalons have a peak response at wavelengths and intervals consistent with standard ITU specifications, but in principle the wavelength should be any value or interval depending on the etalon design.

  FIG. 19 shows an example of a general etalon reflection and transmission response. The transmit response 1901 has a peak at the wavelength of interest, while the reflection response 1903 has a minimum at these same wavelengths. The etalon's maximum and minimum exquisiteness or sharpness reduces the accuracy with which wavelength locking is performed to create an etalon shape that is physically small enough to be placed with other optical elements in a removable module You can make a trade-off. In one aspect of the present disclosure, efficient measurement of etalon responses and algorithmic processing of measurements is possible with improved quality of results.

  To find the etalon peak and / or minimum corresponding to the desired operating wavelength, the laser first tunes the mirror based on a pre-calibrated mirror current value and corresponding wavelength table, Tuned near the exact wavelength. The wavelength locking algorithm then dithers the laser phase electrode current to a narrow range around the default precalibration value and fine tunes the wavelength by searching for peak and / or minimum response. The algorithm can be implemented digitally by controlling the current DAC that drives the laser phase electrode and monitors the etalon response through the ADC.

  FIG. 20 illustrates an example block diagram illustrating another implementation of a wavelength locking algorithm according to one aspect of the present disclosure. Here, the wavelength locking algorithm is executed digitally by controlling the current DAC 2051 that drives the laser phase electrode and monitors the etalon reaction through the ADC 2051. In an example implementation, the phase dithering speed is a compromise between obtaining the latest information on the phase offset at a sufficient rate, and thus the operating wavelength, and minimizing the linewidth effect of dithering. be able to. An example of this technique can step the phase at a rate of 100 μs. The dithering amplitude can also be a compromise between scanning over a wide enough range to capture the maximum / minimum values and not scanning as long as the laser 2053 mode hops persist. The scan amplitude (or range) in the example implementation may be programmable and can be set for each wavelength based on a calibration table, but is generally in the range of +/- 1 mA of the phase electrode current. .

  In one aspect, detected etalon transmit and reflected power received from ADC 2059 (via detector 2058 coupled to circulator 2055 and etalon 2057) is then used to reduce noise and level the response. And processed through an averaging filter 2033. Field programmable device 2031, such as an FPGA, PLD, or the like, is configured to facilitate filtering transmit and reflected power data in parallel. The algorithm then passes the maximum / minimum value search 2035 to request the data to exceed the minimum / maximum above / below threshold at points on either side of the minimum / maximum value in the scan. Based on finding the maximum / minimum value for the set and confirming that this value is actually the inflection point, we will try to find the maximum value in the transmitted data and the corresponding minimum value in the reflected data To do. The average of the identified maximum and minimum points is then used as a new phase offset applied to the laser 2053 to set the wavelength fine-tuning. If the algorithm fails to find an acceptable minimum or maximum value, the new phase offset is based on a well-specified inflection point, or if neither minimum nor maximum value is specified, for the current scan Data is not used and the phase does not change until acquired by a successful scan. The new phase offset is provided to phase offset 2037 and laser 2053 via DAC control 2039 and current DAC 2051. Furthermore, the wavelength locking algorithm described above can be implemented as one or more parallel and independent processes in a field programmable device (103, 531, or the like) such as an FPGA, PLD, or the like. Please note that.

  Further, phase modulation may require achieving at least one or more of the following: (i) wavelength locking, (ii) linewidth reduction, and (iii) Brillouin scattering mitigation. Please note that. As an example, in one implementation, the laser wavelength is interfaced via an SPI, via a multi-channel current DAC driving a laser electrode, via a field programmable device such as an FPGA or PLD, or the like. Tuned under control. The initial mirror and phase electrode currents for the commanded wavelength can be set via a look-up table, and the wavelength locking control loop can detect the power of the detected etalon to maintain wavelength stability. You can run continuously based on. Accordingly, field programmable devices (eg, FPGA, PLD, or based on real-time control algorithm implementations) because independent control loops can be tuned independently without affecting overall system performance and timeline. The same) facilitates enhancement and optimization.

Temperature Control In another aspect of the present disclosure, processing for temperature control of a tunable laser is performed in parallel in a field programmable device (eg, FPGA / PLD) configured to run with a different clock signal than other processing. Can be implemented as an independent process. FIG. 21 shows an example of a diagram of one implementation of temperature control processing. As an example, module 2129 (eg, temp_pid) monitors and controls the associated TEC 2131 through the TEC controller 2135 using a discrete PID loop. Module 2129 can be configured to receive the desired temperature as input and servo at a configurable sample rate (time constant) until the actual temperature of the TEC is equal to the set temperature.

  Module 2129 (eg, temp_pid) monitors the temperature of the TEC, compares the temperature of the TEC to a set temperature (eg, a temperature set point), and adjusts the TEC drive current to achieve the desired temperature. The TEC 2131 can be controlled through a linear control chip. Thus, the temperature can be monitored via a localized thermistor and selected ADC channel. The TEC drive current can also be monitored via the linear control chip and the selected ADC channel. The TEC drive current can also be calculated based on the output of the PID loop, the set temperature, and the actual TEC temperature. Thus, the output of the PID loop drives the selected DAC channel that specifies the output current of the controller.

As described above, the module 2129 (eg, temp_pid) is configured to monitor and control the associated TEC 2131 through the TEC controller circuit 2135. Module 2129 can be configured to receive a desired temperature value as input and servo at a configurable rate (time constant) until the actual temperature of the TEC is equal to the set temperature. Maximum TEC currents and maximum and minimum temperatures can also monitor alarm conditions indicated by red and yellow alarm outputs. The algorithm used for the servo may include a PID loop that uses the following discrete time domain formula:
u (k) = u (k-1) + a0 * e (k) + a1 * y (k) + a2 * y (k-1) + a3 * y (k-2)
Where u (k) is the output,
u (k−1) is the precomputed output,
e (k) is the difference between the set temperature and the actual temperature, y (k), y (k-1), y (k-2) are one and two sample delay input temperatures from the TEC controller.

The values a0, a1, a2, and a3 can be derived from the PID coefficients Kp, Ki, Kd, and the sample period Ts as follows.
a0 = Ki * Ts,
a1 = Kp− (Kd / Ts),
a2 = Kp + (2Kd / Ts),
a3 = −Kd / Ts.

  The structure of the ALU used to generate u (k) may consist of a 16x16 multiplier using a 4: 1x16 multiplexer for each input followed by a 36-bit adder using an accumulator register. it can. A block of 16-bit subtractors generates a value for e (k). u (k) and u (k−1) are checked to avoid windup or overflow and are in a range limited to x “1000”. The accumulator will be the value of u (k−1) for the next iteration. The input multiplexer and multiplier and ALU are all pipelined and can use two clocks for the first product and sum, one clock each for the next three multiplications and additions can do. The accumulator can then hold u (k), which is u (k-1) for the next cycle.

In one aspect of the present disclosure, there may be two error indicators, a red alarm and a yellow alarm. A red alarm can mean that the maximum temperature, current, or temperature difference has been exceeded. If the red alarm occurs after the initial period of suppressing the TEC stop and the set temperature is achieved during the PID loop time, the red alarm causes the TEC to stop and the laser to stop. There may be multiple procedures such as:
TEC_init_proc: When the TEC is first enabled, the red alarm stop is suppressed for a period proportional to the sample period, but for about 5.8 seconds or more.
Temp_control: Set and monitor alarm limits, current limits, and PID limits.
PID_proc: A finite state machine (FSM) that controls PID ALU initialization and PID ALU prioritization.
Pid_mpy_inst: an instance of an embedded parallel signed 16x16 multiplier using a synchronous 32-bit output register. This may be part of the PID ALU.
Local_CLK_Proc: Programmable sample clock generator with 100 μs increments.

  Further, in one aspect of the present disclosure, PID constants and sample periods can be estimated and set. The PID constant can be estimated using the Ziegler-Nichols method, which may require knowledge of the frequency at which the control loop oscillates a given sufficient gain without a differential or integral term. . Furthermore, it may not be possible to obtain this value that requires steady state vibration due to safety limitations imposed on the design. Instead, Tu can be estimated from the damped oscillation period and Ku can be estimated.

  In one aspect of the present disclosure, a simple TEC first-order model (individual coefficient low-pass filter) and PID servo are created in a spreadsheet using discrete coefficients a0-a3 derived from the PID values. be able to. The setpoint step change with temperature generates a loop step response using the selected PID constants, Kp, Ki, and Kd, and the sample period Ts, and the model transfer coefficient, “xfer_coeff”. be able to. Responses can be graphed so that the results can be viewed interactively. The real coefficient input to the PID module can also be multiplied by 128, taking into account the binary point and fractional coefficients in bit 6. In addition, the Ziegler-Nichols table can be implemented to give initial values for PID constants given Ku and Tu estimates.

サンプルレートおよび１次のフィルタ係数を選択した後、スプレッドシートの「Ｋｕ、Ｔｕ」ワークシートを使用してＫｕを、次にＴｕの値を発見できることに留意されたい。 In addition, there may be two panes in the spreadsheet to calculate the variables. The first pane can be used to interactively discover Ku and Tu, and the second pane interacts with the optimal Kp and Ki for SFP (with the derivative term set to zero) Can be used to expand in form. Further, in one aspect of the present disclosure, the Ziegler-Nichols method can assign a coefficient of PID using the following technique based on experimental data or simulated plant behavior.
Set the coefficients Ki and Kd to zero.
Increase the (gain) coefficient Kp until the loop oscillates with a constant amplitude.
• Period of vibration-note that this is the Tu in the table below.
Gain value Kp—Note that this is Ku in the table below, ie the ultimate gain.

Note that after selecting the sample rate and first order filter coefficients, the “Ku, Tu” worksheet in the spreadsheet can be used to find Ku and then the value of Tu.

Boxcar Filter In one aspect of the present disclosure, one or more multi-channel moving average (also known as “boxcar”) filters are digitally implemented in a field programmable device (eg, FPGA or PLD). The boxcar filter can be configured to provide configurable low-pass filtering for each of the 24 ADC channels in a 10G TOSA electronics circuit board, for example. Each of the 24 channels can be set to a different filter depth of samples 0, 1, 2, 4, 8, 16, 32, 64, 128, or 256. This capability can allow for the filtering of ADC output data that is required for short-term fluctuations or random higher frequency noise. Filter depth and availability can also be programmed through a series of channel numbers associated with registers in the register's memory space. Before specifying that the filtered output is valid, the sample memory for a given filter channel must be filled with samples. Thus, in one implementation, when samples are taken, the sum of all samples and the new sample minus the oldest sample can be averaged and expressed as the output value of the filter.

  In one aspect of the present disclosure, one or more boxcar filters are internal to a field programmable device (eg, FPGA or PLD) for data history storage, addressing and indexing, and accumulation for each channel. It can be implemented using a memory block. As an example, individual 24-bit ALUs in a field programmable device can be used for data summing, and the sum can shift multiple positions to the right appropriate for the depth of each filter. it can. In one implementation, from input to output can take approximately 10 system clock times (approximately 400 ns). Because the sample rate of the associated analog subsystem can be about 4 kHz / channel, the boxcar filter can easily adjust all channels while adding very small delay times. A block diagram for a symbol model of one channel of the boxcar filter is shown in FIG.

Nonvolatile Memory Storage In one aspect of the present disclosure, registered memory maps and device wavelength table states may be stored in one or more nonvolatile flash memories (eg, Mcronix flash memory, MX25L4006E). . Each flash memory can be a 4MB capacity device and can be essential during device startup to apply the proper nature and to maintain the overall system behavior set by the end user There is sex. When writing, there may be a series of registers that write the bytes directly to the flash. Therefore, when power is circulated, the byte data is maintained, and the property set by the user can be maintained. An example of the address space of the nonvolatile flash memory can be set as shown in FIG. 23A. The wavelength definition table can be set as shown in FIG. 23B. Each wavelength table can be a 32-byte structure, and each device can contain storage space for many wavelength tables, whether internal or external to the field programmable device. .

Boot-up Flash Procedure for Reading Registers and Wavelength Tables In one aspect of the present disclosure, upon startup of an optical communication system or device, the device is placed in a state determined by the end user due to the nature of the on-board firmware. There are two steps that can be taken. For example, the procedure can include loading a registered memory map into the firmware system and copying the wavelength table to a storage area of the communication system RAM. Each of the memory spaces can be set as 4096 bytes (4 KB). As shown in the flash memory map of FIG. 23A, the register memory map can begin at 0x70000. At startup, the first procedure performed by the nature of the onboard firmware is to copy the register values to the firmware register space. The second procedure performed is to copy the wavelength table from the flash starting at 0x71000 to the wavelength RAM space on the device. Once all of the memory has been copied from the flash, the register value for “wavelength of current” is read by the device, and that wavelength is written to the laser electrode register. At this point, the device can be fully booted and configured, loaded with the selected wavelength, and ready for operation. In this implementation, it may take approximately 0.4 ms to copy all of the register and wavelength data from the flash storage device.

Application programming interface (API)
In one aspect of the present disclosure, an application programming interface (API) can be implemented by a DLL executable library. By importing the API DLL into the project encoding, the API user has access to the function of controlling the tunable laser control electronics. The API functions available to the user allow the user to properly open the serial communication port, read from and write to the register interface, and directly read the device temperature, set the electrode current, and monitor voltage Can be enabled to read, set the wavelength, and provide some higher level macro functions for turning the laser and laser TEC on and off. Thus, the present disclosure can provide software-enabled features that can be accessed via an API, for example, extensive real-time control and monitoring of one or more modules or processes based on actual traffic. Present. As noted above, such programmability is the result of an unprecedented level of flexibility and responsiveness in the optical layer by scaling bandwidth in real time and transmitting separately, providing a given fiber optic installation. Provides higher bandwidth extraction from the network, as well as reduced complexity and associated costs associated with planning, building, operating and maintaining data networks.

  While the foregoing written description of the disclosure allows those skilled in the art to make and use what is currently considered the best mode, those skilled in the art It will be understood and appreciated that combinations exist, and equivalents of the specific embodiments, methods, and examples herein. Accordingly, the present disclosure should not be limited by the embodiments, methods, and examples described above, but should be limited by all embodiments and methods within the scope and spirit of the present disclosure.

  Also, various aspects of the disclosure may be implemented by one or more processing systems. For example, host controller 101, field programmable device 103, or laser 109 can be implemented with a bus architecture, as shown in FIG. 24, which includes a bus and any number of interconnecting buses and bridges. Can do. The bus links various circuits together, including one or more processing systems, one or more memories, one or more communication interfaces, and input / output devices. One or more processing systems are responsible for managing the bus and overall processing, including execution of software stored on non-transitory computer readable media. As described above, the one or more processing systems may include one or more reconfigurable circuit blocks that interpret and execute instructions. In an example implementation, the one or more processing systems may be implemented or include one or more application specific integrated circuits, field programmable logic circuit arrays, or the like. The software, when executed by one or more processing systems, causes the one or more processing systems to perform various functions described herein for any particular device. A non-transitory computer readable medium may also be used to store data that is manipulated by one or more processing systems when executing software. The one or more memories include various types of memory including random access memory or read only memory, and / or other types of magnetic or optical recording media, and corresponding devices for storing information and / or instructions Can be included. The one or more input / output devices may include devices that allow input and / or output of information to external devices or equipment. The one or more communication interfaces can also include any transceiver, such as a mechanism that allows communication with other devices and / or systems including optical transceivers (eg, TOSA and / or ROSA). .

  Although specific combinations of features are disclosed herein and / or recited in the claims, these combinations do not limit the disclosure of the technology. Further, the method or methodology for the present technology disclosed herein includes software, hardware, any combination of software and hardware, as well as discrete hardware circuitry, gate logic, state machines, programmable logic devices (PLDs). ), Field programmable gate array (FPGA), application specific integrated circuit (ASIC), and other suitable hardware configured to perform the various functions described herein. It can be implemented in a computer program or firmware installed in a computer readable medium for execution by a processing system.

  As used herein, the term “software”, “module”, or “processing” refers to any instruction, instruction set, including firmware, microcode, middleware, software, hardware description language, or the like. Widely interpreted to mean a program, subprogram, code, program code, software module, application, software package, routine, object, executable, execution thread, procedure, function, etc. Software can also include various types of machine language instructions including instructions, code, programs, subprograms, software modules, applications, software packages, routines, subroutines, executables, procedures, functions, etc. Further, software can refer to general software, firmware, middleware, microcode, hardware description language, or others. As described above, the software can be stored on a computer-readable medium.

  Examples of computer-readable media include, for example, optical discs, magnetic storage devices, digital versatile discs, flash memory, random access memory (RAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM: synchronous dynamic random access memory), read only memory (ROM), register, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM: electronically erasable PROM) Disk, flash memory device, and And non-transitory computer readable media such as any other suitable media for storing software that can be accessed and read by a processor or processing system. Description of various functions that may be implemented in one or more field programmable devices, either stand-alone or in combination with one or more computer systems that depend on a particular application within design constraints It is also understood that those skilled in the art will recognize the best way to implement the functionality provided.

  As used herein, the term “unit” or “component” means software, hardware, or any combination thereof. A component is a software component that includes a field programmable gate array (FPGA), a digital logic circuit, a digital logic circuit array, an application specific integrated circuit (ASIC), a digital signal processor (DSP), etc., or any combination thereof , Hardware components, or any combination thereof. Thus, components can include software components, task components, processes, procedures, functions, program code, firmware, microcode, circuits, data structures, tables, arrays, and variables.

  For simplicity, the methodology has been described herein as a series of steps or actions, but some steps or actions may occur in a different order and / or in parallel than the order shown and described herein. Thus, it should be understood that claimed subject matter is not limited by the order of steps or actions. Moreover, not all illustrated steps or acts are required to implement various methodologies in accordance with the technology disclosed herein. Moreover, the methodologies disclosed throughout this specification and throughout this specification can be stored in an article of manufacture to facilitate the transfer and transfer of such methodologies to one or more processing systems. it can. The term “article of manufacture” as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or media.

  As used herein, the terms “first”, “second”, and the like can be used to describe various components, but the components are not limited by the above terms. The above terms are only used to distinguish one component from the other. For example, the second component can be referred to as the first component without departing from the scope of the present disclosure, and in a similar manner, the first component can be referred to as the second component. . In addition, the term “and / or” used herein includes any item of a combination of a plurality of related elements or a plurality of related elements.

  Furthermore, when describing one part “couple” or “connect” to another part, the part can be directly coupled to or directly connected to another part, or the part can be a third part Note that it can be connected to or connected to other parts through. The singular form can include the plural form if there is not clearly a contrary meaning in the context. In this disclosure, the term “comprising” or “having” as used herein means that there are any feature, operation, component, step, number, part, or any combination thereof described herein. Means. However, the term “comprising” or “having” does not exclude the presence or additional possibility of one or more other features, operations, components, steps, numbers, parts, or combinations. Also, as used herein, the article “a” is intended to include one or more items. Further, no part, act, step, or instruction used in the present disclosure should be construed as critical or essential to the present disclosure unless explicitly described as such in the present disclosure.

  While the technology has been illustrated in the specific examples described herein to illustrate example embodiments, a wide variety of alternative and / or equivalent implementations can be used without departing from the scope of the disclosure. It will be appreciated by those skilled in the art that they can be used in place of the illustrated and described embodiments. Accordingly, this disclosure is intended to cover any adaptations or variations of the examples and / or embodiments shown and described herein without departing from the spirit and scope of this disclosure.

Claims (20)

An apparatus for controlling, monitoring and / or communicating with an optical device, photonic integrated circuit or subassembly comprising:
An optical device or subassembly;
A field programmable device including a programmable hardware gate coupled to the optical device or subassembly, wherein the plurality of functions at a gate level to control, monitor, and / or communicate with the optical device or subassembly And a field programmable device in which each of the plurality of functions is configured to run as parallel processing without the use of a microprocessor or microcontroller.   The apparatus of claim 1, wherein the plurality of functions are configured to run with different clock signals within the field programmable device.   The apparatus of claim 1, further comprising one or more analog / digital conversion (ADC) circuits and digital / analog conversion (DAC) circuits coupled to the field programmable device.   One or more of said optical devices or subassemblies wherein said field programmable device is selected from the group consisting of a tunable laser, an optical data modulator / demodulator, internal or external optical and optoelectronic monitoring and control functions, or The apparatus of claim 1, configured to control a plurality of parts.   The apparatus of claim 4, wherein the field programmable device comprises one or more field programmable gate arrays (FPGAs) or programmable logic devices (PLDs).   Based on the measured temperature and / or by extrapolating between temperature wavelength maps, the field programmable device moves between tables stored in the field programmable device. The apparatus of claim 4, wherein the apparatus is configured to automatically adapt a laser control current of the tunable laser to the measured temperature to reduce a load on a cooler (TEC). The field programmable device is
(I) control and / or monitoring of laser output power;
(Ii) control and / or monitoring of temperature-sensitive components associated with the optical device or subassembly;
(Iii) control and / or monitoring of the laser wavelength of the tunable laser;
(Iv) control of the wavelength locker function;
2. The device of claim 1, configured to run one or more functions selected from the group consisting of: (v) control and / or monitoring of one or more communication interfaces coupled to a host. apparatus.   The apparatus of claim 1, wherein the optical device or subassembly comprises a communication interface integrated in the field programmable device, preferably the programmable device comprises a field programmable gate array (FPGA).   A graphical user interface (GUI) that enables control, monitoring, and / or communication to a tunable laser, optical data modulator / demodulator, or other optical or optoelectronic component monolithically integrated 9. The apparatus of claim 8, comprising one or both of sockets to an application programming interface (API).   10. The apparatus of claim 9, wherein a software layer is used to interact with a tunable laser through the field programmable device to implement a fast wavelength calibration algorithm.   The field programmable device is configured to implement one or more functions including a soft state machine, an electronic filter, a control and feedback loop, a decision circuit, and a communication interface, each function within the field programmable device The apparatus of claim 1, wherein the apparatus is implemented as parallel processing with different clock signals.   The plurality of functions includes a pounded hole (PDH) algorithm to reduce the line width of light from the tunable laser and / or stabilize the frequency of light from the tunable laser. The apparatus according to 1.   The PDH algorithm is implemented in a reprogrammable hardware gate of the field programmable device, and some of the reprogrammable hardware gates are used to implement a wavelength locking function. 12. The apparatus according to 12.   The reprogrammable hardware gate of the field programmable device is a host communication interface, memory map, wavelength memory and management, programmable read only memory (PROM) to external erasable programmable read only memory (EPROM) -serial peripheral device Interface (SPI) flash interface, set current and voltage for the optical device or subassembly, monitoring of optical and electronic components, boxcar averager, automatic power control, wavelength locking, line narrowing algorithm, temperature A small number of monitoring and control, alarm generation, status monitoring, control and communication, and application programming interfaces Both are configured to implement one, according to claim 13.   One from a graphical user interface (GUI) coupled to the device via wireless communication or from a GUI of another device installed at a remote site on an optical communication link; The apparatus of claim 1, wherein the apparatus is configured to receive a plurality of control signals. An optical modulator or semiconductor optical amplifier, an optical device or subassembly comprising a tunable laser integrated on the same substrate as the non-integrated optical and optoelectronic components;
A field programmable device including a programmable hardware gate coupled to the optical device or subassembly and a laser transmitter and receiver, wherein the optical device or subassembly controls, monitors, and / or communicates with the optical device or subassembly. A field programmable device configured to implement a plurality of functions at a gate level, each of the plurality of functions configured to run as parallel processing without using a microprocessor or microcontroller; An optical communication system comprising:   The optical communication system of claim 16, wherein the field programmable device comprises one or more field programmable gate arrays (FPGAs) or programmable logic devices (PLDs).   The optical communication of claim 17, wherein the field programmable device is configured to include an application programming interface (API) for real-time control and monitoring of the optical device and subassemblies based on actual traffic. system.   The optical communication system according to claim 16, wherein the plurality of functions are configured to run with different clock signals in the field programmable device.   Graphical enabling the field programmable device to control, monitor and / or communicate with the tunable laser integrated on the same substrate as the optical modulator and the semiconductor optical amplifier, non-integrated optical and optoelectronic components The optical communication system according to claim 16, comprising a communication interface including one or both of a socket for a user interface (GUI) or an application programming interface (API).

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