JP2018101648A - Nitride semiconductor device - Google Patents

Abstract

To provide a nitride semiconductor device capable of reducing contact resistance and reducing on-resistance while minimizing an increase in chip size. A nitride semiconductor device is formed on a substrate (15), an electron transit layer (13) made of a nitride semiconductor formed on the substrate (15), and an electron transit layer (13). An electron supply layer (11) that is made of a physical semiconductor and forms a heterojunction interface (111) with an electron transit layer (13), and is formed in the vicinity of the electron supply layer (11) and the heterojunction interface (111). And a recess part (30) formed on a part of the upper side of the electron transit layer (13), and at least a part of the recess part (30). And an ohmic electrode (18). The width of the portion where the ohmic electrode (18) is in contact with the electron transit layer (13) is 2.0 μm or more. [Selection] Figure 1

Description

  The present invention relates to a nitride semiconductor device provided with an ohmic electrode.

  In semiconductor power devices, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) made of silicon semiconductors are the mainstream and widely used. In recent years, this silicon semiconductor device is approaching the physical property performance limit, and it is becoming difficult to further increase the breakdown voltage, reduce the on-resistance, and increase the speed.

  At present, expectations are growing for gallium nitride (GaN), which is one of compound semiconductors, as a new semiconductor material that replaces silicon. This gallium nitride has better physical properties than silicon. Specifically, gallium nitride has a higher dielectric breakdown electric field and a wider band gap than silicon, and can have a high breakdown voltage and a low on-resistance.

  Conventionally, there has been a HEMT (High Speed Electron Mobility Transistor) using gallium nitride that focuses on reducing on-resistance. In general, as a factor contributing to the on-resistance, a resistance of a two-dimensional electron gas (2DEG), a contact resistance between an ohmic electrode and a nitride semiconductor layer, and other parasitic resistances are considered. For this reason, to reduce the on-resistance, it is necessary to increase the concentration of the two-dimensional electron gas, to reduce the contact resistance between the ohmic electrode and the nitride semiconductor layer, and to reduce other parasitic resistance.

  For example, there is a HEMT described in Patent Document 1 (Japanese Patent No. 4333352). As shown in FIG. 7, the HEMT includes an electron supply layer 522 and an electron transit layer 520 made of a nitride semiconductor. It penetrates the electron supply layer 522 and a two-dimensional electron gas layer 536 formed in the vicinity of the heterojunction interface between the electron supply layer 522 and the electron transit layer 520, and part of the upper side of the electron transit layer 520 includes A recess 564 is formed. One end portion of the ohmic electrode 562 is disposed in the recess portion 564. One end portion of the ohmic electrode 562 has a substantially arc-shaped surface 568b protruding toward the outside of the ohmic electrode 562, and is in contact with the two-dimensional electron gas layer 536 on the curved surface 568b. This increases the area of the portion where the curved surface 568b of the ohmic electrode 562 contacts the two-dimensional electron gas layer 536, reduces the contact resistance between the ohmic electrode 562 and the electron transit layer 520, and reduces the on-resistance. doing.

Japanese Patent No. 4333352

  However, in the above-described conventional HEMT, it is considered that the contact resistance is determined only by the area of the portion where the ohmic electrode is in contact with the two-dimensional electron gas layer, so that it is necessary to increase the chip size in order to increase this area. There was a problem.

  Accordingly, an object of the present invention is to provide a nitride semiconductor device capable of reducing contact resistance and reducing on-resistance while minimizing an increase in chip size.

  The inventor of the present application diligently studied the reduction of the on-resistance of the HEMT. And this inventor is not only the area of the part which an ohmic electrode contacts with a two-dimensional electron gas layer, but the area of the part where an ohmic electrode contacts with electron transit layers other than a two-dimensional electron gas layer is contact resistance and unit. It was discovered that the on-resistance per area was affected.

The nitride semiconductor device of the present invention was made based on the above discovery,
A substrate,
An electron transit layer made of a nitride semiconductor formed on the substrate;
An electron supply layer formed on the electron transit layer, made of a nitride semiconductor, and forming a heterojunction interface with the electron transit layer;
A recess formed in a part of the upper side of the electron transit layer while penetrating the electron supply layer and the two-dimensional electron gas layer formed in the vicinity of the heterojunction interface;
An ohmic electrode formed so as to cover at least a part of the recess,
A width of a portion where the ohmic electrode is in contact with the electron transit layer is 2.0 μm or more.

In the nitride semiconductor device of one embodiment,
The width of the portion where the ohmic electrode is in contact with the electron transit layer is 4.0 μm or less.

The nitride semiconductor device of the present invention is
A substrate,
An electron transit layer made of a nitride semiconductor formed on the substrate;
An electron supply layer formed on the electron transit layer, made of a nitride semiconductor, and forming a heterojunction interface with the electron transit layer;
A first recess portion and a first recess portion that penetrate through the electron supply layer and a two-dimensional electron gas layer formed in the vicinity of the heterojunction interface and are spaced apart from each other on a part of the upper side of the electron transit layer. A recess portion having two recess portions;
A first ohmic electrode formed to cover at least a part of the first recess,
A second ohmic electrode formed to cover at least a part of the second recess portion;
A gate electrode formed between the first ohmic electrode and the second ohmic electrode;
The widths of the portions where the first ohmic electrode and the second ohmic electrode are in contact with the electron transit layer are 0.5 μm or more and 4.0 μm or less, respectively.

In the nitride semiconductor device of one embodiment,
An N-type dopant is doped at the interface between the electron transit layer and the recess.

  According to the present invention, the structure in which the ohmic electrode is in contact with the electron transit layer has a width of 2.0 μm or more, so that the contact resistance can be reduced and the on-resistance can be reduced while minimizing the increase in chip size. .

1 is a schematic cross-sectional view showing the vicinity of an ohmic electrode in a nitride semiconductor device according to a first embodiment of the present invention. It is a figure which shows the relationship between the contact width of the said ohmic electrode and an electron transit layer, and contact resistance. It is a schematic cross section of the nitride semiconductor device of the second embodiment of the present invention. It is a figure which shows the relationship between the contact width of the said ohmic electrode and an electron transit layer, and the on-resistance of the said nitride semiconductor device. It is a schematic cross section which shows the vicinity of the ohmic electrode in the nitride semiconductor device of 3rd Embodiment of this invention. It is a schematic cross section of the nitride semiconductor device of the fourth embodiment of the present invention. It is a schematic cross section showing the vicinity of an ohmic electrode in a conventional nitride semiconductor device.

  Hereinafter, the present invention will be described in detail with reference to illustrated embodiments. Each figure is a simplified diagram for understanding the present invention, and does not necessarily match an actual device such as shape and film thickness. Further, numerical values such as materials and film thicknesses described for the purpose of explanation in the embodiments are merely examples.

(First embodiment)
FIG. 1 is a schematic cross-sectional view showing the vicinity of an ohmic electrode in a GaN-based HFET (High speed Electron Mobility Transistor) according to the first embodiment of the present invention.

  As shown in FIG. 1, in this embodiment, a nitride semiconductor layer 16 in which a buffer layer 14, an electron transit layer 13, and an electron supply layer 11 are stacked in this order is formed on a substrate 15.

  The electron transit layer 13 is composed of undoped GaN, and the electron supply layer 11 is composed of undoped AlGaN having a wider band gap than the electron transit layer 13.

  On the electron transit layer 13 side of the heterojunction interface 111 between the electron supply layer 11 and the electron transit layer 13, a two-dimensional electron gas (2DEG) is induced to form a two-dimensional electron gas layer 12.

  A first dielectric film 17 made of a nitride film is formed on the nitride semiconductor layer 16. The first dielectric film 17 and the nitride semiconductor layer 16 penetrate the first dielectric film 17, the electron supply layer 11 and the two-dimensional electron gas layer 12 of the nitride semiconductor layer 16, and above the electron transit layer 13. A recess 30 is formed in part. The recess 30 is formed by etching the electron supply layer 11 and the electron transit layer 13. The recess 30 has a trapezoidal shape in which the bottom width is narrower than the width of the opening. The depth of the recess 30 may be greater than or equal to the depth penetrating the two-dimensional electron gas layer 12, and is, for example, a depth of 50 to 100 nm from the heterojunction interface 111.

  The ohmic electrode 18 is formed so as to cover the bottom of the recessed portion 30 and substantially fill the space in the recessed portion 30. The ohmic electrode 18 is also formed on the first dielectric film 17 in the vicinity of the recess 30. The ohmic electrode 18 is made of a metal layer in which titanium (Ti) and aluminum (Al) are laminated. The ohmic electrode 18 is in contact with the two-dimensional electron gas layer 12 and the electron transit layer 13 at the bottom of the recess 30. The contact width a of the portion where the ohmic electrode 18 is in contact with the electron transit layer 13 is 2.0 μm.

  FIG. 2 shows the relationship between the contact width a and the contact resistance Rc between the ohmic electrode 18 and the electron transit layer 13. Here, the vertical axis of FIG. 2 represents the contact resistance Rc, and the horizontal axis of FIG. 2 represents the contact width a.

As shown in FIG. 2, the contact resistance Rc decreases as the contact width a increases. In particular, the contact resistance Rc rapidly decreases until the contact width a reaches about 2.0 μm. Therefore, it is desirable that the contact width a be 2.0 μm or more. In this case, the contact resistance Rc can be greatly reduced as compared to when the contact width a is less than 2.0 μm. In addition, preferably, the contact resistance Rc can be further reduced by setting the contact width a to 2.5 μm or more, and more preferably setting the contact width a to 3.0 μm or more.
On the other hand, the contact resistance Rc is substantially constant at 1.5Ω when the contact width a is larger than 4.0 μm. For this reason, it is desirable that the contact width a be 4.0 μm or less. That is, if the contact width a is larger than 4.0 μm, the contact resistance Rc cannot be reduced even if the contact width a is increased, and only the chip size is increased.

  According to the GaN-based HFET of the first embodiment, the contact width a in which the ohmic electrode 18 is in contact with the electron transit layer 13 is 2.0 μm, so that the ohmic electrode 18 is in contact with the two-dimensional electron gas layer 12. Compared with the case where the contact resistance is reduced only by increasing the area, the contact resistance can be reduced and the on-resistance can be reduced while minimizing the increase in chip size.

(Second Embodiment)
FIG. 3 is a schematic cross-sectional view of a GaN-based HFET according to the second embodiment of the present invention. The difference from the first embodiment will be described. In the second embodiment, the first recess 301 and the second recess 302, the first ohmic electrode 181 and the second ohmic electrode 182, and the gate electrode 19 It has. In the second embodiment, the same reference numerals as those in the first embodiment are the same as those in the first embodiment, and the description thereof is omitted.

  As shown in FIG. 3, the first recesses penetrate the first dielectric film 17, the electron supply layer 11, and the two-dimensional electron gas layer 12 and are spaced apart from each other on the upper part of the electron transit layer 13. A portion 301 and a second recess portion 302 are formed. The first recess portion 301 and the second recess portion 302 are formed by etching the electron supply layer 11 and the electron transit layer 13. Each of the first recess portion 301 and the second recess portion 302 has a trapezoidal shape in which the bottom width is narrower than the width of the opening. Each depth of the 1st recess part 301 and the 2nd recess part 302 should just be more than the depth which penetrates the two-dimensional electron gas layer 12, for example, is the depth of 50-100 nm from the heterojunction interface 111.

  The first ohmic electrode 181 is formed so as to cover the bottom of the first recess portion 301 and substantially fill the space in the first recess portion 301. The first ohmic electrode 181 is also formed on the first dielectric film 17 in the vicinity of the first recess 301.

  A second ohmic electrode 182 is formed so as to cover the bottom of the second recess 302 and substantially fill the space in the second recess 302. The second ohmic electrode 182 is also formed on the first dielectric film 17 in the vicinity of the second recess portion 302.

  The first ohmic electrode 181 and the second ohmic electrode 182 are made of a metal layer in which titanium (Ti) and aluminum (Al) are laminated.

  A gate electrode 19 is formed on the electron supply layer 11 in the opening formed in the first dielectric film 17 between the first ohmic electrode 181 and the second ohmic electrode 182. The gate electrode 19 is made of a metal layer in which nickel (Ni) and gold (Au) are stacked.

  The first ohmic electrode 181 is in contact with the two-dimensional electron gas layer 12 and the electron transit layer 13 at the bottom of the first recess 301. The contact width a of the portion where the first ohmic electrode 181 is in contact with the electron transit layer 13 is 2.0 μm. The distance Lgs between the first ohmic electrode 181 and the gate electrode 19 is 3 μm.

  The second ohmic electrode 182 is in contact with the two-dimensional electron gas layer 12 and the electron transit layer 13 at the bottom of the second recess 302. The contact width a of the part where the second ohmic electrode 182 contacts the electron transit layer 13 is 2.0 μm. The distance Lgd between the second ohmic electrode 182 and the gate electrode 19 is 20 μm.

  FIG. 4 shows the relationship between the ON resistance Ron · A per unit area and the contact width a in the HFET when the distance Lgs is constant and the distance Lgd is 10 μm or 20 μm. Here, the vertical axis of FIG. 4 represents the on-resistance Ron · A per unit area. The horizontal axis of FIG. 4 represents the contact width a between the ohmic electrode and the electron transit layer.

  As shown in FIG. 4, when the contact width a is about 1.5 μm, the on-resistance Ron · A becomes the minimum value when the distance Lgd is 10 μm or 20 μm. Further, when the contact width a is 0.5 μm or more and 4.0 μm or less, the increase of the on-resistance Ron · A per unit area is made + 5% or less of the above minimum value, and the on-resistance Ron · A per unit area is reduced. Can be reduced. Further, the on-resistance Ron · A per unit area can be reduced to some extent by setting the contact width a to preferably 1.0 μm or more and 3.0 μm or less.

(Third embodiment)
FIG. 5 is a schematic cross-sectional view showing the vicinity of the ohmic electrode 18 in the GaN-based HFET of the third embodiment of the present invention. The difference from the first embodiment will be described. In the third embodiment, an N-type dopant is doped in the interface between the electron transit layer 13 and the recess 30, and an N-type doping region 21 is formed in the interface. Is formed. In the third embodiment, the same reference numerals as those in the first embodiment are the same as those in the first embodiment, and the description thereof is omitted.

  According to the GaN-based HFET of this embodiment, the N-type doping region 21 is formed at the interface with the recess 30 of the electron transit layer 13, so that the ohmic electrode 18 and the electron transit layer 13 are formed by the N-type doping region 21. Can be easily realized.

(Fourth embodiment)
FIG. 6 is a schematic cross-sectional view of a GaN-based HFET according to the fourth embodiment of the present invention. The difference from the second embodiment will be described. In the fourth embodiment, the interface between the first recess portion 301 and the second recess portion 302 of the electron transit layer 13 is doped with an N-type dopant, and these interfaces are arranged. Are formed with N-type doping regions 211 and 212, respectively. In addition, in this 4th Embodiment, since the code | symbol same as the said 2nd Embodiment is the same structure as the said 2nd Embodiment, the description is abbreviate | omitted.

  According to the GaN-based HFET of this embodiment, the N-type doping regions 211 and 212 are formed at the interface between the first recess portion 301 and the second recess portion 302 of the electron transit layer 13. 212, the ohmic contact between the first ohmic electrode 181 and the second ohmic electrode 182 and the electron transit layer 13 can be easily realized.

  In the first to fourth embodiments, the ohmic electrodes 18, 181, and 182 almost fill the space in the recesses 30, 301, and 302, but not limited to this, at least a part of the ohmic electrodes is formed. It is sufficient that the ohmic electrode is in contact with the electron transit layer by being embedded in the recess portion.

  Moreover, in the said 1st-4th embodiment, although the recess part was trapezoid shape where the width | variety of a bottom part is narrower than the width | variety of an opening part, it is not restricted to this, Even if it is a rectangular shape or a fan shape Good.

  In the first and third embodiments, the contact width a of the portion where the ohmic electrode 18 is in contact with the electron transit layer 13 is 2.0 μm. However, the present invention is not limited to this, and it may be larger than 2.0 μm. For example, it may be 2.5 μm or 3.0 μm.

  Moreover, in the said 1st, 3rd embodiment, although the contact width a of the part which the ohmic electrode 18 contacts the electron transit layer 13 was 2.0 micrometers, it is not restricted to this, 2.0 micrometers or more and 4. It may be 0 μm or less.

  In the second and fourth embodiments, the contact width a of the portion where the first and second ohmic electrodes 181 and 182 are in contact with the electron transit layer 13 is 2.0 μm. It may be 0.5 μm or more and 4.0 μm or less. Further, the contact width of the portion where the first ohmic electrode 181 contacts the electron transit layer 13 and the contact width of the portion where the second ohmic electrode 182 contacts the electron transit layer 13 may be different. .

  The nitride semiconductor device of the present invention is not limited to the HFETs of the first to fourth embodiments, but may be HFETs having other configurations.

  Although specific embodiments of the present invention have been described, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

  The present invention and the embodiments are summarized as follows.

The nitride semiconductor device of the present invention is
A substrate 15;
An electron transit layer 13 made of a nitride semiconductor formed on the substrate 15;
An electron supply layer 11 formed on the electron transit layer 13 and made of a nitride semiconductor and forming the heterojunction interface 111 with the electron transit layer 13;
Recess portions 30, 301, 302 that penetrate through the electron supply layer 11 and the two-dimensional electron gas layer 12 formed in the vicinity of the heterojunction interface 111 and are formed in part of the upper side of the electron transit layer 13. When,
Ohmic electrodes 18, 181 and 182 formed so as to cover at least a part of the recess portions 30, 301 and 302,
A recess 30 is formed in a part of the upper side of the electron transit layer 13 through the electron supply layer 11 and the two-dimensional electron gas layer 12 formed in the vicinity of the heterojunction interface 111. Embedded with at least a part of the ohmic electrode 18;
The width a of the portion where the ohmic electrodes 18, 181 and 182 are in contact with the electron transit layer 13 is 2.0 μm or more.

  According to the nitride semiconductor device of the present invention, the width a of the portion where the ohmic electrodes 18, 181 and 182 are in contact with the electron transit layer 13 is 2.0 μm or more, so that the ohmic electrodes 18, 181 and 182 The contact resistance Rc with the electron transit layer 13 can be reduced. For this reason, the contact resistance is reduced while minimizing the increase in chip size as compared with the case where the contact resistance is reduced only by increasing the area where the ohmic electrodes 18, 181 and 182 are in contact with the two-dimensional electron gas layer 12. On-resistance can be reduced.

In the nitride semiconductor device of one embodiment,
The width a of the portion where the ohmic electrode 18 is in contact with the electron transit layer 13 is 4.0 μm or less.
According to the embodiment, since the width a of the portion where the ohmic electrode 18 is in contact with the electron transit layer 13 is 4.0 μm or less, the contact resistance Rc can be reduced even if the contact width a is increased. It is not possible to prevent an increase in chip size.

The nitride semiconductor device of the present invention is
A substrate 15;
An electron transit layer 13 made of a nitride semiconductor formed on the substrate 15;
An electron supply layer 11 formed on the electron transit layer 13 and made of a nitride semiconductor and forming the heterojunction interface 111 with the electron transit layer 13;
First through the electron supply layer 11 and the two-dimensional electron gas layer 12 formed in the vicinity of the heterojunction interface 111 and at a distance from each other in the upper part of the electron transit layer 13. A recess 30 having a recess 301 and a second recess 302;
A first ohmic electrode 181 formed to cover at least a part of the first recess 301;
A second ohmic electrode 182 formed to cover at least a part of the second recess 302;
A gate electrode 19 formed between the first ohmic electrode 181 and the second ohmic electrode 182;
The widths of the portions where the first ohmic electrode 181 and the second ohmic electrode 182 are in contact with the electron transit layer 13 are 0.5 μm or more and 4.0 μm or less, respectively.

  According to the nitride semiconductor device of the present invention, the widths of the portions where the first ohmic electrode 181 and the second ohmic electrode 182 are in contact with the electron transit layer 13 are 0.5 μm or more and 4.0 μm or less, respectively. Therefore, the on-resistance RonA per unit area can be reduced. Therefore, the contact resistance can be reduced and the on-resistance can be reduced while minimizing the increase in chip size.

In the nitride semiconductor device of one embodiment,
An N-type dopant is doped at the interface of the electron transit layer 13 with the recesses 30, 301, and 302.

  According to the embodiment, the interface of the electron transit layer 13 with the recesses 30, 301, 302 is doped with N-type dopants, and N-type doping regions 21, 211, 212 are formed at these interfaces. Therefore, ohmic contact between the ohmic electrodes 18, 181, 182 and the electron transit layer 13 can be easily realized by the N-type doping regions 21, 211, 212.

DESCRIPTION OF SYMBOLS 11 Electron supply layer 12 Two-dimensional electron gas layer 13 Electron travel layer 15 Substrate 18 Ohmic electrode 19 Gate electrode 21 N-type doping region 30 Recessed portion 111 Heterojunction interface 181 First ohmic electrode 182 Second ohmic electrode 301 First recessed portion 302 Second recess part a Contact width

Claims (4)

A substrate,
An electron transit layer made of a nitride semiconductor formed on the substrate;
An electron supply layer formed on the electron transit layer, made of a nitride semiconductor, and forming a heterojunction interface with the electron transit layer;
A recess formed in a part of the upper side of the electron transit layer while penetrating the electron supply layer and the two-dimensional electron gas layer formed in the vicinity of the heterojunction interface;
An ohmic electrode formed so as to cover at least a part of the recess,
A width of a portion where the ohmic electrode is in contact with the electron transit layer is 2.0 μm or more. The nitride semiconductor device according to claim 1,
A width of a portion where the ohmic electrode is in contact with the electron transit layer is 4.0 μm or less. A substrate,
An electron transit layer made of a nitride semiconductor formed on the substrate;
An electron supply layer formed on the electron transit layer, made of a nitride semiconductor, and forming a heterojunction interface with the electron transit layer;
A first recess portion and a first recess portion that penetrate through the electron supply layer and a two-dimensional electron gas layer formed in the vicinity of the heterojunction interface and are spaced apart from each other on a part of the upper side of the electron transit layer. A recess portion having two recess portions;
A first ohmic electrode formed to cover at least a part of the first recess,
A second ohmic electrode formed to cover at least a part of the second recess portion;
A gate electrode formed between the first ohmic electrode and the second ohmic electrode;
The width of the part where the first ohmic electrode and the second ohmic electrode are in contact with the electron transit layer is 0.5 μm or more and 4.0 μm or less, respectively. In the nitride semiconductor device according to any one of claims 1 to 3,
A nitride semiconductor device, wherein an interface of the electron transit layer with the recess is doped with an N-type dopant.

Images