JP2013153319A - Solid-state imaging device, method of driving solid-state imaging device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a white floating phenomenon due to hot carriers while maintaining the linearity and the gain characteristics of an output signal or without increase in the usage number of transistors and increase in circuit size and circuit area.SOLUTION: A solid-state imaging device includes: a photoelectric conversion section for generating signal charges according to the amount of received light; a transfer section for transferring the signal charges generated by the photoelectric conversion section; a storage section for storing the signal charges transferred by the transfer section from the photoelectric conversion section; a reset section to which a reference voltage is inputted; a switch section for switching connection between the storage section and the reset section; a source follower circuit connected to the storage section; an output circuit outputting a voltage signal according to the signal charges stored in the storage section; and a reference-voltage control section for changing the reference voltage according to the operating state of the solid-state imaging device.

Description

  The present technology relates to a solid-state imaging device including a storage unit for storing signal charges generated and transferred by photoelectric conversion, a method for driving the solid-state imaging device, and an electronic apparatus having the solid-state imaging device.

  In a CCD solid-state imaging device using a charge coupled device (CCD), a plurality of photodiodes (PD) are arranged in a two-dimensional matrix, and are based on the optical signal of a subject incident on the photodiodes of the plurality of light receiving sensor portions. Signal charge is generated and stored. The accumulated signal charges are transferred in the vertical direction by a CCD structure vertical transfer register arranged for each column of photodiodes, and transferred in the horizontal direction by a CCD structure horizontal transfer register. The signal charge transferred in the horizontal direction is converted into a voltage by the output unit and output.

  The output unit is usually composed of a so-called floating diffusion type amplifier (FD type amplifier), and includes a floating diffusion (FD) connected to the final stage of the horizontal transfer register and a source follower circuit (output circuit unit). Prepare. The source follower circuit is configured by connecting a plurality of source follower circuits in multiple stages in order to amplify and output a minute signal. As a result, the signal charge of each pixel transferred to the horizontal transfer register is converted and output to a signal voltage corresponding to the signal charge.

  Here, in recent CCD solid-state imaging devices, the current drive capability is improved by reducing the gate length of the drive MOS transistor of the source follower circuit, and the transistor size is reduced. Thereby, the performance (for example, conversion efficiency and frequency characteristics) of the source follower circuit is improved, which contributes to high performance of the camera. However, if the gate length of the driving MOS transistor is reduced, there is a demerit that the potential between the source and the drain is increased and hot carriers are easily generated.

  Hot carriers are secondary electrons and photons (electrons / holes) emitted from a source MOS transistor driven by a source follower circuit in which electrons flowing from the source to the drain are accelerated by a high electric field near the drain and collide with the silicon crystal lattice. Point to). When hot carriers are generated, hot carrier emission occurs. Moreover, most of the holes out of the electron-hole pairs flow toward the substrate and become a substrate current.

  It has been confirmed that hot carrier light emission is emitted from the drive MOS transistor portion of the source follower circuit by observation with an emission microscope. In particular, light emission from the driving MOS transistor at the final stage is relatively remarkable. This is because in the source follower circuit in which the n-channel MOS transistor is a drive MOS transistor, the difference between the source voltage and the drain voltage of the final-stage drive MOS transistor is the largest.

  It has been confirmed that when hot carriers are generated, light emitted by recombination of electron-hole pairs generated by the hot carrier phenomenon or hot carrier emission enters the pixel region and is detected as noise. Alternatively, it is conceivable that among the electron / hole pairs generated by the hot carrier phenomenon, the electrons diffuse and enter the photoelectric conversion portion in the pixel region, resulting in noise. The influence of these noises is particularly noticeable when the source follower circuit is arranged near the pixel region.

  Specifically, in a CCD camera, due to the hot carrier phenomenon in the source follower circuit, in the long exposure mode (exposure time of about 1 second to several minutes) such as shooting in the dark, the source follower circuit is the center. It has been confirmed that the brightness of the image increases in a circular shape (the image appears to shine). As the exposure time increases, the brightness and range of the high brightness area tend to increase. This high luminance region degrades the image as image noise. Of course, when the hot carrier characteristics are poor, the image is similarly deteriorated even in the normal exposure mode with a short exposure time.

  In Patent Document 1, a long exposure mode period is used to suppress a phenomenon called a hot spot in which unnecessary charges are accumulated in a circular shape around a hot carrier in a long exposure mode or a location where light emission occurs. In particular, a driving method and a circuit configuration for reducing a current flowing in a transistor where a hot carrier is generated have been proposed.

JP 2008-35193 A

  In the technique of Patent Document 1 described above, since a technique of controlling the substrate bias voltage is used to suppress hot spots, it is necessary to add a large number of circuit elements in order to control the substrate bias voltage. The number of devices used, the circuit scale, and the circuit area were to be increased.

  This technology has been devised in view of the above problems, and it is caused by hot carriers while maintaining the linearity and gain characteristics of the output signal and without increasing the number of transistors used, circuit scale, or circuit area. An object of the present invention is to provide a solid-state imaging device capable of suppressing white floating, a driving method of the solid-state imaging device, and an electronic apparatus.

  One aspect of the solid-state imaging device according to the present technology includes a photoelectric conversion unit for generating a signal charge corresponding to the amount of received light, a transfer unit for transferring the signal charge generated by the photoelectric conversion unit, An accumulation unit for accumulating the signal charges transferred from the photoelectric conversion unit by the transfer unit; a reset unit to which a reference voltage is input; a switch unit for switching connection between the accumulation unit and the reset unit; An output circuit configured to include a source follower circuit connected to the storage unit, outputting a voltage signal corresponding to the signal charge stored in the storage unit, and the reference voltage according to an operating state of the solid-state imaging device; A reference voltage control unit for changing.

  According to this technology, whilst maintaining the linearity and gain characteristics of the output signal, it is possible to suppress whitening caused by hot carriers without increasing the number of transistors used, circuit scale, or circuit area. become.

It is a block diagram which shows an example of an imaging device. It is a block diagram which shows an example of a solid-state image sensor. It is typical sectional drawing for demonstrating a charge voltage conversion part. It is a figure explaining the potential in a horizontal transfer part and a charge voltage conversion part. It is a timing chart in a charge voltage conversion part. It is a timing chart concerning output operation. It is a block diagram explaining a substrate voltage generation circuit. It is a block diagram explaining a drain voltage generation circuit.

Hereinafter, the present technology will be described in the following order.
(1) Aspects of the present technology:
(2) Configuration of imaging device:
(3) Configuration of solid-state image sensor:
(4) Configuration of the charge-voltage converter:
(5) Summary:

(1) Aspects of the present technology:
One aspect of the solid-state imaging device according to the present technology includes a photoelectric conversion unit for generating a signal charge corresponding to the amount of received light, a transfer unit for transferring the signal charge generated by the photoelectric conversion unit, An accumulation unit for accumulating the signal charges transferred from the photoelectric conversion unit by the transfer unit; a reset unit to which a reference voltage is input; a switch unit for switching connection between the accumulation unit and the reset unit; An output circuit that is connected to the storage unit and includes a source follower circuit connected to the storage unit, and that outputs a voltage signal corresponding to the signal charge stored in the storage unit; And a reference voltage control unit for changing the reference voltage according to the operation state.

  In this aspect, when the photoelectric conversion unit generates a signal charge corresponding to the amount of received light, the transfer unit transfers the signal charge generated by the photoelectric conversion unit to the storage unit. As a result, signal charges corresponding to the amount of light received by the photoelectric conversion unit are stored in the storage unit.

  Further, before transferring a new signal charge from the photoelectric conversion unit to the storage unit, the switch unit connects the reset unit and the storage unit at an appropriate timing. As a result, the storage unit is reset to the reference voltage input to the reset unit. Therefore, when the transfer unit sequentially generates signal charges for the number of unit transfers, the signal charges for the number of unit transfers are stored in the storage unit. The number of unit transfers is an integer of 1 or more, for example once, twice, etc.

  Here, in the solid-state imaging device, hot carriers may be generated in the output circuit. The hot carrier in the output circuit depends on the reference voltage of the storage unit, that is, the reference voltage input to the reset unit, because the output circuit has a source follower circuit configuration.

  The hot carrier generated in the output circuit changes in accordance with various operation states related to exposure such as exposure time, aperture ratio, shutter speed, ISO sensitivity, and the like. These operation states are often managed by setting values inside the apparatus, and in actual products, they are often set as so-called operation modes.

  Therefore, in the solid-state imaging device according to this aspect, the reference voltage can be changed by the reference voltage control unit according to the operating state of the solid-state imaging device. In particular, the reference voltage is controlled so as to suppress hot carriers in an operating state in which the amount of hot carriers generated may increase or in an operating state in which hot carriers at a level that adversely affects image quality may occur. It is preferable to do.

  Further, the larger the potential difference between the source and drain of the driving MOS transistor in the source follower circuit is, the more hot carriers affect the signal charge, so that the potential difference between the source and drain of the driving MOS transistor in the source follower circuit at the subsequent stage becomes smaller. The reference voltage is changed. Thereby, the bad influence with respect to the said signal charge by a hot carrier is suppressed.

  Next, in another selective aspect of the solid-state imaging device according to the present technology, the reference voltage control unit exposes the reference voltage in at least a part of an exposure period provided for capturing a still image. The configuration is such that the voltage is changed to a higher voltage than in other periods.

  In the solid-state imaging device according to this aspect, in the exposure period provided immediately before the transfer unit transfers the signal charge to the storage unit, the reference voltage is changed to a higher voltage than the period other than the exposure period. Yes.

  The exposure period is a period in which the output circuit does not output the voltage signal. Therefore, even if the reference voltage is changed, the voltage signal is not affected. Therefore, the influence of hot carriers can be suppressed without affecting the voltage signal output from the output circuit.

  Next, in another selective aspect of the solid-state imaging device according to the present technology, the reference voltage control unit is configured to use the reference voltage in the exposure period provided for capturing a still image. In this configuration, the signal voltage corresponding to the signal charge stored in the storage unit is changed to a voltage that is outside the performance guarantee range of the input buffer circuit.

  Normally, if the reference voltage for resetting the storage unit is changed outside the guaranteed performance range of the buffer circuit, the signal voltage output from the storage unit is saturated in the buffer circuit. However, such an adverse effect does not occur during the exposure period.

  On the other hand, as described above, the effect of suppressing the inflow of hot carriers increases as the potential difference between the source and drain of the driving MOS transistor in the source follower circuit at the subsequent stage is smaller. This source-drain potential difference becomes smaller as the reference voltage is higher. Therefore, in this aspect, the reference voltage variation range is not limited to the output buffer circuit performance guarantee range, but the reference voltage can be varied outside the output buffer circuit performance guarantee range, and the reset unit holds the reference voltage. The reference voltage to be changed is changed as much as possible in the direction in which the effect of suppressing the generation of hot carriers increases. Thereby, the effect which suppresses the bad influence by a hot carrier can be heightened.

  Next, in another selective aspect of the solid-state imaging device according to the present technology, the reference voltage control unit automatically changes the reference voltage of the storage unit using an internal signal of the solid-state imaging device. This is a configuration to be made.

  In this aspect, since the reference voltage is changed using an internal signal, it is not necessary to input a special signal separately from the outside, it is not necessary to increase the circuit scale and circuit area, and design changes are minimized. That's it. Further, since an internal signal is used, it is easy to automatically change the reference voltage without requiring external control or the like.

  In another selective aspect of the solid-state imaging device according to the present technology, the storage unit is a floating diffusion unit, the reset unit is a drain unit to which the reference voltage is input, and the switch A gate unit that switches a connection between the storage unit and the drain unit, and the floating diffusion unit is reset to the reference voltage by being connected to the drain unit under the control of the gate unit The configuration is as follows.

  In the outline of the present technology described above, the case where the reference voltage is changed for the purpose of suppressing hot carriers is described as an example. However, the reference voltage is not limited to this purpose, and may be used for various purposes. The present disclosure also includes a technique for changing the value according to the operation state.

  Further, the above-described solid-state imaging device includes various modes such as being implemented in a state of being incorporated in another device or being implemented together with another method. In addition, the present technology provides an electronic device or an imaging system having the solid-state imaging device, a driving method of the solid-state imaging device, a program that causes a computer to realize functions corresponding to the configuration of the above-described device, and a computer-readable computer that records the program It can also be realized as a recording medium.

(2) Configuration of imaging device:
FIG. 1 is a configuration diagram illustrating an example of an imaging apparatus including a solid-state imaging device. The imaging apparatus shown in the figure is an example of an electronic device.

  Note that in this specification, the imaging device is a solid-state imaging device in an image capturing unit (photoelectric conversion unit) such as an imaging device such as a digital still camera or a digital video camera, or a mobile terminal device such as a mobile phone having an imaging function. Refers to all electronic devices that use. Of course, an electronic apparatus using a solid-state imaging device for an image capturing unit also includes a copying machine using a solid-state imaging device for an image reading unit. In addition, the imaging device may be a module including a solid-state imaging device to be mounted on the electronic device described above.

  In FIG. 1, an imaging device 100 includes an optical system 110 including a lens group, a solid-state imaging device 120, a DSP 130 (Digital Signal Processor), a frame memory 140, a display device 150, a recording device 160, an operation system 170, a power supply system 180, and a control. Part 190 is provided.

  The DSP 130, the frame memory 140, the display device 150, the recording device 160, the operation system 170, the power supply system 180, and the control unit 190 are connected to each other via a communication bus so that data and signals can be transmitted and received.

  The optical system 110 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 120. The solid-state imaging device 120 converts the amount of incident light imaged on the imaging surface by the optical system 110 into an electrical signal in units of pixels, and outputs it as a pixel signal.

  The display device 150 is a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image, a still image, and other information captured by the solid-state image sensor 120. The recording device 160 records a moving image or a still image captured by the solid-state imaging device 120 on a recording medium such as a DVD (Digital Versatile Disk) or a semiconductor memory.

  The operation system 170 receives various operations from the user, and transmits an operation command corresponding to the user's operation to each unit 130, 140, 150, 160, 180, 190 via the communication bus. The power supply system 180 generates various power sources that serve as driving power sources for the respective units 110, 130, 140, 150, 160, 170, and 190, and supplies them appropriately to these supply targets.

  The control unit 190 includes a CPU that performs arithmetic processing, a ROM that stores a control program for the imaging apparatus 100, a RAM that functions as a work area for the CPU, and the like, and is stored in the ROM while using the RAM as a work area. The CPU executes each control program 110, 120, 130, 140, 150, 160, 170, 180 via the communication bus. Further, for example, the control unit 190 performs control to supply various timing signals from a timing generator (not shown) to each unit.

(3) Configuration of solid-state image sensor:
In the imaging apparatus described above, a solid-state imaging device such as a CCD image sensor according to each embodiment described later can be used as the solid-state imaging device 120. FIG. 2 is a block diagram illustrating a configuration of the solid-state imaging device according to the present embodiment. In the figure, an interline transfer (IT) type solid-state imaging device 10 is illustrated, but the present invention is not limited to this type.

  A solid-state imaging device 10 shown in FIG. 1 includes a plurality of optical sensor units 12, a plurality of readout gate units 13, a plurality of vertical transfer units 14, a horizontal transfer unit 15, and a charge on a semiconductor substrate (chip) 11. A voltage converter 16 is formed. In the following description, the case where the semiconductor substrate is N-type will be described as an example.

  The plurality of optical sensor units 12 constitute so-called pixels, and are two-dimensionally arranged in a matrix on the semiconductor substrate 11. The optical sensor unit 12 includes, for example, a PN junction photodiode, and generates and accumulates signal charges corresponding to the amount of received light by photoelectrically converting the received light over an exposure period. The optical sensor unit 12 constitutes a photoelectric conversion unit in the present embodiment.

  The read gate unit 13 is provided for each pixel, and connects between each pixel and the vertical transfer unit 14 corresponding to the pixel. When the readout gate unit 13 is controlled by a predetermined control signal, the signal charges accumulated in the photosensor unit 12 are transferred (read out) to the vertical transfer unit 14 at an appropriate timing.

  The vertical transfer unit 14 is provided for each pixel column with respect to the matrix-like pixel arrangement. The vertical transfer unit 14 is configured by a CCD (Charge Coupled Device) in which a plurality of electrodes are provided on an oxide film on the surface of a semiconductor substrate. As a result, the vertical transfer unit 14 can apply different voltages adjacent to each other of the plurality of electrodes to form a potential barrier between the electrodes, and hold charges in the electrodes. From such a charge transfer mode, the vertical transfer unit 14 may be called a vertical transfer register.

  The vertical transfer unit 14 sequentially verticalizes signal charges read to the optical sensor unit 12 through the read gate unit 13 by a portion corresponding to one scanning line (one row) in a part of the horizontal blanking period. Forward in the direction. The vertical direction refers to the column direction of a plurality of pixels arranged in a matrix (corresponding to the vertical direction in FIG. 2).

  The horizontal transfer unit 15 is provided at one end of the vertical transfer unit 14 (that is, the end on the transfer destination side). The horizontal transfer unit 15 is configured by a CCD in the same manner as the vertical transfer unit 14 described above. For this reason, the horizontal transfer unit 15 is sometimes called a horizontal transfer register.

  In the horizontal transfer unit 15, signal charges corresponding to one row are sequentially shifted (transferred) from the plurality of vertical transfer units 14. The horizontal transfer unit 15 sequentially transfers the signal charges for one row shifted from the plurality of vertical transfer units 14 in the horizontal direction in the horizontal scanning period after the horizontal blanking period. Note that the horizontal direction refers to the row direction (corresponding to the horizontal direction in FIG. 2) of a plurality of pixels arranged in a matrix.

  In the present embodiment, the readout gate unit 13, the vertical transfer unit 14, and the horizontal transfer unit 15 described above constitute a transfer unit for transferring the signal charge generated by the photoelectric conversion unit with the CCD.

  At the end of the horizontal transfer unit 15 on the transfer destination side, a charge-voltage conversion unit 16 that converts a signal charge transferred by the horizontal transfer unit 15 into a voltage signal is provided. For example, a charge / voltage converter 16 having a floating diffusion amplifier configuration is used.

  Specifically, the charge-voltage conversion unit 16 shown in FIG. 2 includes a floating diffusion (FD) unit 16a that constitutes an accumulation unit, a reset drain (RD) unit 16b that constitutes a charge ejection unit, an accumulation unit, and a charge ejection unit. A reset gate (RG) section 16c for controlling connection of the sections, an output circuit 16d, a bias generation circuit 16e, and a drain voltage generation circuit 16f.

  A reset drain voltage Vdr having a predetermined voltage value is applied to the reset drain unit 16b. The potential of the reset drain section 16b to which the reset drain voltage Vdr is applied is a predetermined voltage applied to the electrode HOG at the final stage of the vertical transfer section 14, which will be described later, when charge transfer is not performed from the horizontal transfer section 15 to the vertical transfer section 14. This is deeper than the potential of the final transfer stage of the horizontal transfer unit 15 (when no voltage is applied).

  The reset gate portion 16c has a MOS transistor configuration, and a DC bias voltage generated by the bias generation circuit 16e is applied to the gate electrode. Further, a reset clock (reset pulse) φRG is applied to the gate electrode from a reset clock generation circuit 21 provided outside the semiconductor substrate 11 via a capacitor 22.

  The reset clock φRG is superimposed on the bias voltage generated by the bias generation circuit 16e and applied to the reset gate unit 16c. As a result, the potential of the floating diffusion portion 16a is reset to the reset drain voltage Vdr at the cycle of the reset clock φRG.

  The signal charge transferred from the horizontal transfer unit 15 to the charge voltage conversion unit 16 is accumulated in the floating diffusion unit 16a. Thereby, the floating diffusion part 16a becomes a voltage according to the accumulated signal charge. The floating diffusion section 16a is connected to an output circuit (output section) 16d having a function as a buffer, and a voltage signal corresponding to the voltage of the floating diffusion section 16a is input to the output circuit 16d.

  The output circuit 16d is one of the peripheral circuits mounted on the same semiconductor substrate 11 as the optical sensor unit 12, the vertical transfer unit 14, the horizontal transfer unit 15, the charge voltage conversion unit 16, and the bias generation circuit 16e. The source follower circuit is used. In this way, the voltage signal output from the charge voltage conversion unit 16 is output to the outside of the semiconductor substrate 11 as the imaging signal Vout via the output circuit 16d.

(4) Configuration of the charge-voltage converter:
Next, an example of the configuration of the charge-voltage conversion unit 16 will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view for explaining the charge-voltage converter 16. As shown in the figure, in the horizontal transfer portion 15, an N-type channel region 11c is formed on the surface side of an N-type semiconductor substrate 11a via a P-type well 11b.

  On the surface of the N-type channel region 11c, N-type transfer (TR) regions 11d are formed at a constant pitch along the horizontal direction in the figure, and the channel region 11c between the transfer regions 11d and 11d is stored ( ST) Region 11e.

  An electrode H1 made of polysilicon of the first layer is formed above the storage region 11e via an insulating film (not shown), and an electrode H2 made of polysilicon of the second layer is formed above the transfer region 11d. Is formed through an insulating film (not shown).

  Adjacent electrodes H1 and H2 formed in this manner form a pair, and two-phase transfer clocks Hφ1 and Hφ2 are alternately applied to the electrode pair (H1 and H2) in the arrangement direction to thereby form a two-phase. The horizontal transfer of driving is realized.

  Furthermore, an electrode HOG made of polysilicon of the second layer is formed at the final stage of the horizontal transfer unit 15. The electrode HOG is electrically connected to a ground potential that is a solid-state image sensor reference potential. The electrode HOG and the channel region below the electrode HOG constitute an output gate portion 11f.

  Further, an N + type floating diffusion (FD) portion 16a is formed adjacent to the output gate portion 11f, and an N + type reset drain (RD) portion is sandwiched between the channel region 11c and the floating diffusion (FD) portion 16a. 16a is formed. Further, a reset gate (RG) portion 16c is formed above the channel region 11c via an insulating film (not shown).

  The reset gate unit 16c is connected to the reset clock generation circuit 21 shown in FIG. 2, and is configured such that the reset clock RGφ generated by the reset clock generation circuit 21 can be applied to the reset gate.

  The floating diffusion portion 16a is connected to a source follower circuit in the output circuit 16d, and a constant drain voltage Vdr is applied to the reset drain portion 16b. The floating diffusion portion 16a is controlled to be connected to the reset drain portion 16b by the control of the reset gate portion 16c by the reset gate pulse φRG.

  The floating diffusion portion 16a is reset to the drain voltage Vdr when connected to the reset drain portion 16b, and holds the signal charge transferred from the horizontal transfer portion 15 when not connected to the reset drain portion 16b.

  The signal charge output from the output gate section 11f is detected by the charge-voltage conversion section 16 having such a floating diffusion amplifier configuration.

  Next, the signal charge transfer operation in the charge-voltage conversion unit 16 configured as described above will be described with reference to FIGS. FIG. 4 is a diagram for explaining potentials in the horizontal transfer unit 15 and the charge-voltage conversion unit 16, and FIG. 5 shows a timing chart in the charge-voltage conversion unit 16.

  The signal charges transferred to the horizontal transfer unit 15 are transferred in the output direction by applying a transfer clock to the transfer electrodes (H1, H2, LH) of the horizontal transfer unit 15, respectively. Specifically, the transfer clock Hφ1 is applied to the electrode H1, the transfer clock Hφ2 is applied to the electrode H2, and the transfer clock LHφ is applied to the electrode LH.

  By these transfer clocks Hφ1, Hφ2, and LHφ, the potential of each register constituting the horizontal transfer unit 15 is raised and lowered at an appropriate timing, and the signal charges are transferred in the output direction (from right to left). The signal charge transferred in the horizontal transfer unit 15 is transferred to the floating diffusion 16c.

  The signal charge transferred to the floating diffusion portion 16a is converted into a voltage corresponding to the amount of charge in the output circuit 16d. Thereafter, the reset gate voltage RGφ is applied to the reset gate portion 16c, whereby the signal charge is swept away by the reset drain portion 16b. By performing such a series of operations, an output signal of the solid-state imaging device 10 can be obtained.

  Note that a voltage HOGφ is applied as a fixed voltage to the electrode HOG in the final stage of the horizontal transfer unit 15. Therefore, the potential under the electrode HOG hardly changes. However, the potential below the electrode LH changes up and down by the transfer clock LHφ applied to the electrode LH.

  Here, when the transfer clock LHφ is in a high level (H level) state, as shown in FIG. 4, accumulation is performed below the electrode LH (channel region 11c in FIG. 3) with the potential below the electrode HOG and the potential below the electrode LH. The maximum signal amount (D range) that can be defined is defined.

  On the other hand, when the transfer clock LHφ is in a low level (L level) state, as shown in FIG. 4, a transfer electric field is formed that decreases stepwise from below the electrode LH to below the electrode HOG. Thus, when a transfer electric field is formed from the lower side of the electrode LH to the lower side of the electrode HOG, the signal charge accumulated under the electrode LH is transferred to the floating diffusion portion 16a beyond the potential under the electrode HOG.

  Next, an output operation for converting signal charges into signal voltages will be described with reference to FIG. This figure shows a timing chart relating to the output operation.

  The “moving image period” shown in the figure is a period during which a so-called preview operation is performed by continuously capturing images. The “exposure operation period” is a period during which exposure for capturing a so-called still image is performed in accordance with an imaging instruction given by the user. The “still image readout period” is a period in which signal charges accumulated in each pixel in the “exposure operation period” are sequentially read and converted into signal voltages. Note that the user can issue an imaging instruction by performing a predetermined operation input to the imaging apparatus 100.

  FIG. 6A shows a timing chart of the substrate voltage Vsub during still image shooting. The substrate voltage Vsub is a voltage for adjusting the amount of charge that can be accumulated in each pixel, and specifically, is the substrate voltage of the N-type semiconductor substrate 11a shown in FIG. The substrate voltage Vsub is created based on a control signal input to the control voltage input terminal 18 from the control voltage generation circuit 30 outside the solid-state imaging device shown in FIG. 7, and as shown in FIG. Furthermore, it is adjusted so as to change according to the operating state.

  The substrate voltage Vsub is lower in the still image reading period than in the moving image period. Specifically, for example, when the substrate voltage Vsub in the moving image period is 10 V, the substrate voltage Vsub in the still image reading period is 4 to 5 V. Thereby, in the still image reading period, the amount of charge that can be accumulated in one pixel is adjusted to be larger than that in the moving image period.

  Further, the substrate voltage Vsub is about halfway between the moving image period and the still image reading period in the exposure period. Specifically, the substrate voltage Vsub in the exposure period is set to about 6 to 7 V in correspondence with specific voltage values in the moving image period and the still image reading period described above. Thus, the adjustment of the substrate voltage Vsub at which the substrate voltage Vsub at the time of taking a still image is different between the exposure period and the still image reading period is called two-stage modulation.

  The reason for performing this two-stage modulation is to cope with the charge leakage of the pixel. The charge leakage of a pixel means that while the signal charge accumulated in each of a plurality of pixels constituting one frame is sequentially read out, the signal charge in the accumulated state is output for the first read signal. On the other hand, for the pixels with a slow readout order, the signal charge is lost over time, and even if the pixels receive the same amount of light, the signal of the pixel with the slow readout order has a lower gradation. is there.

  Therefore, the substrate voltage Vsub in the exposure period is slightly higher than the substrate voltage Vsub in the still image readout period so that the total amount of charge that can be accumulated in each pixel is larger in the still image readout period than in the exposure period. Is set. This makes it difficult for signal charges accumulated in each pixel to leak, and the influence of the above-described charge leakage can be reduced as much as possible.

  When the exposure period starts, an electronic shutter operation for discharging the charges accumulated in each pixel is executed. At this time, the charges discharged from each pixel are discharged to the N-type semiconductor substrate 11a, so that the substrate voltage Vsub increases instantaneously. Thereby, each pixel accumulates electric charges according to the amount of light received after the electronic shutter operation.

  FIG. 6B shows a timing chart relating to the operation of the mechanical shutter. The mechanical shutter mechanically covers or opens the surface of the solid-state imaging device by an opening / closing operation, and is driven by a control signal output from the control unit 190. The mechanical shutter is opened during the moving image period and the exposure operation period, and is closed during the still image reading period. As a result, during moving image shooting or exposure for reading a still image, light can be incident on the pixel, while light is incident on the pixel during a still image reading period in which the signal charge of the still image is transferred. It can be surely prevented.

  FIG. 6C shows a timing chart of the control voltage Vctl. The control voltage Vctl is a voltage for controlling the operation of each part of the solid-state imaging device, and the above-described substrate voltage Vsub is also generated using this control voltage Vctl. The control voltage Vctl is input to the control voltage input terminal 18 of the solid-state imaging device, and is adjusted according to the operation state as shown in FIG.

  Similarly to the substrate voltage Vsub described above, the control voltage Vctl is lower in the still image reading period than in the moving image period, and is about the middle between the moving image period and the still image reading period in the exposure period. Yes.

  FIG. 7 is a block diagram illustrating a substrate voltage generation circuit. As shown in the figure, a control voltage generation circuit 30 is provided outside the solid-state imaging device 10, and the control voltage generation circuit 30 generates a control voltage Vctl and a control voltage input terminal of the solid-state imaging device 10. 18 is input.

  The control voltage Vctl input to the control voltage input terminal 18 is input to the substrate voltage generation circuit 17. The control voltage Vctl is also supplied to other components of the solid-state imaging device 10 as necessary, and is used for various controls. For example, the control voltage Vctl is supplied to the charge voltage conversion unit 16 and can be used as a trigger for changing a drain voltage Vdr described later.

  The substrate voltage generation circuit 17 appropriately adjusts the input control voltage Vctl to generate a substrate voltage Vsub and supply it to the semiconductor substrate 11a. The substrate voltage Vsub in the semiconductor substrate 11a is a voltage that defines the charge storage capacity in the optical sensor unit 12 as described above. The higher the substrate voltage Vsub, the smaller the capacity of the optical sensor unit 12 and the lower the substrate voltage Vsub. The capacity of the optical sensor unit 12 increases as the time increases.

  The substrate voltage Vsub is also supplied to other components of the solid-state imaging device 10 as necessary, and is used for various controls. For example, the substrate voltage Vsub is supplied to the charge voltage conversion unit 16 and can be used as a trigger for changing a drain voltage Vdr described later.

  FIG. 6D is a timing chart showing changes in the drain voltage Vdr. As shown in the figure, the drain voltage Vdr in the exposure period is adjusted to be higher than in other periods. That is, in the MOS transistor structure constituted by the floating diffusion portion 16a, the reset gate portion 16c, and the reset drain portion 16b, the drain voltage Vdr applied to the reset drain portion 16b is higher than usual.

  The drain voltage Vdr during the exposure period may be changed using an existing signal inside the solid-state imaging device, or may be changed using a signal input separately from the outside. In the former case, the above-described reference voltage and control voltage Vctl can be used. When the reference voltage is used, it may be used after eliminating the instantaneous voltage increase at the time of reset described above with the capacitor. In the latter case, a mechanical shutter control signal may be used, or a control signal separately generated by the control unit 190 may be used.

  Here, in the MOS transistor structure, the smaller the potential difference between the source and the drain, the less likely hot carriers are generated. Conversely, the greater the potential difference between the source and the drain, the more likely hot carriers are generated. Therefore, by increasing the drain voltage Vdr during the exposure period as described above, hot carriers are suppressed and the image quality is improved.

  The drain voltage Vdr may be increased at least during a part of the exposure period. Of course, increasing the drain voltage Vdr during the entire exposure period has a higher effect of suppressing hot carriers. However, even if the drain voltage Vdr is increased during a part of the exposure period, the effect of suppressing hot carriers is naturally. Because there is.

  Further, since the drain voltage Vdr is a reference voltage of the signal voltage output from the floating diffusion portion 16a, conventionally, the drain voltage Vdr has been adjusted so as to be within the input restriction range of the buffer IC 23 at the subsequent stage. The buffer IC 23 is disposed outside the solid-state imaging device 10, and is an element that receives the imaging signal Vout output from the output circuit 16d and amplifies it. In the present embodiment, since the drain voltage Vdr is changed only in the exposure period, the drain voltage Vdr can be changed so that the signal voltage is outside the input restriction range of the buffer IC 23 at the subsequent stage.

  That is, during the exposure period, since signal charges are being accumulated in each pixel, the signal charges are not transferred to the floating diffusion portion 16a, and no voltage signal is output from the floating diffusion portion 16a. Therefore, the above input restriction range is a range in which the linearity of the input / output of the buffer IC 23 can be maintained, and even if the drain voltage Vdr is varied during the exposure period, the signal voltage is not affected.

  Therefore, by raising the drain voltage Vdr without being restricted to the input restriction range of the buffer IC 23 at the subsequent stage, the potential difference between the source and the drain can be sufficiently increased, and the effect of suppressing hot carriers can be enhanced. it can.

  FIG. 8 is a block diagram illustrating a drain voltage generation circuit. FIG. 4A shows a drain voltage generation circuit for generating a conventional drain voltage Vdr, and FIG. 4B shows an example of a drain voltage generation circuit for generating a drain voltage Vdr according to the present embodiment. It is.

  As shown in FIG. 8A, in the conventional drain voltage generation circuit, a voltage dividing circuit composed of two MOS resistors 16f3 and 16f4 that connect the power supply Vdd and the ground Vss in series, A source follower circuit composed of a MOS resistor and a current source corresponding to the MOS 16f1 and 16f2 is provided.

  The voltage dividing circuit inputs a voltage obtained by dividing the power supply Vdd to the gate of the driving MOS 16f1 constituting the source follower circuit. As a result, a voltage corresponding to the voltage applied to the gate of the drive MOS 16f1 when the power supply Vdd exceeds a predetermined value is output to the drain of the drive MOS 16f1 as the drain voltage Vdr.

  On the other hand, as shown in FIG. 8B, the drain voltage generating circuit according to the present embodiment incorporates a switch circuit 16f5 in a voltage dividing circuit composed of two MOS resistors 16f3 and 16f4.

  The switch circuit 16f5 is configured by, for example, switching transistors combined in multiple stages, and uses a voltage that varies in voltage at the start timing and end timing of the exposure period, such as the control voltage Vctl and the substrate voltage Vsub described above. ON / OFF is driven. Accordingly, the switch circuit 16f5 is turned on during the moving image period, turned off during the exposure operation period, and turned on during the still image reading period.

  That is, when the switch circuit 16f5 is turned off, the power supply Vdd is directly input as a drive voltage to the drive MOS 16f1 via the voltage dividing circuit, and thus the drain voltage Vdr rises. On the other hand, when the switch circuit 16f5 is turned on, Vdd divided by the voltage dividing circuit is input as a drive voltage to the drive MOS 16f1, so that the drain voltage Vdr decreases.

  By using the drain voltage generating circuit according to FIG. 8B described above, the drain voltage Vdr is automatically changed to a desired voltage value only during the exposure period by adding several circuit elements to the conventional circuit. In addition, the drain voltage generation circuit 16f that can maintain the drain voltage Vdr in the other period at a constant voltage value can be realized.

(5) Summary:
As described above, the solid-state imaging device 10 according to the present embodiment transfers the signal charges generated by the optical sensor unit 12 and the signal charges generated by the optical sensor unit 12 using the CCD. Transfer unit (read gate unit 13, vertical transfer unit 14, horizontal transfer unit 15), floating diffusion unit 16a for storing signal charges transferred from the photosensor unit 12 by the transfer unit, and drain voltage Vdr The reset drain portion 16b, the reset gate portion 16c for switching the connection between the floating diffusion portion 16a and the reset drain portion 16b, and the source follower circuit connected to the floating diffusion portion 16a are provided. Signal charge accumulated in the portion 16a It includes an output circuit 16d which outputs a voltage signal corresponding to the drain voltage generating circuit 16f for changing the drain voltage Vdr in accordance with the operating state of the solid-state imaging device 10, the. This makes it possible to suppress whitening caused by hot carriers while maintaining the linearity and gain characteristics of the output signal and without increasing the number of transistors used, the circuit scale, and the circuit area.

  The application target of the technology according to the present embodiment is not limited to the solid-state imaging device, and the signal charge generated by the photoelectric conversion element such as a photodiode is transferred to the storage unit such as a floating diffusion and stored in the storage unit. Any solid-state imaging device that outputs a voltage signal corresponding to the signal charge can be applied to various devices. In this sense, it goes without saying that the CMOS solid-state imaging device is also an application target of the present technology.

  In addition, the present technology is not limited to the above-described embodiments and modifications, and the configurations disclosed in the above-described embodiments and modifications are mutually replaced, the combinations are changed, known technologies, and the above-described implementations. Configurations in which the configurations disclosed in the embodiments and modifications are mutually replaced or the combinations are changed are also included. Further, the scope of the technical idea according to the present technology is not limited to the above-described embodiment, but extends to the matters described in the claims and equivalents thereof.

In addition, the aspect of this technique demonstrated above can take the following structures.
(A) a photoelectric conversion unit for generating a signal charge according to the amount of received light;
A transfer unit for transferring the signal charge generated by the photoelectric conversion unit;
An accumulator for accumulating signal charges transferred from the photoelectric converter by the transfer unit;
A reset unit to which a reference voltage is input;
A switch unit for switching the connection between the storage unit and the reset unit;
An output circuit that is a source follower circuit connected to the storage unit and outputs a voltage signal corresponding to the signal charge stored in the storage unit;
A reference voltage control unit for changing the reference voltage according to the operating state of the solid-state imaging device;
A solid-state imaging device.

(B) The reference voltage control unit according to (a), wherein the reference voltage is changed to a voltage higher than that other than the exposure period in at least a part of an exposure period provided for capturing a still image. Solid-state image sensor.

(C) The reference voltage control unit receives the reference voltage and a signal voltage corresponding to the signal charge stored in the storage unit in at least a part of an exposure period provided for capturing a still image. The solid-state imaging device according to (a) or (b), wherein the voltage is changed to a voltage that is out of a performance guarantee range of the buffer circuit.

(D) The reference voltage control unit according to any one of (a) to (c), wherein the reference voltage of the storage unit is automatically changed using an internal signal of the solid-state imaging device. Solid-state image sensor.

(E) the storage unit is a floating diffusion unit;
The reset unit is a drain unit to which the reference voltage is input,
The switch unit is a gate unit that switches a connection between the storage unit and the drain unit, and
The solid-state imaging device according to any one of (a) to (d), wherein the floating diffusion portion is reset to the reference voltage by being connected to a drain portion under the control of the gate portion.

(F) The solid-state imaging device according to any one of (a) to (e), wherein the transfer unit transfers the signal charge generated by the photoelectric conversion unit using a CCD (Charge Coupled Device).

(F) a photoelectric conversion step in which the photoelectric conversion unit generates a signal charge corresponding to the amount of received light;
A transfer step in which the transfer unit transfers the signal charge generated by the photoelectric conversion unit;
An accumulation step of accumulating the signal charges transferred from the photoelectric conversion unit by the transfer unit in an accumulation unit;
A reset step of connecting a switch unit for switching the connection between the reset unit to which a reference voltage is input and the storage unit;
An output step of outputting a voltage signal corresponding to the signal charge stored in the storage unit to an output circuit configured by a source follower circuit connected to the storage unit;
A reference voltage control step of changing the reference voltage according to the operating state of the solid-state imaging device;
A method for driving a solid-state imaging device.

(G) a photoelectric conversion unit for generating a signal charge according to the amount of received light;
A transfer unit for transferring the signal charge generated by the photoelectric conversion unit;
An accumulator for accumulating signal charges transferred from the photoelectric converter by the transfer unit;
A reset unit to which a reference voltage is input;
A switch unit for switching the connection between the storage unit and the reset unit;
An output circuit that is a source follower circuit connected to the storage unit and outputs a voltage signal corresponding to the signal charge stored in the storage unit;
A reference voltage control unit for changing the reference voltage according to the operating state of the solid-state imaging device;
An electronic apparatus comprising a solid-state imaging device having

DESCRIPTION OF SYMBOLS 10 ... Solid-state image sensor, 11 ... Semiconductor substrate, 12 ... Optical sensor part, 13 ... Read-out gate part, 14 ... Vertical transfer part, 15 ... Horizontal transfer part, 16 ... Charge voltage conversion part, 16a ... Floating diffusion part, 16b ... Reset drain section, 16c ... reset gate section, 16d ... output circuit, 16e ... bias generation circuit, 16f ... drain voltage generation circuit, 17 ... substrate voltage generation circuit, 18 ... control voltage input terminal, 21 ... reset clock generation circuit, 22 ... Capacitor, 23 ... Buffer IC, 30 ... Control voltage generation circuit, 11a ... Semiconductor substrate, 11b ... P-type well, 11c ... Channel region, 11d ... Transfer region, 11e ... Storage region, 11f ... Output gate, 16f1 ... Drive MOS, 16f3... MOS resistor, 16f4... MOS resistor, 16f5. H, 100 ... Imaging device, 110 ... Optical system, 120 ... Solid-state imaging device, 130 ... DSP, 140 ... Frame memory, 150 ... Display device, 160 ... Recording device, 170 ... Operation system, 180 ... Power supply system, 190 ... Control unit

Claims (8)

A photoelectric conversion unit for generating a signal charge according to the amount of received light;
A transfer unit for transferring the signal charge generated by the photoelectric conversion unit;
An accumulator for accumulating signal charges transferred from the photoelectric converter by the transfer unit;
A reset unit to which a reference voltage is input;
A switch unit for switching the connection between the storage unit and the reset unit;
An output circuit configured by a source follower circuit connected to the storage unit, and outputting a voltage signal corresponding to the signal charge stored in the storage unit;
A reference voltage control unit for changing the reference voltage according to the operating state of the solid-state imaging device;
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the reference voltage control unit changes the reference voltage to a voltage higher than that other than the exposure period in at least a part of an exposure period provided for capturing a still image.   The reference voltage control unit includes a buffer circuit that receives the reference voltage and a signal voltage corresponding to a signal charge stored in the storage unit during at least a part of an exposure period provided for capturing a still image. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is changed to a voltage that is outside a range of performance guarantee.   The solid-state imaging device according to claim 1, wherein the reference voltage control unit automatically changes a reference voltage of the storage unit using an internal signal of the solid-state imaging device. The storage unit is a floating diffusion unit,
The reset unit is a drain unit to which the reference voltage is input,
The switch unit is a gate unit that switches a connection between the storage unit and the drain unit, and
2. The solid-state imaging device according to claim 1, wherein the floating diffusion portion is reset to the reference voltage by being connected to a drain portion under the control of the gate portion.   The solid-state imaging device according to claim 1, wherein the transfer unit transfers a signal charge generated by the photoelectric conversion unit by a CCD (Charge Coupled Device). A photoelectric conversion step in which the photoelectric conversion unit generates a signal charge according to the amount of received light;
A transfer step in which the transfer unit transfers the signal charge generated by the photoelectric conversion unit;
An accumulation step of accumulating the signal charges transferred from the photoelectric conversion unit by the transfer unit in an accumulation unit;
A reset step of connecting a reset unit to which a reference voltage is input and a switch unit for switching the connection of the storage unit;
An output step of outputting a voltage signal corresponding to the signal charge stored in the storage unit to an output circuit configured by a source follower circuit connected to the storage unit;
A reference voltage control step of changing the reference voltage according to the operating state of the solid-state imaging device;
A method for driving a solid-state imaging device. A photoelectric conversion unit for generating a signal charge according to the amount of received light;
A transfer unit for transferring the signal charge generated by the photoelectric conversion unit;
An accumulator for accumulating signal charges transferred from the photoelectric converter by the transfer unit;
A reset unit to which a reference voltage is input;
A switch unit for switching the connection between the storage unit and the reset unit;
An output circuit configured by a source follower circuit connected to the storage unit, and outputting a voltage signal corresponding to the signal charge stored in the storage unit;
A reference voltage control unit for changing the reference voltage according to the operating state of the solid-state imaging device;
An electronic apparatus comprising a solid-state imaging device having

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