JP2011128442A - Display panel, display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a display panel capable of achieving high gradation at low cost; a display device; and electrical equipment. <P>SOLUTION: A plurality of pixels 13R, a plurality of pixels 13G and a plurality of pixels 13B are arrayed according to colors, and also, periodically arranged in a row direction. A plurality of writing lines WSL and a plurality of power supply lines PSL are assigned one by two pixel rows. Two signal lines DTL are assigned by pixel column. One of the two signal lines DTL assigned by pixel column is connected to the pixel 13 included in one upper pixel row among the two pixel rows assigned by scanning line WSL. The other of the two signal lines DTL assigned by pixel column is connected to the second pixel included in the one lower pixel row among the two pixel rows assigned by scanning line WSL. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display panel that displays an image with a light emitting element arranged for each pixel, and a display device and an electronic apparatus including the display panel.

  In recent years, in the field of display devices that perform image display, display devices that use current-driven optical elements, such as organic EL (electroluminescence) elements, whose light emission luminance changes according to the value of a flowing current are used as light emitting elements of pixels. Developed and commercialized.

  Unlike a liquid crystal element or the like, the organic EL element is a self-luminous element. Therefore, a display device (organic EL display device) using an organic EL element does not require a light source (backlight), and thus has higher image visibility and lower power consumption than a liquid crystal display device that requires a light source. And the response speed of the element is fast.

  In the organic EL display device, similarly to the liquid crystal display device, there are a simple (passive) matrix method and an active matrix method as its driving method. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display device. For this reason, active matrix systems are currently being actively developed. In this method, a current flowing through a light emitting element arranged for each pixel is controlled by an active element (generally a TFT (Thin Film Transistor)) provided in a drive circuit provided for each light emitting element.

  Incidentally, in the organic EL display device, as in other display devices, higher gradation and higher definition are required. Conventionally, various methods relating to high gradation have been disclosed. For example, in order to realize high gradation, methods using a driver with a large number of bits are disclosed in various documents. Also, various methods have been disclosed for high definition. For example, in Patent Document 1, in order to solve the shortage of threshold correction time due to high definition, two signal lines are arranged for each column, one signal line is assigned to an even line, and the other signal line Is assigned to odd lines, and even lines and odd lines are driven in a time-sharing manner.

JP 2008-158303 A

  By the way, when a driver having a large number of bits is used to realize high gradation, there is a problem that the cost of the driver increases. In particular, in the case of a panel having a large number of pixels, a large number of drivers are required, which causes a problem that the cost of the display device increases.

  Further, when the pitch of the scanning lines in the panel is reduced for higher definition, for example, as shown in FIG. 11, the terminal pitch of the gate driver 110 is changed to the scanning lines (not shown) in the display panel 100. And the mounting width W1 of the gate driver 110 becomes larger than the width W2 of the display area 100A of the display panel 100. As a result, in the display panel 100, a large non-display area 100B that does not contribute to display is formed around the display area 100A, and the entire display panel 100 cannot be effectively used.

  The present invention has been made in view of such problems, and a first object thereof is to provide a display panel, a display device, and an electronic apparatus that can realize high gradation at low cost. A second object is to provide a display panel, a display device, and an electronic apparatus that can effectively use the entire panel in a high-definition panel.

  The display panel of the present invention includes a plurality of pixels arranged in a matrix, a plurality of scanning lines arranged in a row, and a plurality of signal lines arranged in a column. Each pixel has one light emitting element and one pixel circuit. A plurality of scanning lines are assigned one for each two pixel rows, and a plurality of signal lines are assigned two for each pixel column. One of the two signal lines assigned to each pixel column is connected to the first pixel included in the first pixel row among the two pixel rows assigned to each scanning line. The other of the two signal lines assigned to each pixel column is connected to a second pixel included in a second pixel row different from the first pixel row among the two pixel rows assigned to each scanning line. .

  The display device of the present invention includes the display panel and a drive unit that drives the display panel. An electronic apparatus according to the present invention includes the display device.

  In the display panel, the display device, and the electronic device of the present invention, a plurality of scanning lines are assigned to every two pixel rows, and a plurality of signal lines are assigned to every two pixel rows. Furthermore, one of the two signal lines assigned to each pixel column is connected to the first pixel in the first pixel row, and the other signal line is connected to the second pixel in the second pixel row. Thereby, for example, one pixel can be constituted by the first pixel and the second pixel, so that a gray level twice the number of gray levels of the data driver connected to the signal line can be realized. In the display panel, display device, and electronic device of the present invention, the number of scanning lines is half the number of pixel columns. Thereby, for example, even when the terminal pitch of the gate driver connected to the scanning line becomes larger than the pitch of the scanning line due to high definition, the mounting width of the gate driver is reduced in the display area of the display panel. It can be narrower than the width.

  According to the display panel, the display device, and the electronic apparatus of the present invention, for example, it is possible to realize a gradation that is twice the number of gradations of the data driver connected to the signal line. Thereby, high gradation can be realized at low cost. Further, according to the display panel, the display device, and the electronic apparatus of the present invention, for example, the mounting width of the gate driver can be made smaller than the width of the display area of the display panel. Thereby, the entire display panel can be effectively used in a high-definition panel.

It is a block diagram showing an example of the display apparatus which concerns on one embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of an internal configuration of each pixel in FIG. 1. FIG. 2 is a configuration diagram illustrating an example of a connection relationship between each pixel of FIG. 1 and a drive circuit. FIG. 2 is a top view illustrating an example of a configuration of the display panel in FIG. 1. It is a wave form diagram showing an example of the various waveforms in the display apparatus of FIG. It is a block diagram showing an example of the connection relationship different from the connection relationship of FIG. It is a perspective view showing the external appearance of the application example 1 of the display apparatus of the said embodiment. (A) is a perspective view showing the external appearance seen from the front side of the application example 2, (B) is a perspective view showing the external appearance seen from the back side. 12 is a perspective view illustrating an appearance of application example 3. FIG. 14 is a perspective view illustrating an appearance of application example 4. FIG. (A) is a front view of the application example 5 in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) is a left side view, and (E) is a right side view, (F) is a top view and (G) is a bottom view. It is a top view showing an example of the composition of the display panel concerning a comparative example.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the invention will be described in detail with reference to the drawings. The description will be given in the following order.

1. Embodiment (FIGS. 1 to 5)
2. Modified example (FIG. 6)
3. Application examples (FIGS. 7 to 11)
4). Comparative example (FIG. 12)

<Embodiment>
(Schematic configuration of the display device 1)
FIG. 1 shows an example of the entire configuration of a display device 1 according to an embodiment of the present invention. The display device 1 includes a display panel 10 and a drive circuit 20 (drive unit).

(Display panel 10)
The display panel 10 has a display area 10A in which three types of organic EL elements 11R, 11G, and 11B (light emitting elements) having different emission colors are two-dimensionally arranged. The display area 10A is an area for displaying an image using light emitted from the organic EL elements 11R, 11G, and 11B. The organic EL element 11R is an organic EL element that emits red light, the organic EL element 11G is an organic EL element that emits green light, and the organic EL element 11B is an organic EL element that emits blue light. The organic EL elements 11R, 11G, and 11B are light emitting elements having the same size, for example. Hereinafter, the organic EL element 11 is appropriately used as a general term for the organic EL elements 11R, 11G, and 11B.

(Display area 10A)
FIG. 2 shows an example of a circuit configuration in the display area 10A. In the display area 10 </ b> A, a plurality of pixel circuits 12 are two-dimensionally arranged in pairs with the individual organic EL elements 11. In the present embodiment, one organic EL element 11 and one pixel circuit 12 constitute one pixel 13. More specifically, as shown in FIG. 1, the pair of organic EL elements 11R and the pixel circuit 12 constitute one pixel 13R (red pixel), and the pair of organic EL elements 11G and the pixel circuit 12 are one. One pixel 13G (green pixel) is configured, and the pair of organic EL elements 11B and the pixel circuit 12 configure one pixel 13B (blue pixel).

Each pixel circuit 12 includes, for example, a drive transistor Tr ₁ , a write transistor Tr _2, and a storage capacitor C _s , and has a circuit configuration of 2Tr1C. The drive transistor Tr ₁ and the write transistor Tr ₂ are formed by, for example, n-channel MOS type thin film transistors (TFTs). The drive transistor Tr ₁ or the write transistor Tr ₂ may be, for example, a p-channel MOS type TFT.

In the display area 10A, a plurality of write lines WSL (scanning lines) are arranged in rows, and a plurality of signal lines DTL are arranged in columns. In the display region 10A, a plurality of power supply lines PSL (members to which power supply voltage is supplied) are further arranged in a row along the write lines WSL. One organic EL element 11 is provided near the intersection of each signal line DTL and each scanning line WSL. Each signal line DTL is the output end of the later of the signal line drive circuit 23 (not shown) is connected to either the drain electrode and source electrode of the writing transistor Tr ₂ (not shown). Each scanning line WSL is the output end of the write line drive circuit 24 will be described later (not shown) is connected to the gate electrode of the writing transistor Tr ₂ (not shown). Each power supply line PSL is connected to an output end (not shown) of a power supply line drive circuit 25 described later and either _one of a drain electrode and a source electrode (not shown) of the drive transistor Tr1. Of the drain electrode and the source electrode of the write transistor Tr ₂ , the one not connected to the signal line DTL (not shown) is connected to the gate electrode (not shown) of the drive transistor Tr ₁ and one end of the storage capacitor C _s. ing. Of the drain electrode and the source electrode of the driving transistor Tr ₁ , the one not connected to the power supply line PSL (not shown) and the other end of the storage capacitor C _s are connected to the anode electrode (not shown) of the organic EL element 11. Has been. A cathode electrode (not shown) of the organic EL element 11 is connected to the ground line GND, for example.

FIG. 3 illustrates an example of a connection relationship between each pixel 13 and the drive circuit 20. In FIG. 3, a suffix is added to the end of each write line WSL and each power supply line PSL. This suffix represents, for example, the scanning order of the write line WSL and each power supply line PSL. A suffix is also added to the end of each signal line DTL. This suffix represents the order when the signal lines DTL are counted in order from the left side. The signal line DTL whose order is an even number is represented as a signal line DTL _2k, and the signal line DTL whose order is an odd number. Is represented as a signal line DTL _2k-1 (see FIGS. 5A and 5B).

  The plurality of pixels 13R, the plurality of pixels 13G, and the plurality of pixels 13B are arranged in columns for each color and are periodically arranged in the row direction (for example, 13R, 13G, 13B, 13R, 13G, 13B,...). Is arranged. A plurality of write lines WSL are assigned to every two lines (two pixel rows). A plurality of power supply lines PSL are also allocated for every two lines (two pixel rows). A plurality of power supply lines PSL are assigned to every two lines to which the write line WSL is assigned.

A plurality of signal lines DTL are assigned two for each line (one pixel column). One of the two signal lines DTL assigned to each line (one pixel column) (for example, the odd-numbered signal line DTL _2k-1 ) is assigned to two lines (two pixel rows) assigned to each scanning line WSL. Are connected to pixels 13 (first pixels) included in one upper line (one pixel row), for example, to pixels 13 (first pixels) included in odd-numbered lines (pixel rows) from the upper side. It is connected. On the other hand, the other of the two signal lines DTL assigned to each line (one pixel column) (for example, the even-numbered signal line DTL _2k ) is assigned to two lines (two pixel rows) assigned to each scanning line WSL. Are connected to pixels 13 (second pixels) included in one lower line (one pixel row), for example, pixels 13 (second pixels) included in even-numbered lines (pixel rows) from the upper side. It is connected to the. The “upper one line” or “odd-numbered line” in the present embodiment corresponds to a specific example of “first pixel row” in the present invention. Further, “lower one line” or “even-numbered line” in the present embodiment corresponds to a specific example of “second pixel row” in the present invention.

More specifically, for example, the first signal line DTL ₁ is connected to the pixel 13R included in the upper one line (one pixel row) of the two lines (two pixel rows) assigned to each scanning line WSL. Has been. The second signal line DTL ₂ is connected to the pixels 13R included in one lower line (one pixel row) among the two lines (two pixel rows) assigned to each scanning line WSL. The pixels 13R connected to the signal line DTL ₁ and the pixels 13R connected to the signal line DTL ₂ are arranged in a common line (one pixel column) and assigned to each scanning line WSL. A red pixel unit 14R is configured for every two lines (two pixel rows).

Similarly, the third signal line DTL ₃ is connected to the pixels 13G included in the upper one line (one pixel row) of the two lines (two pixel rows) assigned to each scanning line WSL. The fourth signal line DTL ₄ is connected to the pixels 13G included in one lower line (one pixel row) of the two lines (two pixel rows) assigned to each scanning line WSL. The pixels 13G connected to the signal line DTL ₃ and the pixels 13G connected to the signal line DTL ₄ are arranged in a common line (one pixel column) and assigned to each scanning line WSL. A green pixel unit 14G is configured for every two lines (two pixel rows).

Further, the fifth signal line DTL ₅ is connected to the pixels 13B included in the upper one line (one pixel row) of the two lines (two pixel rows) assigned to each scanning line WSL. The sixth signal line DTL ₆ is connected to the pixels 13B included in the lower one line (one pixel row) of the two lines (two pixel rows) assigned to each scanning line WSL. The pixels 13B connected to the signal line DTL ₅ and the pixels 13B connected to the signal line DTL ₆ are arranged in a common line (one pixel column) and assigned to each scanning line WSL. A blue pixel unit 14B is configured for every two lines (two pixel rows). In the following description, the pixel unit 14 is used as a general term for the pixel units 14R, 14G, and 14B for convenience.

  The pixel units 14R, 14G, and 14B described above constitute one display pixel 15. That is, in the display device 1 of the present embodiment, the number of pixels included in the display pixel 15 is twice that of a normal display device in which one display pixel is formed by three of a red pixel, a green pixel, and a blue pixel (6 It is).

(Drive circuit 20)
Next, each circuit in the drive circuit 20 will be described with reference to FIG. The drive circuit 20 includes a timing generation circuit 21, a video signal processing circuit 22, a signal line drive circuit 23, a write line drive circuit 24, and a power supply line drive circuit 25.

  The timing generation circuit 21 controls the video signal processing circuit 22, the signal line drive circuit 23, the write line drive circuit 24, and the power supply line drive circuit 25 to operate in conjunction with each other. The timing generation circuit 21 outputs a control signal 21A to each circuit described above, for example, in response to (in synchronization with) the synchronization signal 20B input from the outside.

  The video signal processing circuit 22 performs predetermined correction on the video signal 20 </ b> A input from the outside, and outputs the corrected video signal 22 </ b> A to the signal line driving circuit 23. Examples of the predetermined correction include gamma correction and overdrive correction. Here, in the case where the video signal 20A is configured to include information about the luminance for each pixel, the video signal processing circuit 22 uses, for example, information about the luminance for each pixel included in the video signal 22A as a pixel unit. It is assigned every 14th. For example, the video signal processing circuit 22 determines that the luminance (luminance A) of one red pixel included in the video signal 22A is equal to the sum of the luminances of the two red pixels 13R included in the one pixel unit 14. (For example, so as to be equal), information on the luminance for the two red pixels 13R included in one pixel unit 14 is generated from the information on the luminance A. .

The signal line driving circuit 23 applies the video signal 22A (signal voltage V _sig ) input from the video signal processing circuit 22 to each signal line DTL in response to (in synchronization with) the input of the control signal 21A. This is to be written to the target pixel 13. That is, the signal line driving circuit 23 writes the signal voltage V _sig for controlling the gradation to each pixel 13. Note that writing refers to applying a predetermined voltage to the gate of the driving transistor Tr ₁ . The signal line driving circuit 23 outputs a signal voltage corresponding to the pixels 13 for two lines (two pixel columns) selected by the writing line driving circuit 24 to each signal line DTL.

  The write line driving circuit 24 sequentially selects one scanning line WSL from among the plurality of scanning lines WSL in response to (in synchronization with) the input of the control signal 21A. The power supply line drive circuit 25 sequentially applies a power supply voltage supplied from a power supply circuit (not shown) to the plurality of power supply lines PSL in response to (in synchronization with) the input of the control signal 21A, so that the organic EL element 11 emits light. And controls the extinction.

(Top panel configuration of display panel 10)
FIG. 4 illustrates an example of a top surface configuration of the display panel 10. The display panel 10 has a structure in which, for example, the drive panel 30 and the sealing panel 40 are bonded together via a sealing layer (not shown). For example, as shown in FIG. 4, a plurality of video signal supply TABs 51 (flexible printed wiring boards) are attached to one side (long side) of the drive panel 30. For example, a scanning signal supply TAB 52 (flexible printed wiring board) is attached to the other side (short side) of the drive panel 30. Further, for example, a power supply voltage supply TAB 53 (flexible printed wiring board) is attached to a short side of the drive panel 30 and a side different from the scanning signal supply TAB 52. The video signal supply TAB 51 is obtained by hollowly wiring an IC (second driver IC) in which the signal line driving circuit 23 is integrated into an opening of a film-like wiring board. The scanning signal supply TAB 52 is obtained by hollow wiring an IC (first driver IC) in which the writing line driving circuit 24 is integrated in an opening of a film-like wiring board. The power supply voltage supply TAB 53 is an IC in which the power supply line driving circuit 25 is integrated and is hollowly wired in the opening of a film-like wiring board. The power supply voltage supply TAB 53 is connected to the output terminal (not shown) of the power supply voltage adjustment circuit 26. The anode signal output TCP 54 is connected to the input terminal (not shown) of the power supply voltage adjustment circuit 26.

  The sealing panel 40 includes, for example, a sealing substrate (not shown) that seals the organic EL element 11 and a color filter (not shown). For example, the color filter is provided in a region of the surface of the sealing substrate through which light from the organic EL element 11 passes. The color filter has, for example, a red filter, a green filter, and a blue filter (not shown) corresponding to each of the organic EL elements 11R, 11G, and 11B.

(Operation of display device 1)
Next, an example of the operation (operation from extinction to light emission) of the display device 1 of the present embodiment will be described. In the present embodiment, even if the threshold voltage V _th and the mobility μ of the driving transistor Tr ₁ change with time, the light emission luminance of the organic EL element 11 is kept constant without being affected by them. For this reason, a correction operation for variations in the threshold voltage V _th and the mobility μ is incorporated.

In the present embodiment, the driving is performed every two lines (two pixel columns) for various reasons described later. Therefore, in this embodiment, every time two lines (two pixel columns) are scanned, signal voltages V _sig (V _sigA , V _sigB ) for two lines (two pixel columns) are applied to each signal line DTL. . Specifically, for the odd-numbered signal line DTL _2k-1, the signal voltage V _sigA is applied for the even-numbered signal lines DTL _2k, the signal voltage V _sigB is applied.

FIGS. 5A to 5F show examples of various waveforms in two lines (two pixel columns) of the display device 1. FIG 5 (A), V _ofs to the signal line _{DTL, V sig1A, V sig2A,} V sig3A are periodically applied, FIG. 5 (B), V _ofs to the signal line _DTL, V sig1B, V sig2B , V _sig3B is periodically applied. Note that 1 in 1A and 1B added to the end of V _sig indicates the top two lines (two pixel columns), and 2 in 2A and 2B added to the end of V _sig This indicates the second two lines (two pixel columns), and 3 in 3A and 3B added to the end of V _sig indicates the third two lines (two pixel columns) from the top.

FIG. 5C shows a state in which V _on and V _off are applied to the write line WSL ₁ at a predetermined timing. Incidentally, 1 attached to the end of the write line WSL ₁ is that this is a write line WSL corresponding to the two lines of the uppermost (2 pixel columns). FIG. 5D shows how V _CCL and V _CCH are applied to the power supply line PSL ₁ at a predetermined timing. Note that _{1 at} the end of the power supply line PSL ₁ indicates that the power supply line PSL corresponds to the top two lines (two pixel columns). FIGS. 5E and 5F show the gate voltage V _g of the drive transistor Tr ₁ in response to voltage application to the signal lines DTL _2k−1 , DTL _2k , the write line WSL ₁ , and the power supply line PSL ₁ . In addition, it is shown that the source voltage V _s changes from moment to moment.

[Threshold correction preparation period]
First, preparation for threshold correction is performed. Specifically, the power supply line drive circuit 25 lowers the voltage of the power supply line PSL ₁ from V _ccH the V _ccL (T _1). Then, the source voltage V _s becomes V _ccL , the organic EL element 11 is extinguished, and the gate voltage V _g is lowered to a predetermined voltage.

[Threshold correction period]
Next, threshold correction is performed. Specifically, after the write line drive circuit 24 increases the voltage of the write line WSL ₁ from V _off to V _{on while} the voltages of the signal lines DTL _2k−1 and DTL _2k are V _ofs. (T _2), the power supply line drive circuit 25 raises the voltage of the power supply line PSL ₁ from V _ccL the V _ccH (T _3). Then, the gate voltage V _g becomes V _ofs , and further, a current I _d flows between the drain and source of the drive transistor Tr ₁ , and the source voltage V _s increases. At this time, when the source voltage V _s is lower than (V _ofs −V _th ) (when threshold correction is not yet completed), the drive transistor Tr ₁ is cut off (the potential difference V _gs becomes V _th) . Until the current I _d flows between the drain and source of the drive transistor Tr ₁ . As a result, the holding capacitor C _s is charged to V _th, the potential difference V _gs becomes V _th. Thereafter, while the voltage of the signal lines DTL _2k-1 and DTL _2k continues to be V _ofs , the write line drive circuit 24 reduces the voltage of the write line WSL ₁ from V _on to V _off (T ₄ ). Then, the gate of the driving transistor Tr ₁ becomes floating, and the threshold correction is stopped. As a result, the potential difference V _gs can be maintained at V _th regardless of the voltage _levels of the signal lines DTL _2k−1 and DTL _2k . In this way, by setting the potential difference V _gs to V _th , the emission luminance of the organic EL element 11 varies even when the threshold voltage V _th of the drive transistor Tr ₁ varies for each pixel circuit 12. Can be eliminated.

[Threshold correction stop period]
Then, during the stop period of the threshold correction, the signal line drive circuit 23 changes the voltage of the signal line DTL _2k-1, DTL _2k from _{V ofs} V sig1A, the _V sig1B.

[Writing / μ correction period]
Next, writing and μ correction are performed. Specifically, the write line drive circuit 24 changes the voltage of the write line WSL ₁ from V _off to V _on while the voltages of the signal lines DTL _2k−1 and DTL _2k are V _sig1A and V _sig1B. up (T _5), connecting the gate of the drive transistor Tr ₁ in the signal line DTL _2k-1, DTL _2k. Then, the gate voltage of the drive transistor Tr ₁ becomes _V sig1A, V sig1B. At this time, the anode voltage of the organic EL element 11 is still smaller than the threshold voltage V _el of the organic EL element 11 at this stage, and the organic EL element 11 is cut off. Therefore, the current I _d flows through the element capacitance (not shown) of the organic EL element 11 and the element capacitance is charged. Therefore, the source voltage V _s increases by ΔV, and the potential difference V _gs eventually becomes V _sig1A + V _th −ΔV. (Or V _sig1B + V _th −ΔV). In this way, μ correction is performed simultaneously with writing. Here, ΔV increases as the mobility μ of the drive transistor Tr ₁ increases. Therefore, by reducing the potential difference V _gs by ΔV before light emission, variations in the mobility μ for each pixel circuit 12 can be removed. .

[Flash duration]
Next, the write line drive circuit 24 lowers the voltage of the write line WSL ₁ from V _on to V _off (T ₆ ). Then, the gate of the drive transistor Tr ₁ becomes floating, the gate of the drive transistor Tr ₁ - source voltage of the (potential difference V _gs) while maintaining a constant, the drain of the drive transistor Tr ₁ - current I _d between the source Flowing. As a result, the source voltage V _s rises, and the gate of the drive transistor Tr ₁ rises in conjunction with it, and the organic EL element 11 starts to emit light with a luminance smaller than the desired luminance.

  In the display device 1 according to the present embodiment, as described above, the pixel circuit 12 is controlled to be turned on / off in each pixel 13, and a driving current is injected into the organic EL element 11 of each pixel 13, thereby generating holes and electrons. Recombine with each other to emit light, and the light is extracted outside. As a result, an image is displayed in the display area 10 </ b> A of the display panel 10.

  By the way, it is conceivable to use a driver having a large number of bits as one method for realizing high gradation in an organic EL display device. However, in such a case, the cost of the driver increases. In particular, in the case of a panel having a large number of pixels, a large number of drivers are required, which increases the cost of the display device.

  Further, in an organic EL display device, as one method for realizing high definition, it is conceivable to narrow the pitch of scanning lines in a panel. However, if the pitch of the scanning lines in the panel is reduced, for example, as shown in FIG. 11, the terminal pitch of the gate driver 110 is larger than the pitch of the scanning lines (not shown) in the display panel 100. The mounting width W1 of the gate driver 110 becomes larger than the width W2 of the display area 100A of the display panel 100. As a result, in the display panel 100, a large non-display area 100B that does not contribute to display is formed around the display area 100A, and the entire display panel 100 cannot be effectively used.

  On the other hand, in the present embodiment, a plurality of scanning lines WSL are allocated one by one for every two lines (two pixel rows), and a plurality of signal lines DTL are allocated by two for each one line (one pixel column). Yes. Further, pixels included in one line (pixel row) of two lines (two pixel rows) in which one of the two signal lines DTL assigned to each line (one pixel column) is assigned to each scanning line WSL. 13 and the other signal line DTL is connected to the pixels 13 included in the other line (pixel row) of the two lines (two pixel rows) assigned to each scanning line WSL. Thereby, one pixel (for example, the display pixel 15 described above) can be configured by the plurality of pixels 13 connected to the two signal lines DTL assigned to each line (one pixel column). As a result, for example, it is possible to realize a gradation that is twice the number of gradations of the integrated IC (data driver connected to the signal line DTL) of the signal line driving circuit 23.

  As described above, in this embodiment, it is possible to realize a gradation twice as many as the number of gradations of the data driver connected to the signal line DTL. Thereby, high gradation can be realized at low cost. For example, when the number of gradations of the data driver is 8 bits, a 16-bit gradation can be realized. Therefore, even when a data driver with low specifications is used, a high-quality video can be displayed.

  In the present embodiment, the number of scanning lines WSL is half the number of pixel columns. Thereby, for example, even when the terminal pitch of the integrated IC (gate driver connected to the scanning line WSL) of the write line driving circuit 24 is larger than the pitch of the scanning line WSL, The mounting width W3 can be made narrower than the width W4 of the display area 10A of the display panel 10 (see FIG. 4). As a result, the entire display panel 10 can be effectively used.

<Modification>
(First modification)
In the above-described embodiment, the signal voltage V _sig for controlling the gradation is written in each pixel 13. For example, the signal voltage V is applied to one of the two pixels 13 included in the pixel unit 14. _sig may be written and a signal different from the signal voltage V _sig may be written to the other pixel 13. For example, a signal related to color conversion or a signal related to luminance correction may be written to the other pixel 13. At this time, the size of the organic EL element 11 to signal different from the signal voltage V _sig is included in the pixel 13 to be written, that is different from the size of the organic EL element 11 where the signal voltage V _sig is included in the pixel 13 to be written Is preferred, but it may be the same size.

(Second modification)
In the above embodiment, the pixel units 14R, 14G, and 14B constitute one display pixel 15. For example, as shown in FIG. 6, in each line (pixel row), the pixels 13R, 13G , 13B may constitute one display pixel 15. However, in this case, the number of gradations is the same as the number of gradations of the data driver connected to the signal line DTL. However, since the plurality of scanning lines WSL are assigned to every two lines (two pixel rows), it is possible to drive two lines (two pixel rows) at the same time as in the above embodiment.

Here, when the video signal 20A is configured to include information about the luminance for each pixel, the video signal processing circuit 22 uses the information about the luminance for each pixel included in the video signal 22A, for example, as the pixel 13. It is preferable to assign each. In this case, the signal writing for one frame is performed in half the time without changing the number of lines (number of display pixel rows) as compared with a display device of a type driven for each line (one pixel row). It can be performed. Therefore, for example, even when the display panel 10 is driven at a high frame rate of, for example, about 120 Hz, it is possible to secure a sufficient time for threshold correction and signal writing of the drive transistor Tr ₁ .

  In the present modification, the number of scanning lines WSL is half the number of pixel columns as in the above embodiment. Thereby, for example, due to high definition, the terminal pitch of the integrated IC (gate driver connected to the scanning line WSL) of the writing line driving circuit 24 becomes larger than the pitch of the scanning line WSL. However, the mounting width W3 of the gate driver can be made narrower than the width W4 of the display area 10A of the display panel 10. As a result, the entire display panel 10 can be effectively used in a high-definition panel.

<Application example>
Hereinafter, application examples of the display device 1 described in the above embodiment and the like will be described. The display device 1 according to the above-described embodiment or the like receives a video signal input from the outside or a video signal generated inside, such as a television device, a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, or a video camera. The present invention can be applied to display devices of electronic devices in various fields that display as images or videos.

(Application example 1)
FIG. 7 illustrates an appearance of a television device to which the display device 1 according to the above-described embodiment or the like is applied. The television apparatus has, for example, a video display screen unit 300 including a front panel 310 and a filter glass 320. The video display screen unit 300 is configured by the display device 1 according to the above-described embodiment and the like. Yes.

(Application example 2)
FIG. 8 illustrates an appearance of a digital camera to which the display device 1 according to the above-described embodiment or the like is applied. The digital camera includes, for example, a flash light emitting unit 410, a display unit 420, a menu switch 430, and a shutter button 440. The display unit 420 is configured by the display device 1 according to the above-described embodiment and the like. ing.

(Application example 3)
FIG. 9 illustrates an appearance of a notebook personal computer to which the display device 1 according to the above-described embodiment or the like is applied. The notebook personal computer has, for example, a main body 510, a keyboard 520 for inputting characters and the like, and a display unit 530 for displaying an image. The display unit 530 is a display according to the above-described embodiment and the like. The apparatus 1 is configured.

(Application example 4)
FIG. 10 shows an appearance of a video camera to which the display device 1 according to the above-described embodiment or the like is applied. This video camera has, for example, a main body 610, a subject photographing lens 620 provided on the front side surface of the main body 610, a start / stop switch 630 at the time of photographing, and a display 640. Reference numeral 640 denotes the display device 1 according to the above-described embodiment and the like.

(Application example 5)
FIG. 11 illustrates an appearance of a mobile phone to which the display device 1 according to the above-described embodiment or the like is applied. For example, the mobile phone is obtained by connecting an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. Yes. The display 740 or the sub-display 750 is configured by the display device 1 according to the above-described embodiment and the like.

  Although the present invention has been described with the embodiment, the modification, and the application example, the present invention is not limited to the above-described embodiment and the like, and various modifications can be made.

  For example, in the above-described embodiment, the case where the display device 1 is an active matrix type has been described. However, the configuration of the pixel circuit 12 for driving the active matrix is not limited to that described in the above-described embodiment, and is necessary. Depending on the case, a capacitor or a transistor may be added to the pixel circuit 12. In that case, a necessary drive circuit may be added in addition to the signal line drive circuit 23, the write line drive circuit 24, and the power supply line drive circuit 25 described above in accordance with the change of the pixel circuit 12.

  In the above-described embodiment and the like, the timing generation circuit 21 controls the driving of the signal line driving circuit 23, the writing line driving circuit 24, and the power supply line driving circuit 25, but other circuits control these driving. You may make it do. The control of the signal line drive circuit 23, the write line drive circuit 24, and the power supply line drive circuit 25 may be performed by hardware (circuit) or software (program).

  In the above-described embodiment and the like, the pixel circuit 12 has a 2Tr1C circuit configuration. However, as long as the pixel circuit 12 includes a circuit configuration in which a dual gate transistor is connected in series to the organic EL element 11. The circuit configuration may be other than the 2Tr1C circuit configuration.

Further, in the above-described embodiment and the like, the case where the drive transistor Tr ₁ and the write transistor Tr ₂ are formed by n-channel MOS thin film transistors (TFTs) is illustrated, but a p-channel transistor is exemplified. (For example, a p-channel MOS type TFT) may be used. However, in this case, the source and drain of the transistor Tr ₂ that are not connected to the power supply line PSL and the other end of the storage capacitor C _s are connected to the cathode of the organic EL element 11 and the anode of the organic EL element 11 is connected. Is preferably connected to GND or the like.

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 10, 100 ... Display panel, 10A, 100A ... Display area, 11, 11R, 11G, 11B ... Organic EL element, 12 ... Pixel circuit, 13, 13R, 13G, 13B ... Pixel, 14, 14R, 14G, 14B ... Pixel unit, 15 ... Display pixel, 20 ... Drive circuit, 20A, 22A ... Video signal, 20B ... Synchronization signal, 21 ... Timing generation circuit, 21A ... Control signal, 22 ... Video signal processing circuit, 23 ... Signal Line drive circuit 24 ... Write line drive circuit 25 ... Power supply line drive circuit 30 ... Drive panel 40 ... Sealing panel 51 ... Video signal supply TAB 52 ... Scanning signal supply TAB 53 ... Power supply voltage supply TAB , 100B ... non-display area, 110 ... gate driver, C _s ... holding capacity, DTL, DTL1～DTL18 ... signal line, I _d ... current, GND ... ground line, _{SL, PSL 1, PSL 2,} PSL 3 ... power lines, Tr ₁ ... driving transistor, Tr ₂ ... write transistor, V _g ... gate voltage, V _gs ... potential, V _s ... source _voltage, V _sig, V sig1A, V _sig1B , V _sig2A , V _sig2B , V _sig3A , V _sig3B ... signal voltage, V _ccH , V _CCL , V _off , V _ofs , V _on , ΔV ... voltage, V _th , V _el ... threshold voltage, W1 ... mounting width, W2... Width, WSL, WSL ₁ , WSL ₂ , WSL ₃ ... Write line, μ.

Claims (7)

A plurality of pixels arranged in a matrix;
A plurality of scan lines arranged in rows;
With multiple signal lines arranged in rows,
Each pixel has one light emitting element and one pixel circuit,
The plurality of scan lines are assigned one for every two pixel rows,
The plurality of signal lines are assigned two for each pixel column,
One of the two signal lines assigned to each pixel column is connected to the first pixel included in the first pixel row among the two pixel rows assigned to the scanning lines,
The other of the two signal lines assigned to each pixel column is connected to a second pixel included in a second pixel row different from the first pixel row among the two pixel rows assigned to each scanning line. The display panel. The display panel according to claim 1, wherein the first pixel and the second pixel include light emitting elements that emit the same color. The display panel according to claim 1, wherein the first pixel and the second pixel have light-emitting elements having the same size. The display panel according to claim 1, wherein the first pixel and the second pixel have light emitting elements of different sizes. A display panel;
A drive unit for driving the display panel,
The display panel includes a plurality of pixels arranged in a matrix, a plurality of scanning lines arranged in a row, and a plurality of signal lines arranged in a column,
Each pixel has one light emitting element and one pixel circuit,
The plurality of scan lines are assigned one for every two pixel rows,
The plurality of signal lines are assigned two for each pixel column,
One of the two signal lines assigned to each pixel column is connected to the first pixel included in the first pixel row among the two pixel rows assigned to the scanning lines,
The other of the two signal lines assigned to each pixel column is connected to a second pixel included in a second pixel row different from the first pixel row among the two pixel rows assigned to each scanning line. The display device. A flexible printed wiring board connected to the display panel;
The drive unit includes one or more first driver ICs connected to the plurality of scanning lines, and one or more second driver ICs connected to the plurality of signal lines,
The display device according to claim 5, wherein the first driver IC and the second driver IC are supported by the flexible printed wiring board. A display device,
The display device includes a display panel and a drive unit that drives the display panel,
The display panel includes a plurality of pixels arranged in a matrix, a plurality of scanning lines arranged in a row, and a plurality of signal lines arranged in a column,
Each pixel has one light emitting element and one pixel circuit,
The plurality of scan lines are assigned one for every two pixel rows,
The plurality of signal lines are assigned two for each pixel column,
One of the two signal lines assigned to each pixel column is connected to the first pixel included in the first pixel row among the two pixel rows assigned to the scanning lines,
The other of the two signal lines assigned to each pixel column is connected to a second pixel included in a second pixel row different from the first pixel row among the two pixel rows assigned to each scanning line. Electronic equipment.

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