JP2011176761A - Solid-state imaging apparatus and camera system - Google Patents

Abstract

Provided are a solid-state imaging device and a camera system capable of suppressing deterioration of output linearity and increase of fixed pattern noise even when the amount of light irradiation is small.
A solid-state imaging device according to the present invention includes a unit cell, a column signal line, a first current source, and a power supply unit. The power supply unit includes a reset transistor and a read transistor. When the FD unit 106 is reset, a power supply potential lower than the power supply potential when the signal voltage is output from the unit cell 100 to the column signal line 111 is reset. 125.
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device and a camera system.

  In recent years, MOS image sensors have attracted attention as solid-state imaging devices that can replace CCD image sensors. This has many advantages such as the fact that MOS-type image sensors can be manufactured by the CMOS process, existing facilities can be used, stable supply is possible, and high-speed reading is possible, so that high speed and high resolution can be achieved. This is because.

  For example, Patent Document 1 discloses a configuration and a driving method of a general MOS type solid-state imaging device.

JP 2008-067344 A

  A general solid-state imaging device will be described with reference to FIGS. FIG. 13 is a diagram illustrating an overall configuration of a general solid-state imaging device.

  In this solid-state imaging device, a plurality of unit cells 100 are arranged. In FIG. 13, for simplification of the drawing, the unit cells 100 are arranged in 2 rows × 2 columns. However, the present invention is not limited to this, and an arbitrary number of unit cells 100 are arranged in the row direction and the column direction. Can be done.

  In each of the plurality of unit cells 100, a photodiode 101 as a photoelectric conversion element (pixel), a transfer transistor 102, an FD (floating diffusion) unit 106, a reset transistor 103, a readout transistor 104, and a selection transistor 105 are arranged. .

  The plurality of unit cells 100 include a column signal line 111, a first current source 112 serving as a load for the read transistor 104, a CDS (Correlated Double Sampling) circuit 113, a horizontal selection transistor 114, a horizontal signal line 121, and a horizontal selection circuit 123. And an amplifier circuit 124 are connected.

  The column signal line 111 is connected to the ground via the first current source 112. The column signal line 111 forms a source follower circuit together with the read transistor 104 and the first current source 112 when the unit cell 100 is selected (when reading a signal). The output of the read transistor 104 is output to the CDS circuit 113.

  Light incident on the solid-state imaging device is converted into signal charges by the photodiode 101. The signal charge generated in the photodiode 101 is transferred by the transfer transistor 102 in response to the transfer pulse φTX, and is temporarily stored in the FD unit 106. The signal charge of the unit cell 100 selected by the selection transistor 105 in accordance with the selection pulse φSEL is converted into a voltage and output to the CDS circuit 113 via the column signal line 111. Further, the horizontal selection transistor 123 selectively turns on the horizontal selection transistor 114 to select the column signal line 111 that outputs the signal voltage to the horizontal signal line 121, and the signal voltage is output to the outside through the amplifier circuit 124. . The charge accumulated in the FD unit 106 is removed (reset) by the reset transistor 103 in response to the reset pulse φRS. The FD unit 106 is supplied with a reset potential supplied from the voltage source 126 connected via the pixel power line 125. Reset to. Further, the vertical selection circuit 122 performs driving by supplying driving pulses corresponding to the transfer transistor 102, the selection transistor 105, and the reset transistor 103.

Next, the operation of the solid-state imaging device will be described. FIG. 14 is a timing chart showing the operation timing of the solid-state imaging device of FIG. In FIG. 14, the horizontal axis represents time, and the vertical axis represents the potential of each signal. The reset pulse φRS represents a pulse signal for commonly controlling the reset transistors 103 in a predetermined row. The transfer pulse φTX represents a pulse signal for commonly controlling the transfer transistors 102 in a predetermined row. The selection pulse φSEL represents a pulse signal for commonly controlling the selection transistors 105 in a predetermined row. The potential V _fd represents the potential of the FD unit 106 of the predetermined unit cell 100, and the potential V _l represents the potential of the column signal line 111 connected to the predetermined unit cell 100. Hereinafter, the operation timing will be described by taking a predetermined unit cell 100 as an example, but other unit cells 100 can be operated in the same manner.

At time t ₀ , the potential of the selection pulse φSEL is set to “L” level, and the potential of the reset pulse φRS is set to “H” level. At this time, the transfer pulse φTX is at the “L” level, and the photodiode 101 and the FD unit 106 are electrically disconnected. In this state, the selection transistor 105 is in an off state, and the output of the reading transistor 104 is not read out to the column signal line 111. Further, the reset transistor 103 is in an on state, and the potential of the FD unit 106 is set to a reset level.

At time t ₁ , the potential of the selection pulse φSEL changes to “H” level, and the potential of the reset pulse φRS changes to “L” level. In this state, the reset transistor 103 is turned off and the selection transistor 105 is turned on. As a result, the read transistor 104 starts an operation of outputting the reset level to the column signal line 111.

At time t ₂ , the potential of the transfer pulse φTX changes to “H” level, and the transfer transistor 102 is turned on. As a result, the signal charge (electrons) of the photodiode 101 is transferred to the FD unit 106. The potential of the gate of the reading transistor 104 decreases in proportion to the amount of light incident on the pixel, and accordingly, the potential of the column signal line 111 decreases.

At time t ₃ , the potential of the transfer pulse φTX changes to “L” level, the transfer transistor 102 is turned off, and the transfer of signal charges (electrons) of the photodiode 101 is completed.

At time t ₄ , the potential of the selection pulse φSEL changes to “L” level, the potential of the reset pulse φRS changes to “H” level, the selection transistor 105 is turned off, and the potential of the FD portion 106 is reset again. Set to level.

  From the CDS circuit 113, the potential of the column signal line 111 when the FD unit 106 is reset to the potential of the pixel power supply line 125 and electrons corresponding to the amount of light irradiation are transferred from the photodiode 101 to the FD unit 106. A potential corresponding to the difference from the potential of the column signal line 111 is output.

  The output from the CDS circuit 113 of each column is sequentially read out to the horizontal signal line 121 for each column via the horizontal selection transistor 114 controlled by the horizontal selection circuit 123, amplified by the amplifier circuit 124, and output. .

  By sequentially performing the above operation for each row of the unit cells 100, signals of pixels arranged in an array in the XY directions are output, and two-dimensional image data is generated.

  However, the solid-state imaging device may cause degradation of output linearity when the amount of light irradiation is small, which leads to degradation of image quality due to fixed pattern noise. The reason will be described below.

である。 When the potential of the pixel power supply line 125 is V _dd , the potential V _fdrst of the FD unit 106 when the FD unit 106 is reset is

It is.

で示される。ここで、Ｖ_fdはＦＤ部１０６の電位、Ｖ_lは列信号線１１１の電位、Ｖ_thは読み出しトランジスタ１０４のしきい値電圧、βは読み出しトランジスタ１０４のトランスコンダクタンス係数である。 When the read transistor 104 operates in the saturation region, the amount of current I _ds flowing between the drain and source of the read transistor 104 is

Indicated by Here, V _fd is the potential of the FD portion 106, V _l is the potential of the column signal line 111, V _th is the threshold voltage of the read transistor 104, and β is the transconductance coefficient of the read transistor 104.

であらわされる。 The current flowing between the source and the drain of the reading transistor 104 is determined to be a constant value by the constant current source (first current source 112). If the current value of the constant current source is I _bias , the FD unit 106 is The potential V _l1rst of the column signal line 111 when reset is

It is expressed.

であらわされる。ここで、Ｎはフォトダイオード１０１で発生した電子の数、ｑは電子一つあたりの電荷量、ＣはＦＤ部１０６の容量である。この時の列信号線１１１の電位Ｖ_l1sigは、

となる。 Next, when electrons generated in the photodiode 101 are transferred to the FD unit 106, the potential of the FD unit 106 changes according to the number of electrons. The potential V _fdsig of the FD unit 106 at this time is

It is expressed. Here, N is the number of electrons generated in the photodiode 101, q is the amount of charge per electron, and C is the capacitance of the FD unit 106. The potential V _l1sig of the column signal line 111 at this time is

It becomes.

で示される。これより、読み出しトランジスタ１０４がリニア領域にある時の、ＦＤ部１０６をリセットした時の列信号線１１１の電位Ｖ_l2rst及びフォトダイオード１０１で発生した電子をＦＤ部１０６に転送した時の列信号線１１１の電位Ｖ_l2sigを求めると、

及び

となる。 Here, the expressions (3) and (5) are values when the reading transistor 104 operates in the saturation region. Assuming that the read transistor 104 operates in the linear region instead of the saturation region, the current I _ds flowing between the source and drain of the read transistor 104 is

Indicated by As a result, when the read transistor 104 is in the linear region, the column signal line when the potential V _l2rst of the column signal line 111 and the electrons generated in the photodiode 101 are transferred to the FD unit 106 when the FD unit 106 is reset. When the potential V _l2sig of 111 is obtained,

as well as

It becomes.

を満たす時はリニア領域、

を満たす時は飽和領域で動作する。 Whether a transistor operates in a saturation region or a linear region depends on the gate voltage, drain voltage, and threshold voltage of the transistor,

When satisfying the linear region,

When it satisfies, it operates in the saturation region.

  From Expression (1), Expression (4), Expression (9), and Expression (10), if the read transistor 104 is operating in the saturation region when the FD portion 106 is reset, electrons generated in the photodiode 101 are transferred. After that, the read transistor 104 operates in the saturation region. This is because the electrons have a negative charge, and the potential of the FD portion 106 after the electrons generated in the photodiode 101 are transferred is lower than the potential when the FD portion 106 is reset. However, if the readout transistor 104 is operating in the linear region when the FD portion 106 is reset, the readout transistor 104 after transferring electrons operates in the linear region when the amount of electrons generated in the photodiode 101 is small. However, when it is large, it operates in the saturation region.

となる。ここで、Ｖ_biasは任意の基準電位である。 In a general solid-state imaging device, the potential of the column signal line 111 after resetting the FD unit 106 in the CDS circuit 113 and the potential of the column signal line 111 after transferring electrons generated in the photodiode 101 are calculated. The difference is output from the CDS circuit 113. Therefore, the output potential V _o1 from the CDS circuit 113 when the read transistor 104 is operating in the saturation region when the FD unit 106 is reset is obtained from the equations (3) and (5).

It becomes. Here, V _bias is an arbitrary reference potential.

となる。 Further, if the read transistor 104 is operating in the linear region when the FD unit 106 is reset, the output voltage V _o2 from the CDS circuit 113 at that time is expressed by the equations (3), (7), (8), From Equation (9) and Equation (10),

It becomes.

Here, based on Expression (11), the output potential V _o1 of the CDS circuit 113 with respect to the number of electrons generated in the photodiode 101 when the reading transistor 104 operates in the saturation region when the FD unit 106 is reset is graphed. The result is shown in FIG. Further, based on Expression (12), the output potential V _o2 of the CDS circuit 113 with respect to the number of electrons generated in the photodiode 101 when the read transistor 104 operates in the linear region when the FD unit 106 is reset is graphed. This is shown in FIG.

  As shown in FIG. 16, when the read transistor 104 operates in the linear region when the FD unit 106 is reset, the number of generated electrons does not increase until the read transistor 104 operates in the saturation region. It can be seen that the increase in the output potential becomes nonlinear and the output linearity of the solid-state imaging device deteriorates. In addition, since the transistor characteristics in the linear region generally vary widely from transistor to transistor, fixed pattern noise that varies in output from unit cell 100 also increases.

Since the 1 / f noise has a great influence on the S / N of the solid-state imaging device, the readout transistor 104 has a thin gate oxide film thickness or a buried channel type in order to reduce the 1 / f noise. However, due to this influence, the threshold voltage V _th is lowered and often becomes 0 V or less. Even when the power supply voltage is lowered to reduce power consumption, the substrate bias effect of the read transistor 104 is reduced, so that the threshold voltage _Vth is lowered. In the actual transistor, the drain-source current also depends on the drain-source voltage in the region where the gate potential is close to the value obtained by adding the drain potential and the threshold voltage V _th even when the equation (9) is satisfied. To come.

  As described above, the reset potential of the FD unit 106 and the drain potential of the readout transistor 104 are the same potential as in the solid-state imaging device of FIG. It can be said that linearity is deteriorated and fixed pattern noise is increased.

  Therefore, the present invention has been made in view of such problems, and provides a solid-state imaging device and a camera system capable of suppressing degradation of output linearity and increase of fixed pattern noise even when the amount of light irradiation is small. For the purpose.

  To achieve the above object, a solid-state imaging device according to an aspect of the present invention is provided corresponding to a plurality of unit cells arranged in an array and a column of the unit cells, and the units of the corresponding column A column signal line commonly connected to the cell; a current source connected to the column signal line; and a power supply unit for supplying a power supply potential to the unit cell, wherein the unit cell includes a photodiode, FD (floating diffusion) part for temporarily holding the signal charge generated in the photodiode, and between the photodiode and the FD part, to transfer the charge from the photodiode to the FD part A transfer transistor connected to the FD unit, a reset transistor for resetting a potential of the FD unit, and a gate connected to the FD unit, A read transistor for reading a signal voltage corresponding to the potential of the D portion, and a selection transistor provided between the read transistor and the column signal line, and for outputting a signal voltage from the unit cell to the column signal line And the power supply unit includes a pixel power line commonly connected to the reset transistor and the readout transistor, and the signal from the unit cell to the column signal line when the FD unit is reset. A power supply potential lower than a power supply potential at the time of outputting a voltage is supplied through the pixel power supply line.

  According to this aspect, the reset potential of the FD portion can be made lower than the drain potential of the read transistor so that the read transistor operates in the saturation region even when the number of accumulated electrons of the photodiode is small. As a result, even when the amount of light irradiation is small, it is possible to operate the read transistor in the saturation region and suppress deterioration in linearity and increase in fixed pattern noise.

  Here, the power supply unit further includes a power supply for supplying a power supply potential to the pixel power supply line, a switch provided between the power supply and the power supply line, the pixel power supply line, and the power supply. May be provided with a resistor provided in parallel with the switch.

  In general, in the MOS process, the resistance can be generated in a very small area, so that the chip size can be reduced.

  The solid-state imaging device according to one embodiment of the present invention is provided corresponding to a plurality of unit cells arranged in an array and a column of the unit cells, and is commonly connected to the unit cells of the corresponding column. A column signal line, a current source connected to the column signal line, and a power supply unit for supplying a power supply potential to the unit cell. The unit cell is generated by a photodiode and the photodiode. An FD (floating diffusion) portion for temporarily holding the signal charge, and a transfer transistor provided between the photodiode and the FD portion for transferring the charge from the photodiode to the FD portion, A reset transistor connected to the FD unit for resetting the potential of the FD unit, and a gate connected to the FD unit, in accordance with the potential of the FD unit A read transistor for reading a signal voltage, and the power supply unit has a pixel power supply line commonly connected to the reset transistor and the read transistor, and at least three power supply potentials are supplied to one unit cell. When the FD unit is reset, the power supply unit supplies a power supply potential lower than the power supply potential when the signal voltage is output from the unit cell to the column signal line via the pixel power supply line. It is characterized by being supplied.

  According to this aspect, when the unit cell has a three-transistor configuration that does not include a selection transistor, it is possible to suppress degradation of linearity and increase of fixed pattern noise when the amount of light irradiation is small.

  Here, the power supply unit further includes a power supply for supplying a power supply potential to the pixel power supply line, a switch provided between the power supply and the power supply line, the pixel power supply line, and the power supply. May be provided with a resistor provided in parallel with the switch.

  According to this aspect, the chip size can be reduced.

  A camera system according to one embodiment of the present invention includes the solid-state imaging device.

  According to this aspect, it is possible to suppress degradation of linearity and increase of fixed pattern noise when the amount of light irradiation is small.

  According to the first aspect of the present invention, when the FD portion is reset regardless of the threshold voltage of the read transistor, the operation region of the read transistor can be a saturation region, and the number of charges stored in the photodiode is small. Also, deterioration of linearity and increase of fixed pattern noise are suppressed.

  According to the second aspect of the present invention, in a solid-state imaging device that realizes a high S / N, without increasing the number of constituent elements, the read transistor when the FD portion is reset regardless of the threshold voltage of the read transistor. The operation region can be a saturation region, and without increasing the chip size, the deterioration of linearity and the increase of fixed pattern noise are suppressed even when the number of electrons stored in the photodiode is small.

1 is a diagram illustrating an overall configuration of a solid-state imaging device according to a first embodiment of the present invention. It is an operation | movement timing chart of the solid-state imaging device of 1st Embodiment in this invention. It is a figure which shows the whole structure of the solid-state imaging device of the modification of 1st Embodiment in this invention. It is an operation | movement timing chart of the solid-state imaging device of the modification of 1st Embodiment in this invention. It is a figure which shows the whole structure of the solid-state imaging device of 2nd Embodiment in this invention. It is an operation | movement timing chart of the solid-state imaging device of 2nd Embodiment in this invention. It is a figure which shows the whole structure of the solid-state imaging device of 3rd Embodiment in this invention. It is a figure which shows the whole structure of the solid-state imaging device of the comparative example of 3rd Embodiment in this invention. It is an operation | movement timing chart of the solid-state imaging device of the comparative example of 3rd Embodiment in this invention. It is a timing chart which shows an analog-digital conversion operation | movement. It is an operation | movement timing chart of the solid-state imaging device of 3rd Embodiment in this invention. It is a figure which shows the whole structure of the imaging device of 4th Embodiment in this invention. It is a figure which shows the whole structure of a general solid-state imaging device. It is an operation | movement timing chart of a general solid-state imaging device. It is a figure which shows the relationship between the output electric potential of a CDS circuit, and the number of electrons which generate | occur | produced in the photodiode. It is a figure which shows the relationship between the output electric potential of a CDS circuit, and the number of electrons which generate | occur | produced in the photodiode.

  Hereinafter, a solid-state imaging device and a camera system according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating an overall configuration of a solid-state imaging device according to a first embodiment of the present invention. In FIG. 1, the same components as those in FIG. 13 are given the same reference numerals.

  The solid-state imaging device of this embodiment includes a plurality of unit cells 100 arranged in an array in the XY direction, a column signal line 111, a first current source 112, a CDS circuit 113, a horizontal selection transistor 114, Horizontal signal line 121, vertical selection circuit 122, horizontal selection circuit 123, amplifier circuit 124, pixel power supply line 125, first power supply switching transistor 131, first voltage source 132, and second power supply A switching transistor 133 and a second voltage source 134 are provided.

  In the unit cell 100, a photodiode 101 as a photoelectric conversion element (pixel) and signal charges (electrons) generated by the photodiode 101 are transferred, and the signal charges generated by the photodiode 101 are temporarily held. The FD unit 106 is connected between the photodiode 101 and the FD unit 106, and is connected to the transfer transistor 102 and the FD unit 106 for transferring electrons from the photodiode 101 to the FD unit 106. A reset transistor 103 for resetting (initializing) the potential, a read transistor (amplification transistor) 104 for reading a voltage signal corresponding to the potential of the FD unit 106, a gate connected to the FD unit 106, and a read transistor 104 And a column signal line 111, and a read transistor It selects the output of the motor 104, and a selection transistor 105 for outputting a voltage signal to the column signal line 111 from the unit cell 100.

  The column signal lines 111 are provided corresponding to the columns of the unit cells 100 and are commonly connected to the unit cells 100 of the corresponding columns.

  The first current source 112 is connected to the column signal line 111.

  The CDS circuit 113 is connected to the column signal line 111. The CDS circuit 113 is provided for each column signal line 111, and the potential difference at any two different timings in the corresponding column signal line 111, that is, the potential at the time of reset operation (the column signal line when the FD unit 106 is at the reset potential). The signal corresponding to the difference between the output potential to 111 and the potential at the time of signal output operation (the output potential to the column signal line 111 when the signal charge is transferred to the FD portion 106) is output.

  The horizontal selection transistor 114 is connected to the CDS circuit 113.

  The horizontal signal line 121 is commonly connected to the horizontal selection transistors 114 in each column.

  The vertical selection circuit 122 controls the transistor of the unit cell 100.

  The horizontal selection circuit 123 controls the horizontal selection transistor 114.

  The amplifier circuit 124 is connected to the horizontal signal line 121.

  The pixel power line 125 is connected in common to the reset transistor 103 and the readout transistor 104 of the unit cell 100 and supplies a power supply potential to the unit cell 100. The pixel power supply line 125 has a power supply potential lower than the power supply potential when the signal voltage is output from the unit cell 100 to the column signal line 111 (during signal output operation) when the FD unit 106 is reset (during the reset operation). Supply. In other words, the power supply unit configured by the pixel power line 125, the first power switching transistor 131, the first voltage source 132, the second power switching transistor 133, and the second voltage source 134 is in a reset operation. A power supply potential (a power supply potential different from the ground potential) lower than the power supply potential (a power supply potential different from the ground potential) during the signal output operation is supplied to the unit cell 100 via the pixel power supply line 125.

  The second power supply switching transistor 133 is a switch provided between the second voltage source 134 and the pixel power supply line 125, and is connected to the pixel power supply line 125 and the second voltage source 134.

  The first power supply switching transistor 131 is a switch provided between the first voltage source 132 and the pixel power supply line 125, and is connected to the pixel power supply line 125 and the first voltage source 132.

  The first voltage source 132 supplies a power supply potential different from the ground potential to the pixel power supply line 125.

  The second power supply switching transistor 133 is a switch provided between the second voltage source 134 and the pixel power supply line 125, and is connected to the pixel power supply line 125 and the second voltage source 134.

  The second voltage source 134 supplies a power supply potential different from the ground potential to the pixel power supply line 125. The first voltage source 132 and the second voltage source 134 are power sources having different power source potentials. The power source potential supplied from the second voltage source 134 to the pixel power source line 125 is determined by the first voltage source 132. It is set lower than the power supply potential supplied to the line 125.

  1 includes a column A / D conversion circuit that is provided corresponding to each CDS circuit 113 and that performs A / D conversion (analog-digital conversion) on the output signal of the corresponding CDS circuit 113. There may be. That is, the solid-state imaging device shown in FIG. 1 has a configuration having an amplifier circuit (column amplifier) for each column, a configuration having an AD conversion circuit for each column, and performing external output with digital signals, and performing external output with analog signals. Any of the configurations can be used.

  1 includes a pixel, a transfer transistor, an FD unit, a reset transistor, an amplifying transistor, and a selection transistor, a so-called 1-pixel 1-cell structure, and a plurality of pixels in one unit cell. Furthermore, any one of the FD portion, the reset transistor, the amplification transistor, and the selection transistor, or a structure in which all of them are shared in one unit cell, that is, a so-called multi-pixel 1-cell structure can be used. That is, in the unit cell 100 of FIG. 1, one reset transistor, one readout transistor, and one selection transistor are provided corresponding to one pixel, but a plurality of adjacent pixels share the reset transistor, readout transistor, and selection transistor. The number of transistors per pixel can be substantially reduced.

  In addition, the solid-state imaging device of FIG. 1 has a structure in which pixels are formed on the surface of a semiconductor substrate, that is, on the same side as the surface on which the gate terminal and wiring of the transistor are formed, and A so-called back-illuminated image sensor (back-illuminated solid-state imaging device) structure formed on the back surface side with respect to the surface on which the gate terminal and the wiring are formed can also be used.

  FIG. 2 is an operation timing chart of the solid-state imaging device shown in FIG.

In FIG. 2, the horizontal axis represents time, and the vertical axis represents the potential of each signal. The reset pulse φRS represents a pulse signal for commonly controlling the reset transistors 103 in a predetermined row. The transfer pulse φTX represents a pulse signal for commonly controlling the transfer transistors 102 in a predetermined row. The selection pulse φSEL represents a pulse signal for commonly controlling the selection transistors 105 in a predetermined row. The potential V _fd represents the potential of the FD unit 106 of the predetermined unit cell 100, and the potential V _l represents the potential of the column signal line 111 connected to the predetermined unit cell 100. The power supply pulse φVDCEL1 represents a pulse signal that controls the first power supply switching transistor 131. A power pulse φVDCEL2 represents a pulse signal that connects the second power switching transistor 133. The potentials V _ddpx , V _ddrd, and V _ddrs respectively represent the potential of the pixel power supply line 125, the first power supply potential, and the second power supply potential. The potentials V _fdrst2 and V _fdsig2 are the potential of the FD unit 106 when reset and the potential of the FD unit 106 when electrons generated in the photodiode 101 are transferred, respectively.

  First, when the selection pulse φSEL becomes “H” level, all the selection transistors 105 connected to the selection pulse φSEL are turned on.

となる。 Next, when the reset pulse φRS becomes “H” level, all the reset transistors 103 connected to the reset pulse φRS are turned on, and the potential V _fd of the FD portion 106 in the corresponding row is _{equal to} the potential V _{ddpx of the} pixel power supply line 125. At this time, since the power supply pulses φVDCEL1 and φVDCEL2 are set to the “H” level and the “L” level, respectively, the potential _Vddpx of the pixel power supply line 125 is the second power supply potential _Vddrs , and the FD portion The potential V _fdrst2 of

It becomes.

Next, after the reset pulse φRS is set to the “L” level, φVDCEL1 is switched to the “L” level and φVDCEL2 is switched to the “H” level, and the potential _Vddpx of the pixel power supply line 125 becomes the first power supply potential _Vddrd .

で表される。 Next, when the transfer pulse φTX becomes “H” level, all the transfer transistors 102 connected to the transfer pulse φTX are turned on, and electrons generated in the photodiodes 101 in the corresponding row are transferred to the FD unit 106. When the number of transferred electrons is N, the charge amount per electron is q, and the capacitance of the FD unit 106 is C, the potential V _fdsig2 of the FD unit 106 is

It is represented by

The electrical signal transferred to the FD unit 106 is read to the column signal line 111 as a voltage signal by a source follower circuit including the read transistor 104 and the first current source 112. Then, the potential V _l of the column signal line 111 when the potential V _fd of the FD portion 106 is reset to the potential V _ddpx of the pixel power supply line 125 and the electrons accumulated according to the amount of light irradiation are transferred to the FD portion 106. A potential corresponding to the difference from the potential V ₁ of the column signal line at this time is output from the CDS circuit 113.

  The output from the CDS circuit 113 of each column is sequentially read out to the horizontal signal line 121 for each column via the horizontal selection transistor 114 controlled by the horizontal selection circuit 123, amplified by the amplifier circuit 124, and output. .

In contrast to a general solid-state imaging device, the solid-state imaging device according to the first embodiment has a pixel power supply line 125 for reading out the potential V _ddpx of the pixel power supply line 125 and the signal of the FD unit 106 when the FD unit 106 is reset. The potential V _ddpx of the pixel power supply line 125 when the FD unit 106 is reset is lowered by _switching the potential V _ddpx of the pixel FD unit 106. Accordingly, the reset potential of the FD portion 106 can be made lower than the drain potential of the read transistor 104 so that the read transistor 104 operates in the saturation region even when the number of accumulated electrons of the photodiode 101 is small.

を満たすような第２の電源電位Ｖ_ddrs及び第１の電源電位Ｖ_ddrdに設定することで、フォトダイオード１０１の蓄積電子数が少ない場合でも、読み出しトランジスタ１０４を飽和領域で動作させ、リニアリティの劣化及び固定パターンノイズの増加を抑えることが可能となる。 Specifically, from Equation (9), Equation (10) and Equation (14),

By setting the second power supply potential V _DDRs and the first power supply potential V _DDRD that satisfies, even if the number of stored electrons of the photodiode 101 is small, the read transistor 104 is operated in the saturation region, the linearity of the degradation In addition, an increase in fixed pattern noise can be suppressed.

(Modification of the first embodiment)
Here, in the configuration shown in FIG. 1, the potential supplied to the pixel power supply line 125 is switched using two voltage sources. However, the pixel power supply line using only the voltage source supplying the first power supply potential V _ddrd is used. It is also possible to switch the potential supplied to 125. A solid-state imaging device having such a configuration is shown in FIG. 3 as a modification of the first embodiment of the present invention.

  FIG. 3 is a diagram illustrating an overall configuration of a solid-state imaging device according to a modification of the first embodiment of the present invention. In FIG. 3, the same components as those in FIG.

  The solid-state imaging device of the present modification includes a plurality of unit cells 100 arranged in an array in the XY direction, a column signal line 111, a first current source 112, a CDS circuit 113, a horizontal selection transistor 114, Horizontal signal line 121, vertical selection circuit 122, horizontal selection circuit 123, amplifier circuit 124, pixel power supply line 125, first power supply switching transistor 131, first voltage source 132, and second power supply A switching transistor 133, a second current source 141, and a transistor 142 are provided.

  The unit cell 100 includes a photodiode 101, an FD unit 106 to which signal charges (electrons) generated in the photodiode 101 are transferred, and temporarily hold the signal charges generated in the photodiode 101, and a photodiode. A transfer transistor 102 provided between the photodiode 101 and the FD unit 106 for transferring electrons from the photodiode 101 to the FD unit 106 and a reset transistor connected to the FD unit 106 for resetting the potential of the FD unit 106 103 and a gate are connected to the FD unit 106, and are provided between the read transistor 104 and the column signal line 111 for reading out a voltage signal corresponding to the potential of the FD unit 106. The output is selected, and the column signal line 111 from the unit cell 100 is selected. And a selection transistor 105 for outputting a voltage signal.

  The column signal lines 111 are provided corresponding to the columns of the unit cells 100 and are commonly connected to the selection transistors 105 in the corresponding columns.

  The first current source 112 is connected to the column signal line 111.

  The CDS circuit 113 is connected to the column signal line 111. The CDS circuit 113 is provided for each column signal line 111 and outputs a signal corresponding to a potential difference at any two different timings in the corresponding column signal line 111.

  The horizontal selection transistor 114 is connected to the CDS circuit 113.

  The horizontal signal line 121 is commonly connected to the horizontal selection transistors 114 in each column.

  The vertical selection circuit 122 controls the transistor of the unit cell 100.

  The horizontal selection circuit 123 controls the horizontal selection transistor 114.

  The amplifier circuit 124 is connected to the horizontal signal line 121.

  The pixel power line 125 is connected in common to the reset transistor 103 and the readout transistor 104 of the unit cell 100 and supplies a power supply potential to the unit cell 100. The pixel power supply line 125 supplies a power supply potential lower than the power supply potential when the signal voltage is output from the unit cell 100 to the column signal line 111 when the FD unit 106 is reset. In other words, a power supply unit configured by the pixel power line 125, the first power switching transistor 131, the first voltage source 132, the second power switching transistor 133, the second current source 141, and the transistor 142 is: A power supply potential (power supply potential different from the ground potential) lower than the power supply potential (power supply potential different from the ground potential) during the signal output operation during the reset operation is supplied to the unit cell 100 through the pixel power supply line 125.

  The first power supply switching transistor 131 is a switch provided between the first voltage source 132 and the pixel power supply line 125, and is connected to the pixel power supply line 125 and the first voltage source 132.

  The first voltage source 132 supplies a power supply potential different from the ground potential to the pixel power supply line 125.

  The second power supply switching transistor 133 is connected to the pixel power supply line 125. The source potential of the second potential supply transistor 142 is connected to the second power supply switching transistor 133.

  The transistor 142 has a gate and a drain connected to the first voltage source 132 and forms a source follower circuit paired with the second current source 141.

  FIG. 4 is an operation timing chart of the solid-state imaging device shown in FIG.

In FIG. 4, the horizontal axis represents time, and the vertical axis represents the potential of each signal. The reset pulse φRS represents a pulse signal for commonly controlling the reset transistors 103 in a predetermined row. The transfer pulse φTX represents a pulse signal for commonly controlling the transfer transistors 102 in a predetermined row. The selection pulse φSEL represents a pulse signal for commonly controlling the selection transistors 105 in a predetermined row. The potential V _fd represents the potential of the FD unit 106 of the predetermined unit cell 100, and the potential V _l represents the potential of the column signal line 111 connected to the predetermined unit cell 100. The power supply pulse φVDCEL1 represents a pulse signal that controls the first power supply switching transistor 131. The power supply pulse φVDCEL2 represents a pulse signal that controls the second power supply switching transistor 133. The potentials V _ddpx , V _ddrd, and V _ddrs2 represent the potential of the pixel power supply line 125, the first power supply potential, and the source potential of the transistor 142, respectively.

である。従って、式（１６）及び式（１７）より、

を満たすパラメータに設定することで、フォトダイオード１０１での発生電子数が少ない場合でも、読み出しトランジスタ１０４を飽和領域で動作させ、リニアリティの劣化や固定パターンノイズの増加を抑えることが可能となる。 The selection pulse φSEL, the reset pulse φRS, the transfer pulse φTX, and the power supply pulses φVDCEL1 and φVDCEL2 are the same signals as those in the operation timing chart shown in FIG. 2, but the second power supply potential V _{ddrs in} FIG. The source potential V _ddrs2 . When the current value of the second current source 141 is I _vdcel , the threshold voltage of the transistor 142 is V _th2 , and the transconductance coefficient of the transistor 142 is β ₂ , the source potential V _ddrs2 of the transistor 142 is

It is. Therefore, from Equation (16) and Equation (17),

By setting the parameter to satisfy the condition, even when the number of electrons generated in the photodiode 101 is small, the reading transistor 104 can be operated in the saturation region, and deterioration of linearity and increase of fixed pattern noise can be suppressed.

As described above, even in a configuration in which the potential supplied to the pixel power supply line 125 is switched using only the voltage source that supplies the first power supply potential V _ddrd , it is possible to suppress deterioration in linearity and increase in fixed pattern noise. .

A method of generating a first power supply potential V _DDRD different potentials V _Ddrs2 by using the voltage source for supplying a first power supply potential V _DDRD is considered a number other than the circuit shown in FIG. 3, both the first The same effects as those of the embodiment can be obtained, and this modification does not specify the method.

(Second Embodiment)
FIG. 5 is a diagram illustrating an overall configuration of a solid-state imaging apparatus according to the second embodiment of the present invention. In FIG. 5, the same components as those in FIG. Hereinafter, the difference from the first embodiment will be mainly described, and the other parts are the same as those of the first embodiment.

  The solid-state imaging device of this embodiment includes a plurality of unit cells 100 arranged in an array in the XY direction, a column signal line 111, a first current source 112, a CDS circuit 113, a horizontal selection transistor 114, A horizontal signal line 121, a vertical selection circuit 122, a horizontal selection circuit 123, an amplification circuit 124, a pixel power supply line 125, a voltage switching transistor 151, a voltage source 152, and a voltage drop resistor 153 are provided.

  The unit cell 100 includes a photodiode 101, an FD unit 106 to which signal charges (electrons) generated in the photodiode 101 are transferred, and temporarily hold the signal charges generated in the photodiode 101, and a photodiode. A transfer transistor 102 provided between the photodiode 101 and the FD unit 106 for transferring electrons from the photodiode 101 to the FD unit 106 and a reset transistor connected to the FD unit 106 for resetting the potential of the FD unit 106 103 and a gate are connected to the FD unit 106, and are provided between the read transistor 104 and the column signal line 111 for reading out a voltage signal corresponding to the potential of the FD unit 106. The output is selected, and the column signal line 111 from the unit cell 100 is selected. And a selection transistor 105 for outputting a voltage signal.

  The column signal lines 111 are provided corresponding to the columns of the unit cells 100 and are commonly connected to the selection transistors 105 of the corresponding columns.

  The first current source 112 is connected to the column signal line 111.

  The CDS circuit 113 is connected to the column signal line 111. The CDS circuit 113 is provided for each column signal line 111 and outputs a signal corresponding to a potential difference at any two different timings in the corresponding column signal line 111.

  The horizontal selection transistor 114 is connected to the CDS circuit 113.

  The horizontal signal line 121 is commonly connected to the horizontal selection transistors 114 in each column.

  The vertical selection circuit 122 controls the transistor of the unit cell 100.

  The horizontal selection circuit 123 controls the horizontal selection transistor 114.

  The amplifier circuit 124 is connected to the horizontal signal line 121.

  The pixel power line 125 is connected in common to the reset transistor 103 and the readout transistor 104 of the unit cell 100 and supplies a power supply potential to the unit cell 100. The pixel power supply line 125 supplies a power supply potential lower than the power supply potential when the signal voltage is output from the unit cell 100 to the column signal line 111 when the FD unit 106 is reset. In other words, the power supply unit configured by the pixel power supply line 125, the voltage switching transistor 151, the voltage source 152, and the voltage reduction resistor 153 has a power supply potential (a power supply potential different from the ground potential) during the signal output operation during the reset operation. A lower power supply potential (a power supply potential different from the ground potential) is supplied to the unit cell 100 through the pixel power supply line 125.

  The voltage switching transistor 151 is a switch provided between the voltage source 152 and the pixel power supply line 125, and is connected to the pixel power supply line 125 and the voltage source 152.

  The voltage source 152 supplies a power supply potential different from the ground potential to the pixel power supply line 125.

  The voltage drop resistor 153 is inserted between the pixel power line 125 and the voltage source 152 so as to be in parallel with the voltage switching transistor 151.

  FIG. 6 is an operation timing chart of the solid-state imaging device shown in FIG.

In FIG. 6, the horizontal axis represents time, and the vertical axis represents the potential of each signal. The reset pulse φRS represents a pulse signal for commonly controlling the reset transistors 103 in a predetermined row. The transfer pulse φTX represents a pulse signal for commonly controlling the transfer transistors 102 in a predetermined row. The selection pulse φSEL represents a pulse signal for commonly controlling the selection transistors 105 in a predetermined row. The potential V _fd represents the potential of the FD unit 106 of the predetermined unit cell 100, and the potential V _l represents the potential of the column signal line 111 connected to the predetermined unit cell 100. The power supply pulse φVDCEL3 represents a pulse signal for controlling the voltage switching transistor 151. The potentials V _ddpx , V _ddrd, and V _{ddrs 3} are the potential of the pixel power supply line 125, the potential supplied by the voltage source 152, and the potential of the pixel power supply line 125 when the power supply pulse φVDCEL 3 is at “H” level. The potentials V _fdrst3 and V _fdsig3 are the potential of the FD unit 106 when reset and the potential of the FD unit 106 when electrons generated in the photodiode 101 are transferred, respectively.

  First, when the selection pulse φSEL becomes “H” level, all the selection transistors 105 connected to the selection pulse φSEL are turned on.

で表される。電圧降下用抵抗１５３の抵抗値をＲとすると、抵抗による電圧降下でＶ_ddrs3は

となる。従って、ＦＤ部１０６をリセットした時のＦＤ部１０６の電位Ｖ_fdrst3は

となる。 Next, when the reset pulse φRS becomes “H” level, all the reset transistors 103 connected to the reset pulse φRS are turned on, and the FD portion 106 in the corresponding row is reset to the potential of the pixel power supply line 125. At this time, since the power supply pulse φVDCEL3 is at “H” level, the current flowing from the voltage source 152 to the pixel power supply line 125 passes through the voltage drop resistor 153. The amount of current flowing through the pixel power line 125 is a value obtained by multiplying the amount of current of the first current source 112 by the total number of first current sources 112 arranged in a plurality. _Assuming that the current amount of the first current source 112 is I _bias and the total number of the first current sources 112 is K, the current amount I _total flowing through the pixel power supply line 125 is

It is represented by When the resistance value of the voltage drop resistor 153 is R, V _ddrs3 is _represented by the voltage drop due to the resistor.

It becomes. Therefore, the potential V _fdrst3 of the FD unit 106 when the FD unit 106 is reset is

It becomes.

で表される。 Next, when the transfer pulse φTX becomes “H” level, all the transfer transistors 102 to which the transfer pulse φTX is supplied are turned on, and electrons generated in the photodiodes 101 in the corresponding row are transferred to the FD unit 106. When the number of electrons generated in the photodiode 101 is N, the charge amount per electron is q, and the capacitance of the FD portion 106 is C, the potential V _fdsig3 of the FD portion 106 is

It is represented by

  The potential of the FD portion 106 is read out to the column signal line 111 by a source follower circuit including the reading transistor 104 and the first current source 112, and the FD portion 106 is reset to the potential of the pixel power supply line 125. A potential corresponding to the difference between the potential of the column signal line 111 and the potential of the column signal line 111 when electrons generated in the photodiode 101 are transferred to the FD unit 106 according to the amount of light irradiation is output from the CDS circuit 113. Is done.

  The output from the CDS circuit 113 of each column is sequentially read out to the horizontal signal line 121 for each column via the horizontal selection transistor 114 controlled by the horizontal selection circuit 123, amplified by the amplifier circuit 124, and output. .

を満たすパラメータに、電圧降下用抵抗１５３の抵抗値、第１の電流源１１２の電流値、第１の電流源１１２の数、及び読み出しトランジスタ１０４のしきい値電圧を設定することで、蓄積電子数が少ない場合でも、読み出しトランジスタ１０４を飽和領域で動作させ、リニアリティの劣化及び固定パターンノイズの増加を抑えることが可能となる。 In contrast to a general solid-state imaging device, the solid-state imaging device according to the second embodiment includes a voltage drop resistor 153 inserted in parallel with the voltage switching transistor 151 and turns off the voltage switching transistor 151 only when the FD unit 106 is reset. As a result, the potential of the pixel power line 125 when the FD unit 106 is reset is lowered. Accordingly, the reset potential of the FD portion 106 can be made lower than the drain potential of the read transistor 104 so that the read transistor 104 operates in the saturation region even when the number of electrons generated in the photodiode 101 is small. . Specifically, from Equation (16) and Equation (21),

By setting the resistance value of the voltage drop resistor 153, the current value of the first current source 112, the number of the first current sources 112, and the threshold voltage of the reading transistor 104 as parameters satisfying Even when the number is small, it is possible to operate the read transistor 104 in the saturation region and suppress deterioration in linearity and increase in fixed pattern noise.

  In general, in the MOS process, the voltage drop resistor 153 can be generated in a very small area, so that even when the number of stored electrons is small, it is possible to reduce the chip size while suppressing deterioration of linearity and increase of fixed pattern noise. It becomes.

  In the MOS process, the voltage drop resistor 153 can be generated in various ways, such as a resistance by a polycrystalline silicon wiring, a resistance by a metal wiring, a resistance by a transistor, and a diffusion resistance. The resistor 153 can obtain the same effect in any case, and its method is not specified.

(Third embodiment)
FIG. 7 is a diagram illustrating an overall configuration of a solid-state imaging apparatus according to the third embodiment of the present invention. In FIG. 7, the same components as those in FIG. Hereinafter, the difference from the first embodiment will be mainly described, and the other parts are the same as those of the first embodiment.

  The solid-state imaging device of this embodiment includes a plurality of unit cells 200 arranged in an array in the XY direction, a column signal line 111, a first current source 112, a CDS circuit 113, a horizontal selection transistor 114, Comparator 115, counter 116, horizontal signal line 121, vertical selection circuit 122, horizontal selection circuit 123, amplification circuit 124, pixel power supply line 125, switch unit 160, voltage source 162, voltage switching transistor 163, a RAMP wave generation circuit 300, and a clock generator 400.

  The unit cell 200 includes a photodiode 101, an FD unit 106 to which signal charges (electrons) generated in the photodiode 101 are transferred, and temporarily hold the signal charges generated in the photodiode 101. A transfer transistor 102 provided between the photodiode 101 and the FD unit 106 for transferring electrons from the photodiode 101 to the FD unit 106; a reset transistor 103 connected to the FD unit 106 for resetting the FD unit 106; , The gate is connected to the FD portion 106, and the read transistor 104 for reading a voltage signal corresponding to the potential of the FD portion 106 is included.

  The column signal lines 111 are provided corresponding to the columns of the unit cells 200, and are commonly connected to the read transistors 104 of the corresponding columns.

  The first current source 112 is connected to the column signal line 111.

  The CDS circuit 113 is connected to the column signal line 111. The CDS circuit 113 is provided for each column signal line 111 and outputs a signal corresponding to a potential difference at any two different timings in the corresponding column signal line 111.

  Comparator 115 is connected to CDS circuit 113 and RAMP wave generation circuit 300, and compares the output potential of CDS circuit 113 with the output potential of RAMP wave generation circuit 300.

  The counter 116 is connected to the comparator 115 and the clock generator 400.

  The comparator 115 and the counter 116 are provided for each column signal line 111, that is, for each CDS circuit 113, and constitute an AD conversion circuit that performs analog-digital conversion on the output signal of the corresponding CDS circuit 113.

  The horizontal selection transistor 114 is connected to the counter 116.

  The horizontal signal line 121 is commonly connected to the horizontal selection transistors 114 in each column.

  The vertical selection circuit 122 controls the transistor of the unit cell 200.

  The horizontal selection circuit 123 controls the horizontal selection transistor 114.

  The amplifier circuit 126 is connected to the horizontal signal line 121.

  The pixel power line 125 is commonly connected to the reset transistor 103 and the read transistor 104 of the unit cell 200. The pixel power supply line 125 supplies a power supply potential lower than the power supply potential when the signal voltage is output from the unit cell 200 to the column signal line 111 when the FD unit 106 is reset. The pixel power supply line 125 supplies three power supply potentials to one unit cell 200. In other words, the power supply unit configured by the pixel power supply line 125, the switch unit 160, the voltage source 162, and the voltage switching transistor 163 supplies three power supply potentials to one unit cell 200, and performs a signal output operation during a reset operation. A power supply potential (a power supply potential different from the ground potential) lower than the current power supply potential (a power supply potential different from the ground potential) is supplied to the unit cell 200 through the pixel power supply line 125.

  The voltage source 162 supplies a power supply potential different from the ground potential to the pixel power supply line 125.

  A plurality of switch units 160 are provided corresponding to the rows, and the pixel power supply line 125 and the voltage source 162 are short-circuited or disconnected. The switch unit 160 includes a first voltage source connection transistor 161 and a second voltage source connection transistor 164 controlled by different signal lines.

  The first voltage source connection transistor 161 and the second voltage source connection transistor 164 are switches provided between the voltage source 162 and the pixel power supply line 125.

  The voltage switching transistor 163 is inserted between the pixel power line 125 and the ground.

  Here, in order to explain the effect of the solid-state imaging device of the present embodiment, the second voltage source connection transistor 164 is not provided in the configuration of FIG. 7, and the solid-state imaging device is configured only by the first voltage source connection transistor 160. Is presented as a comparative example, and the solid-state imaging device of FIG. 7 is compared with the solid-state imaging device of the comparative example.

  FIG. 8 is a diagram illustrating an overall configuration of a solid-state imaging device of a comparative example. In FIG. 8, the same components as those in FIG. 7 are given the same reference numerals.

  The solid-state imaging device of this comparative example includes a plurality of unit cells 200 arranged in an array in the XY direction, a column signal line 111, a first current source 112, a CDS circuit 113, a horizontal selection transistor 114, Comparator 115, counter 116, horizontal signal line 121, vertical selection circuit 122, horizontal selection circuit 123, amplification circuit 124, pixel power supply line 125, switch unit 160, voltage source 162, voltage switching transistor 163, a RAMP wave generation circuit 300, and a clock generator 400.

  The unit cell 200 includes a photodiode 101, an FD unit 106 to which signal charges (electrons) generated in the photodiode 101 are transferred, and temporarily hold the signal charges generated in the photodiode 101. A transfer transistor 102 for transferring electrons from the 101 to the FD unit 106, a reset transistor 103 for resetting the FD unit 106, and a read transistor 104 for reading a voltage signal of the FD unit 106 are included.

  The column signal lines 111 are provided corresponding to the columns of the unit cells 200, and are commonly connected to the read transistors 104 of the corresponding columns.

  The first current source 112 is connected to the column signal line 111.

  The CDS circuit 113 is connected to the column signal line 11.

  The comparator 115 is connected to the CDS circuit 113 and the RAMP wave generation circuit 300, and compares the magnitude of the output of the CDS circuit 113 and the output potential of the RAMP wave generation circuit 300.

  The counter 116 is connected to the comparator 115 and the clock generator 400.

  The horizontal selection transistor 114 is connected to the counter 116.

  The horizontal signal line 121 is commonly connected to the horizontal selection transistors 114 in each column.

The vertical selection circuit 122 controls the transistor of the unit cell 200.
The horizontal selection circuit 123 controls the horizontal selection transistor 114.

  The amplifier circuit 126 is connected to the horizontal signal line 121.

  The pixel power line 125 is commonly connected to the reset transistor 103 and the read transistor 104 of the unit cell 200.

  The voltage source 162 supplies a power supply potential different from the ground potential to the pixel power supply line 125.

  A plurality of switch units 160 are provided corresponding to the rows, and the pixel power supply line 125 and the voltage source 162 are short-circuited or disconnected. The switch unit 160 includes only the first voltage source connection transistor 161.

  The transistor 163 is inserted between the pixel power line 125 and the ground.

  The solid-state imaging device having the configuration shown in FIG. 8 is widely used as a 1-cell 3-transistor MOS type image sensor excluding a selection transistor in order to increase the aperture ratio of the pixel portion for the purpose of improving the sensitivity of the pixel portion.

  FIG. 9 is an operation timing chart of the solid-state imaging device of FIG.

In FIG. 9, the horizontal axis represents time, and the vertical axis represents the potential of each signal. The reset pulse φRS represents a pulse signal for commonly controlling the reset transistors 103 in a predetermined row. The transfer pulse φTX represents a pulse signal for commonly controlling the transfer transistors 102 in a predetermined row. The potential V _fd represents the potential of the FD unit 106 of the predetermined unit cell 200, and the potential V _l represents the potential of the column signal line 111 connected to the predetermined unit cell 200. The power supply pulse φVDCEL4 represents a pulse signal for controlling the first voltage source connection transistor 161 and the transistor 163. The potentials V _ddpx , V _ddrd, and V _gnd are the potential of the pixel power supply line 125, the potential supplied by the voltage source 161, and the ground potential, respectively.

First, when the reset pulse φRS becomes “H” level, all the reset transistors 103 to which the reset pulse φRS is supplied are turned on, and the FD portion 106 in the corresponding row is reset to the potential V _ddpx of the pixel power supply line 125. .

  Next, when the transfer pulse φTX becomes “H” level, all the transfer transistors 102 to which the transfer pulse φTX is supplied are turned on, and electrons generated in the photodiodes 101 in the corresponding row are transferred to the FD unit 106.

  The potential of the FD portion 106 is read out to the column signal line 111 by a source follower circuit including the reading transistor 104 and the first current source 112, and the FD portion 106 is reset to the potential of the pixel power supply line 125. A potential corresponding to the difference between the potential of the column signal line 111 and the potential of the column signal line 111 when electrons accumulated according to the light irradiation amount are transferred to the FD unit 106 is output from the CDS circuit 113.

  The output from the CDS circuit 113 in each column is converted into a digital signal by the comparator 115 and the counter 116.

  Here, an example of the analog-digital conversion operation timing is shown in FIG.

10, the horizontal axis represents time, the vertical axis represents the potential of each signal, the potential V _CDS represents the output potential of the CDS circuit 113, the potential V _ramp represents the output signal of the RAMP wave generation circuit 300, and the clock V _clk represents the clock generator 400. The output pulse signal, count value _Dout , represents an output digital value from the counter 116.

In synchronization with the clock V _clk, the potential V _ramp rises linearly, at time t ₁₀ is the potential V _ramp becomes the potential V _CDS the same potential. When the output of the clock V _clk is started, the output of the comparator 115 is at the “L” level, but when the potential V _ramp and the potential V _CDS become the same potential, the output changes from the “L” level to the “H” level. When the output of the comparator 115 becomes “H” level, the counter 116 stops counting.

At this time, the count value D _out of the counter 116 outputs are clock number outputted from the output start of the clock V _clk to the comparator 115 is inverted, the count value in response to the output potential of the CDS circuit 113 is high D _out also increases. That is, the count value _Dout is a value obtained by digitally converting the output potential of the CDS circuit 113.

  The output from the counter 116 of each column is sequentially read out to the horizontal signal line 121 for each column via the horizontal selection transistor 114 controlled by the horizontal selection circuit 123, and is buffered and output by the amplifier circuit 126.

After the potential reading of the FD portion 106 is completed, the reset pulse φRS and the power supply pulse φVDCEL4 are set to the “H” level to set the FD portion 106 to the ground potential V _gnd so that all the read transistors 104 in a given row are turned off. Then, an arbitrary row is in a non-selected state.

  By sequentially performing this operation for each row, a signal of each pixel arranged in the XY direction is output, and two-dimensional image data is generated.

  Here, considering the operation region of the read transistor 104 in the MOS image sensor of FIG. 8, the reset potential of the FD portion 106 is equal to the drain voltage of the read transistor 104, and there is a possibility that the read transistor 104 operates in the linear region. Therefore, when the number of stored electrons is small, an increase in fixed pattern noise and deterioration of output linearity can occur.

  On the other hand, the solid-state imaging device of the present embodiment shown in FIG. 7 divides the voltage source connection transistor of the switch unit 160 into a first voltage source connection transistor 161 and a second voltage source connection transistor 164. , And controlled by power supply pulses φVDCEL4 and VDCEL5, respectively.

  FIG. 11 shows an operation timing chart of the solid-state imaging device of the present embodiment.

In FIG. 11, the horizontal axis represents time, and the vertical axis represents the potential of each signal. The reset pulse φRS represents a pulse signal for commonly controlling the reset transistors 103 in a predetermined row. The transfer pulse φTX represents a pulse signal for commonly controlling the transfer transistors 102 in a predetermined row. The potential V _fd represents the potential of the FD unit 106 of the predetermined unit cell 200, and the potential V _l represents the potential of the column signal line 111 of the column including an arbitrary unit cell 200. The power pulse φVDCEL4 represents a pulse signal for controlling the first voltage source connection transistor 161 and the transistor 163, and the power pulse φVDCEL5 represents a pulse signal for controlling the second voltage source connection transistor 164. The potentials V _ddpx , V _ddrd2 , V _gnd, and V _ddrs4 are the potential of the pixel power line 125, the potential of the pixel power line 125, the ground potential, and the power pulse φVDCEL 4 when the power pulses φVDCEL 4 and φVDCEL 5 are both “L” level. Is the potential of the pixel power supply line 125 when the power supply pulse φVDCEL5 is at the “H” level. The potentials V _fdrst4 and V _fdsig4 are the potential of the FD unit 106 when reset and the potential of the FD unit 106 when electrons generated in the photodiode 101 are transferred, respectively.

となる。従って、ＦＤ部１０６をリセットした時のＦＤ部１０６の電位Ｖ_fdrst4は

である。 First, when the reset pulse φRS becomes “H” level, all the reset transistors 103 connected to the reset pulse φRS are turned on, and the FD portion 106 of the corresponding row is reset to the potential of the pixel power supply line 125. At this time, since the power supply pulse φVDCEL5 is at the “H” level, the current flowing through the pixel power supply line 125 flows only through the first voltage source connection transistor 161. When the on-resistance value of the first voltage source connection transistor 161 is R _on1 , the current amount of the first current source 112 is I _bias , and the total number of the first current sources 112 is K, the potential V _ddrs4 is

It becomes. Therefore, the potential V _fdrst4 of the FD unit 106 when the FD unit 106 is reset is

It is.

で表される。 Next, when φTX becomes “H” level, all the transfer transistors 102 to which the transfer pulse φTX is supplied are turned on, and electrons generated in the photodiodes 101 in the corresponding row are transferred to the FD unit 106. When the number of accumulated electrons is N, the charge amount per electron is q, and the capacitance of the FD unit 106 is C, the potential V _fdsig4 of the FD unit 106 is

It is represented by

である。 Here, when the drain voltage of the reading transistor 104 is obtained, the power supply pulse φVDCEL5 becomes “L” level after the reset of the FD unit 106 is finished, so that the current flowing through the pixel power supply line 125 is the first voltage source connection transistor. 161 and the second voltage source connection transistor 164 flow. Therefore, when the on resistance value of the second voltage source connected transistors 164 and R _on2, potential V _Ddrd2 is

It is.

  The potential of the FD portion 106 is read out to the column signal line 111 by a source follower circuit including the reading transistor 104 and the first current source 112, and the FD portion 106 is reset to the potential of the pixel power supply line 125. A potential corresponding to the difference between the potential of the column signal line 111 and the potential of the column signal line 111 when electrons generated in the photodiode 101 are transferred to the FD unit 106 according to the amount of light irradiation is output from the CDS circuit 113. Is done.

  The output from the CDS circuit 113 in each column is converted into a digital signal by, for example, an analog-digital conversion method shown in FIG.

  The output from the counter 116 of each column is sequentially read out to the horizontal signal line 121 for each column via the horizontal selection transistor 114 controlled by the horizontal selection circuit 123, amplified by the amplification circuit 126, and output.

を満たすパラメータに、第１の電圧源接続トランジスタ１６１及び第２の電圧源接続トランジスタ１６４のｏｎ抵抗値、読み出しトランジスタ１０４のドレイン・ソース間電流及びしきい値電圧、並びに第１の電流源１１２の数を設定することで、フォトダイオード１０１での発生電子数が少ない場合でも、読み出しトランジスタ１０４を飽和領域で動作させ、リニアリティの劣化及び固定パターンノイズの増加を抑えることが可能となる。 In contrast to the solid-state imaging device as shown in FIG. 8, the solid-state imaging device according to the present embodiment divides the voltage source connection transistor and sets the resistance between the voltage source 162 and the pixel power supply line 125 only when the FD unit 106 is reset. By increasing the value, the potential of the pixel power supply line 125 when the FD unit 106 is reset is lowered. Accordingly, the reset potential of the FD portion 106 can be made lower than the drain potential of the read transistor 104 so that the read transistor 104 operates in the saturation region even when the number of electrons generated in the photodiode 101 is small. It was. Specifically, from Equation (16), Equation (26) and Equation (27),

The on-resistance values of the first voltage source connection transistor 161 and the second voltage source connection transistor 164, the drain-source current and threshold voltage of the read transistor 104, and the first current source 112 By setting the number, even when the number of electrons generated in the photodiode 101 is small, the read transistor 104 can be operated in a saturation region, and deterioration of linearity and increase in fixed pattern noise can be suppressed.

  The solid-state imaging device of the present embodiment is obtained by dividing the voltage source connection switch from the solid-state imaging device of FIG. 8, and can suppress degradation of linearity and increase of fixed pattern noise without increasing the chip size. It becomes.

(Fourth embodiment)
FIG. 12 is a diagram illustrating an overall configuration of an imaging apparatus (camera system) according to a fourth embodiment of the present invention.

  The imaging apparatus according to the present embodiment is roughly composed of a solid-state imaging apparatus 200, an optical system 240, a DSP (Digital Signal Processor) 250, an image display device 280 such as a liquid crystal screen, and an image memory 290.

  The optical system 240 includes a lens 241 that collects light from the subject and forms an image on the pixel array of the solid-state imaging device 200.

  The solid-state imaging device 200 is the solid-state imaging device described in the first to third embodiments of the present invention. The solid-state imaging device 200 selects an imaging region 210 in which unit cells including a photosensitive element such as a photodiode and a MOS transistor are arranged in a two-dimensional array, and unit cells of the imaging region 210 are selected in units of rows. A vertical selection circuit 220 that controls reset and signal readout, and a timing control unit 230 that supplies a drive pulse to the vertical selection circuit 220 are provided.

  The solid-state imaging device 200 is provided in each column, and an A / D conversion circuit that performs A / D conversion on the pixel signal read from the imaging region 210, and a column digital memory that holds the A / D converted pixel signal. And a horizontal scanning unit that drives reading of the digital pixel signal that is selected and held in each column of the column digital memory.

  The DSP 250 includes a camera system control unit 260 and an image processing circuit 270.

  The image processing circuit 270 receives the digital pixel signal output from the solid-state imaging device 200 and performs processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance necessary for camera signal processing. Further, the image processing circuit 270 performs conversion into a compression format such as JPEG, recording in the image memory 290, and display signal processing to the image display device 280.

  The camera system control unit 260 controls the optical system 240, the solid-state imaging device 200, and the image processing circuit 270 in accordance with various settings designated by a user I / F (not shown), and integrates the entire operation of the imaging device. Such as a microcomputer. The user I / F receives, for example, a zoom magnification change and a real-time instruction such as a release button, and the camera system control unit 260 changes the zoom magnification of the lens 241, travel of the curtain shutter, and reset scanning of the solid-state imaging device 200. Control.

  As described above, the solid-state imaging device of the present invention has been described based on the embodiment. However, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.

  For example, in the solid-state imaging device of the third embodiment, when one voltage source is connected to the pixel power supply line via two voltage source connection transistors connected in parallel, and two power supply voltages are supplied to the pixel power supply line. did. However, as in the configuration of FIG. 1, two power source switching transistors are provided corresponding to two voltage sources that supply different power source potentials, and the voltage source is connected to the pixel power source line via the corresponding power source switching transistor. Two power supply voltages may be supplied to the pixel power supply line by connection. Similarly, as in the configuration of FIG. 5, one voltage source is connected to the pixel power supply line via the voltage switching transistor, and further a voltage drop resistor is connected in parallel to the voltage switching transistor. A power supply voltage may be supplied.

  In the solid-state imaging device of the above embodiment, the power supply unit supplies three power supply potentials to one unit cell. However, if the reset potential of the FD portion can be made lower than the drain potential of the read transistor so that the read transistor operates in the saturation region even when the number of accumulated electrons in the photodiode is small, the power supply potential is limited to three power supply potentials. Instead, at least three power supply potentials, that is, four or more power supply potentials may be supplied to the unit cell.

  The present invention can be used for a solid-state imaging device, and in particular, for a MOS solid-state imaging device.

100, 200 Unit cell 101 Photodiode 102 Transfer transistor 103 Reset transistor 104 Read transistor 105 Select transistor 106 FD section 111 Column signal line 112 First current source 113 CDS circuit 114 Horizontal select transistor 115 Comparator 116 Counter 121 Horizontal signal line 122 220 vertical selection circuit 123 horizontal selection circuit 124 amplifier circuit 125 pixel power supply line 126 voltage source 131 first power switching transistor 132 first voltage source 133 second power switching transistor 134 second voltage source 141 second current source 142 transistor 151 voltage switching transistor 152, 162 voltage source 153 voltage drop resistor 160 switch unit 161 first voltage source connection transistor 1 3 voltage switching transistor 164 the second voltage source connected transistor 200 solid-state imaging device 210 imaging region 230 timing control unit 240 an optical system 241 lens 250 DSP
260 Camera System Control Unit 270 Image Processing Circuit 280 Image Display Device 290 Image Memory 300 RAMP Wave Generation Circuit 400 Clock Generator

Claims (11)

A plurality of unit cells arranged in an array; and
Column signal lines provided corresponding to the columns of the unit cells and connected in common to the unit cells of the corresponding columns;
A current source connected to the column signal line;
A power supply unit for supplying a power supply potential to the unit cell,
The unit cell is
A photodiode;
An FD (floating diffusion) section for temporarily holding signal charges generated in the photodiode;
A transfer transistor provided between the photodiode and the FD unit, for transferring charges from the photodiode to the FD unit;
A reset transistor connected to the FD unit for resetting the potential of the FD unit;
A read transistor having a gate connected to the FD unit and reading a signal voltage corresponding to the potential of the FD unit;
A selection transistor that is provided between the read transistor and the column signal line and outputs a signal voltage from the unit cell to the column signal line;
The power supply unit includes a pixel power supply line commonly connected to the reset transistor and the readout transistor, and outputs the signal voltage from the unit cell to the column signal line when resetting the FD unit. A solid-state imaging device that supplies a power source potential lower than the power source potential via the pixel power source line. The solid-state imaging device further includes:
The solid-state imaging device according to claim 1, wherein a CDS circuit that outputs a signal corresponding to a potential difference at any two different timings in the column signal line is provided for each column signal line. The power supply unit further includes:
A first power source and a second power source having different power source potentials for supplying a power source potential to the pixel power source line;
A first switch provided between the first power source and the power line;
The solid-state imaging device according to claim 1, further comprising: a second switch provided between the second power supply and the power supply line. The power supply unit further includes:
A power supply for supplying a power supply potential to the pixel power supply line;
A switch provided between the power source and the power line;
The solid-state imaging device according to claim 1, further comprising: a resistor provided in parallel with the switch between the pixel power supply line and the power supply. The solid-state imaging device further includes:
The solid-state imaging device according to claim 2, wherein an AD conversion circuit for analog-digital conversion of an output signal of the CDS circuit is provided for each CDS circuit. A plurality of unit cells arranged in an array; and
Column signal lines provided corresponding to the columns of the unit cells and connected in common to the unit cells of the corresponding columns;
A current source connected to the column signal line;
A power supply unit for supplying a power supply potential to the unit cell,
The unit cell is
A photodiode;
An FD (floating diffusion) section for temporarily holding signal charges generated in the photodiode;
A transfer transistor provided between the photodiode and the FD unit, for transferring charges from the photodiode to the FD unit;
A reset transistor connected to the FD unit for resetting the potential of the FD unit;
A gate connected to the FD portion, and a read transistor for reading a signal voltage corresponding to the potential of the FD portion;
The power supply unit includes a pixel power line commonly connected to the reset transistor and the readout transistor, and supplies at least three power supply potentials to one unit cell.
The power supply unit supplies, via the pixel power line, a power supply potential lower than a power supply potential when the signal voltage is output from the unit cell to the column signal line when the FD unit is reset. Imaging device. The solid-state imaging device further includes:
The solid-state imaging device according to claim 6, wherein a CDS circuit that outputs a signal corresponding to a potential difference at any two different timings in the column signal line is provided for each column signal line. The power supply unit further includes:
A first power source and a second power source having different power source potentials for supplying a power source potential to the pixel power source line;
A first switch provided between the first power source and the power line;
The solid-state imaging device according to claim 6, further comprising a second switch provided between the second power supply and the power supply line. The power supply unit further includes:
A power supply for supplying a power supply potential to the pixel power supply line;
A switch provided between the power source and the power line;
The solid-state imaging device according to claim 6, further comprising a resistor provided in parallel with the switch between the pixel power supply line and the power supply. The solid-state imaging device further includes:
The solid-state imaging device according to claim 7, wherein an AD conversion circuit for analog-digital conversion of an output signal of the CDS circuit is provided for each CDS circuit. A camera system comprising the solid-state imaging device according to claim 1.

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