JP2011040422A - Semiconductor substrate, semiconductor device and method of manufacturing the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate which can reduce an interface state by terminating a dangling bond generated at the interface of a semiconductor layer with fluorine and can efficiently introduce the fluorine only to an active region even in the process of a low thermal history. <P>SOLUTION: The semiconductor substrate includes an insulating layer 9 comprising a fluorine diffusion preventing film 6 and a fluorine-containing silicon oxide film 7 formed on the fluorine diffusion preventing film 6, and a semiconductor layer 8 formed on the insulating layer 9. The semiconductor layer 8 and the fluorine-containing silicon oxide film 7 are in contact. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing the semiconductor device.

  In general, in a MOS-FET type semiconductor device, a dangling bond of silicon existing at the interface between a silicon semiconductor layer and a gate insulating film acts as a trap, so that a leakage current increases or a threshold voltage of the FET varies. It is known that In order to suppress this, it is widely performed to terminate the dangling bonds with hydrogen (H) or fluorine (F) to inactivate the traps.

In the case of using hydrogen, a method is adopted in which hydrogen is introduced into the interface between silicon and the gate insulating film by performing a heat treatment on the silicon wafer at about 400 ° C. in a hydrogen atmosphere.
However, since the bond energy of Si—H is relatively low, there is a problem that hydrogen is desorbed over time due to stress such as hot carriers and heat during transistor operation, and dangling bonds are generated again.

  Therefore, the Si-F bond has a stronger bonding force than the Si-H bond, and therefore, as a substitute for hydrogen, fluorine has attracted attention as a means for reducing the interface state. (Patent Document 1 to Patent Document 4).

JP-A-8-316465 JP-A-7-147398 JP-A-3-149821 JP-A-2005-116607

  Incidentally, the methods described in Patent Documents 1 and 2 are methods of implanting fluorine ions into a silicon substrate. Therefore, in a process where the miniaturization has progressed and the thermal history is low, damage caused by fluorine ions cannot be sufficiently recovered, a defect occurs in the silicon substrate, and a device such as a DRAM that requires low leakage current is required. There was inconvenience that it was not suitable.

  Patent Document 3 describes a method in which fluorine is contained in an oxide film embedded in a silicon substrate. However, since fluorine diffuses to the back side of the silicon substrate, a low thermal history is obtained. In the process, there was a problem that the introduction efficiency of fluorine was poor.

Patent Document 4 discloses a method for recovering crystallinity by annealing in an oxygen atmosphere after fluorine ions are implanted in advance into a semiconductor layer of an SOI (Silicon On Insulator) substrate.
However, since the oxide film is formed on the surface of the semiconductor layer by performing the annealing treatment in the oxygen atmosphere, it is necessary to remove the oxide film and expose the surface of the semiconductor layer before forming the gate insulating film. At this time, fluorine terminated at the surface portion of the semiconductor layer by the annealing treatment is damaged, and the effect is reduced.

Therefore, the present invention employs the following configuration.
The semiconductor substrate of the present invention includes a fluorine diffusion preventing film, an insulating layer made of a silicon oxide film containing fluorine formed on the fluorine diffusion preventing film, and a semiconductor layer formed on the insulating layer, The semiconductor layer and the silicon oxide film containing fluorine are in contact with each other.

In the present invention, a silicon oxide film containing fluorine is provided under the semiconductor layer. As a result, fluorine contained in the silicon oxide film is introduced into the semiconductor layer and becomes an end of dangling bonds generated at the interface with the gate insulating film, so that the interface state can be reduced.
Further, since the fluorine diffusion preventing film is provided under the silicon oxide film, it is possible to suppress the diffusion of fluorine from the silicon oxide film to the lower layer side (opposite side of the semiconductor layer). Thereby, fluorine can be efficiently introduced only into the active region even in a process with a low thermal history.

FIG. 1 is a plan view showing a part of an example of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a semiconductor substrate according to an embodiment of the present invention. FIG. 3 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 8 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 11 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 12 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[First Embodiment]
Hereinafter, a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.
First, a memory cell of a DRAM manufactured using the semiconductor device of this embodiment will be described. FIG. 1 is a plan view schematically showing a layout of a MOS-FET (memory cell transistor) in a memory cell region of a DRAM.

  As shown in FIG. 1, in the memory cell 1 of the DRAM device of this embodiment, a plurality of elongated strip-like active regions 2 are arranged in a diagonally upward right direction with predetermined intervals. The active region 2 is formed on the surface of the semiconductor substrate, and is formed by being insulated and isolated by an element isolation region.

A gate electrode 3 functioning as a word line is formed in the longitudinal (Y) direction of FIG. 1, and a planar type MOS-FET is formed at the intersection of the gate electrode 3 and the active region 2. .
In FIG. 1, bit lines and capacitor elements are omitted.

<Semiconductor substrate>
Next, the semiconductor substrate of this embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view taken along the line AA ′ in FIG.
As shown in FIG. 2, the semiconductor substrate 4 includes a semiconductor layer 5, a fluorine diffusion preventing film 6 formed on the semiconductor layer 5, and a silicon oxide film 7 (SiO ₂ ) formed on the fluorine diffusion preventing film 6. And a semiconductor layer 8 formed on the silicon oxide film 7. That is, the semiconductor substrate 4 is a substrate having a structure in which the fluorine diffusion preventing film 6 and the silicon oxide film 7 are inserted between the semiconductor layer 5 and the semiconductor layer 8.

  As the semiconductor layer 5, for example, a silicon substrate can be used, and a thin silicon oxide film (not shown) of about 3 to 10 nm, for example, may be formed on the surface 5 a on the side where the fluorine diffusion preventing film 6 is formed. Absent.

  As the fluorine diffusion preventing film 6, any film can be used as long as it has a function of preventing fluorine diffusion. For example, a silicon nitride film or a silicon oxynitride film is preferably used. The film thickness of the fluorine diffusion preventing film 6 is preferably about 20 nm.

The silicon oxide film 7 is an FSG (Fluorinated Silicate Glass) film containing fluorine, and it is preferable to use a film doped with fluorine of 1 × 10 ²⁰ / cm ³ or more. The film thickness of the silicon oxide film 7 is preferably about 100 nm.
The insulating layer 9 is formed by the fluorine diffusion preventing film 6 and the silicon oxide film 7 containing fluorine.

For example, a silicon substrate can be used as the semiconductor layer 8 and is formed in contact with the silicon oxide film 7.
In the semiconductor layer 8, a thin silicon oxide film (not shown) of about 3 to 10 nm, for example, may be formed on the surface 8b on the side in contact with the silicon oxide film 7.

  The semiconductor substrate 4 of the present embodiment configured as described above has a configuration in which a silicon oxide film 7 containing fluorine is provided below the semiconductor layer 8. As a result, fluorine contained in the silicon oxide film 7 is introduced into the semiconductor layer 8 and terminates at a dangling bond generated at the interface 8a of the semiconductor layer 8, so that the interface state can be reduced. Further, since the fluorine diffusion preventing film 6 is provided under the silicon oxide film 7, it is possible to suppress the diffusion of fluorine from the silicon oxide film 7 to the lower layer side (opposite side of the semiconductor layer 8). Thereby, fluorine can be efficiently introduced only into the active region even in a process with a low thermal history.

<Semiconductor device>
Next, a semiconductor device using the semiconductor substrate of this embodiment will be described.
As shown in FIG. 11, the semiconductor device 11 of this embodiment includes a semiconductor substrate 4, an element isolation region 12 provided on the semiconductor substrate 4, a gate insulating film 13 formed on the semiconductor substrate 4, and gate insulation. A gate electrode 14 provided on the film 13 and a source region and a drain region provided at positions that are self-aligned with the gate electrode 14 in the semiconductor layer 8 of the semiconductor substrate 4 are provided. .

  A contact plug 16 is formed on each source region 15 and drain region 15, and a bit wiring 17, a capacitor element 18, an upper metal wiring layer 19, and a surface protection film are connected to the contact plug 16. 20 is formed.

  Since the semiconductor device 11 of the present embodiment is formed using the semiconductor substrate 4 described above, the interface state of the semiconductor layer 8 can be reduced, and the process can be efficiently performed only in the active region even in a low thermal history process. Fluorine can be introduced.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of this embodiment will be described.
First, as shown in FIG. 2, a fluorine diffusion preventing film 6 is formed on the semiconductor layer 5, and a silicon oxide film 7 containing fluorine is formed on the fluorine diffusion preventing film 6. As the semiconductor layer 5, for example, a P-type silicon substrate can be used, and a silicon oxide film having a thickness of about 3 to 10 nm (not shown) may be formed on the surface 5 a by a thermal oxidation method. .

As the fluorine diffusion preventing film 6, for example, a silicon nitride film (Si ₃ N ₄ ) can be used, and the film thickness is preferably 10 to 50 nm. The film thickness of the fluorine diffusion preventing film 6 may be set in a range in which the effect of suppressing the diffusion of fluorine can be obtained according to the thermal history applied in the device forming process, and may be a film thickness smaller than 10 nm. .
Further, as a method of forming a silicon nitride film as the fluorine diffusion preventing film 6 on the semiconductor layer 5, it is preferable to use the LP-CVD method.

The silicon oxide film 7 is preferably formed to a thickness of about 100 nm by, for example, a CVD method. As the silicon oxide film 7, for example, an FSG film (Fluorinated Silicate Glass film) doped with fluorine of 1 × 10 ²⁰ / cm ³ or more is preferably used. Note that fluorine doping may be performed by adding, for example, SiF ₄ to SiH ₄ and O ₂ as material gases when forming a film by a CVD method. Further, F ions may be implanted into the deposited silicon oxide film 7 with an energy of 30 keV and a dose of about 5 × 10 ¹⁶ / cm ² , for example.
Further, the fluorine diffusion preventing film 6 and the silicon oxide film 7 form an insulating layer 9.

Thereafter, another semiconductor layer 8 is prepared, and the surface 8b and the surface 7a of the silicon oxide film 7 are bonded using a well-known wafer bonding technique to form one wafer. The semiconductor layer 8 may have a thin silicon oxide film formed on the surface 8b by, for example, a thermal oxidation method (not shown).
After bonding, the interface 8a of the semiconductor layer 8 is polished, and the semiconductor substrate 4 is formed by adjusting the film thickness so that the film thickness is suitable for device formation. The semiconductor substrate 4 thus formed is used as a device formation region.

  Next, as shown in FIG. 3, a silicon oxide film 21 having a thickness of about 10 nm is formed using, for example, a thermal oxidation method. Thereafter, a silicon nitride film 22 having a thickness of about 150 nm is deposited by using, for example, LP-CVD, and the silicon nitride film 22 and the silicon oxide film 21 are patterned by using a well-known lithography technique and dry etching technique.

  Next, as shown in FIG. 4, using the silicon nitride film 22 as a mask, the semiconductor layer 8 is etched by about 200 nm, for example, to form a trench 23 for element isolation using an STI (Shallow Trench Isolation) structure.

  Next, as shown in FIG. 5, a silicon oxide film 24 of, eg, about 400 nm is deposited on the semiconductor layer 8 by HDP-CVD (High Density Plasma). Thereafter, the deposited silicon oxide film 24 is polished and removed by CMP (Chemical Mechanical Polishing) using the silicon nitride film 22 as a stopper, thereby forming the STI buried oxide film 12.

  Thereafter, the silicon nitride film 22 is removed by wet etching using a chemical solution such as hot phosphoric acid, and the silicon oxide film 21 is removed by wet etching using a chemical solution such as hydrofluoric acid. The interface 8a of the semiconductor layer 8 is exposed.

Next, as shown in FIG. 6, a gate insulating film 13 having a thickness of, for example, about 6 nm is formed on the semiconductor layer 8. As the gate insulating film 13, it is preferable to use a silicon oxide film.
Further, when forming the gate insulating film 13, it is preferable to use an ISSG (In-Situ Steam Generation) oxidation method. By using the ISSG oxidation method, it is possible to suppress the generation of stress due to the diffusion of the oxidized species as compared with thermal oxidation using a normal heating furnace, and therefore, leakage at the end of the STI buried oxide film 12 or the like. An effect of reducing current can be obtained.

Thereafter, a polysilicon film 31 having a thickness of about 80 nm doped with, for example, phosphorus at a concentration of about 1 × 10 ²⁰ / cm ^{3 is} formed on the gate insulating film 13. Next, a metal film 32 in which a tungsten (W) film having a thickness of about 70 nm is stacked on a polysilicon film 31 on, for example, a tungsten nitride (WN) having a thickness of about 5 nm is formed.

  Thereafter, a silicon nitride film 33 having a thickness of about 140 nm is deposited by, for example, LP-CVD. Then, the silicon nitride film 33 is patterned using a known lithography technique and dry etching technique.

  Next, as shown in FIG. 7, the gate electrode 14 composed of the metal film 32 and the polysilicon film 31 is formed by performing, for example, anisotropic dry etching using the silicon nitride film 33 as a mask.

Next, as shown in FIG. 8, for example, phosphorus with a dose of about 1 × 10 ¹³ / cm ² is ion-implanted at an energy of 30 keV, and heat treatment is performed at 900 ° C. for 10 seconds in an inert gas such as nitrogen. Thereby, the source region 15 and the drain region 15 are formed. Thereafter, for example, the silicon nitride film 34 having a thickness of about 10 nm deposited by the LP-CVD method is etched back by normal anisotropic dry etching, so that the sidewall silicon nitride film 35 covering the side wall of the gate electrode 14 is formed. Form.

  Next, as shown in FIG. 9, a BPSG film is deposited with a film thickness of about 400 nm by, for example, CVD as an interlayer insulating film 36 with a wiring layer formed as an upper layer, and then a reflow process at 750 ° C. for 30 minutes. I do. Note that after the reflow treatment, the surface 36a of the interlayer insulating film 36 may be further planarized by CMP.

Next, as shown in FIG. 10, the contact hole 41 is formed by using, for example, a well-known lithography technique and dry etching technique. Thereafter, polysilicon 42 is deposited so as to fill the contact hole 41, and the polysilicon deposited on the interlayer insulating film 36 is polished and removed by CMP to form a contact plug 43. As the polysilicon 42, for example, phosphorus doped with a concentration of about 1 × 10 ²⁰ / cm ³ may be used, and may be deposited in the contact hole 41 by the LP-CVD method.

  Next, as shown in FIG. 11, a bit wiring 17, a capacitor element 18, an upper metal wiring layer 19, a surface protective film 20, and the like are formed so as to be connected to the contact plug 16. The semiconductor device 11 used for the DRAM memory cell is completed through the above steps.

In the present embodiment, fluorine (F) is diffused from the silicon oxide film 7 containing fluorine by heat treatment applied during the manufacturing process, and dangling bonds existing at the interface 8a of the semiconductor layer 8 with the gate insulating film 13 are formed. Terminated. For this reason, it becomes possible to suppress the characteristic fluctuation resulting from the leakage current of the MOS-FET and the trap.
Further, in this embodiment, since the fluorine diffusion preventing film 6 is provided, in order to prevent fluorine from diffusing from the silicon oxide film 7 to the lower layer side (opposite side of the semiconductor layer 8), even in the process of low thermal history. Fluorine can be introduced efficiently.

[Second Embodiment]
Next, a method for manufacturing the semiconductor device of the second embodiment will be described. The present embodiment is a modification of the first embodiment, and differs from the first embodiment only in the method of manufacturing the semiconductor substrate 4, and the description of the same parts will be omitted below.

In the first embodiment, the fluorine diffusion preventing film 6 and the silicon oxide film 7 are sequentially formed on the semiconductor layer 5. However, in this embodiment, the silicon oxide film 7 is formed on the semiconductor layer 5, and N By performing heat treatment in a ₂ O atmosphere, a fluorine diffusion preventing film 6 is formed at the interface between the semiconductor layer 5 and the silicon oxide film 7.

Specifically, first, a silicon oxide film 7 doped with fluorine of 1 × 10 ²⁰ / cm ³ or more is formed on the semiconductor layer 5 by, eg, CVD.
Thereafter, heat treatment is performed at 950 ° C. for 20 minutes in an N ₂ O atmosphere. By this step, a silicon oxynitride film functioning as the fluorine diffusion preventing film 6 is formed at the interface between the semiconductor layer 5 and the silicon oxide film 7.
Through the above steps, the fluorine diffusion preventing film 6 and the silicon oxide film 7 are laminated on the semiconductor layer 5, and the subsequent steps are the same as those in the first embodiment.

  Also in this embodiment, since the fluorine diffusion preventing film 6, the silicon oxide film 7, and the semiconductor layer 8 are laminated, as in the first embodiment, the interface state of the semiconductor layer 8 can be reduced. Even in a process with a low heat history, fluorine can be efficiently introduced only into the active region. In addition, since the step of forming the fluorine diffusion preventing film can be omitted, an effect of increasing the yield can be obtained.

As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention can be variously changed in the range which is not limited to the said embodiment and does not deviate from the summary.
For example, in the above embodiment, the planar type MOS-FET has been described. However, as shown in FIG. 12, it may be a MOS-FET having a groove type gate electrode.

  In that case, after performing the same process as the above embodiment until the formation of the element isolation shown in FIG. 5, the silicon nitride film and the silicon oxide film are removed. After that, as shown in FIG. 12, the silicon substrate in the region where the trench gate electrode is to be formed is removed by etching, and a trench pattern (gate trench) 51 for the gate electrode is formed. Next, a polysilicon film 53 doped with an impurity such as phosphorus and a metal film 54 such as tungsten are deposited so as to fill the groove pattern 51 through the gate insulating film 52, and patterned to form a groove-type gate electrode. 55 is formed.

  Thereafter, impurities such as phosphorus are introduced by an ion implantation method, and annealing is performed in an inert gas such as nitrogen to form the source region 56 and the drain region 56. Thereafter, in the same manner as in the above embodiment, an interlayer insulating film, a source region, a drain region 56, and a gate electrode 56 are formed, and contact plugs, wiring layers, and the like connected to each other are formed. -The FET is completed.

  As described above, even in the case of forming the MOS-FET having the groove-type gate electrode 55, fluorine (F) diffuses from the silicon oxide film 7 containing fluorine by the heat treatment applied during the manufacturing process, and the gate insulation. Dangling bonds existing at the interface 8a of the semiconductor layer 8 with the film 52 are terminated. For this reason, it becomes possible to suppress the characteristic fluctuation resulting from the leakage current of the MOS-FET and the trap. In addition, since the fluorine diffusion preventing film 6 is provided, fluorine is efficiently introduced even in a low heat history process in order to prevent fluorine from diffusing from the silicon oxide film 7 to the lower layer side (opposite the semiconductor layer 8). be able to.

  In the above embodiment, the application to the DRAM device has been described. However, this is an example, and the application to the DRAM device is not limited. The present invention can be applied to any semiconductor element including a MOS-FET. The material of the semiconductor layer 8 (semiconductor substrate to be bonded) provided on the silicon oxide film 7 can be applied to SiGe, SiC, or the like in addition to pure Si. In addition to the silicon nitride film, a silicon oxynitride film (SiON) may be used as the fluorine diffusion preventing film 6.

  Since the present invention relates to a method for manufacturing a semiconductor device, it can be widely used in the manufacturing industry for manufacturing semiconductor devices.

  DESCRIPTION OF SYMBOLS 4 ... Semiconductor substrate, 5, 8 ... Semiconductor layer, 6 ... Fluorine diffusion prevention film, 7 ... Silicon oxide film, 9 ... Insulating layer, 13, 52 ... Gate insulating film, 14, 55 ... gate electrode, 15, 56 ... source region and drain region, 51 ... gate trench

Claims (10)

A fluorine diffusion preventing film and an insulating layer made of a silicon oxide film containing fluorine formed on the fluorine diffusion preventing film;
A semiconductor layer formed on the insulating layer,
A semiconductor substrate, wherein the semiconductor layer and the silicon oxide film containing fluorine are in contact with each other. A fluorine diffusion preventing film and an insulating layer made of a silicon oxide film containing fluorine formed on the fluorine diffusion preventing film;
A semiconductor layer formed on the insulating layer;
A gate insulating film formed on the semiconductor layer;
A gate electrode provided on the gate insulating film,
A semiconductor device, wherein the semiconductor layer and the silicon oxide film containing fluorine are in contact with each other.   A gate trench is provided in the semiconductor layer formed on the insulating layer, the gate insulating film is provided in the gate trench, and the gate electrode is provided on the gate insulating film. The semiconductor device according to claim 2. Forming a silicon oxide film containing fluorine on the fluorine diffusion preventing film;
Forming a semiconductor layer on the silicon oxide film;
Forming a gate insulating film on the semiconductor layer;
And a step of forming a gate electrode on the gate insulating film.   The method of manufacturing a semiconductor device according to claim 4, wherein an ISSG oxidation method is used when forming the gate insulating film on the semiconductor layer.   The semiconductor layer formed on the silicon oxide film is provided with a gate trench, the gate insulating film is formed in the gate trench, and the gate electrode is formed on the gate insulating film. A method for manufacturing a semiconductor device according to claim 4 or 5.   7. The method of manufacturing a semiconductor device according to claim 4, wherein a silicon nitride film or a silicon oxynitride film is formed as the fluorine diffusion preventing film. Forming a silicon oxide film on the first semiconductor layer;
Performing a heat treatment in a nitrogen oxide atmosphere to form a fluorine diffusion preventing film at an interface between the semiconductor layer and the silicon oxide film; and
Forming a second semiconductor layer on the silicon oxide film;
And a step of forming a gate electrode on the gate insulating film.   9. The method of manufacturing a semiconductor device according to claim 8, wherein an ISSG oxidation method is used when the gate insulating film is formed on the second semiconductor layer.   A gate trench is provided in the second semiconductor layer formed on the silicon oxide film, the gate insulating film is formed in the gate trench, and the gate electrode is formed on the gate insulating film. A manufacturing method of a semiconductor device according to claim 8 or 9.

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