+

JP2008060091A - Variable resistance element - Google Patents

Variable resistance element Download PDF

Info

Publication number
JP2008060091A
JP2008060091A JP2005007379A JP2005007379A JP2008060091A JP 2008060091 A JP2008060091 A JP 2008060091A JP 2005007379 A JP2005007379 A JP 2005007379A JP 2005007379 A JP2005007379 A JP 2005007379A JP 2008060091 A JP2008060091 A JP 2008060091A
Authority
JP
Japan
Prior art keywords
resistance
layer
resistance change
lower electrode
upper electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005007379A
Other languages
Japanese (ja)
Inventor
Akihiro Sakai
章裕 酒井
Hideaki Adachi
秀明 足立
Akihiro Odakawa
明弘 小田川
Tsutomu Sugano
勉 菅野
Yasunari Sugita
康成 杉田
Seiji Onaka
清司 大仲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2005007379A priority Critical patent/JP2008060091A/en
Priority to PCT/JP2006/300142 priority patent/WO2006075574A1/en
Publication of JP2008060091A publication Critical patent/JP2008060091A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/021Formation of switching materials, e.g. deposition of layers
    • H10N70/026Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/041Modification of switching materials after formation, e.g. doping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/821Device geometry
    • H10N70/826Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/883Oxides or nitrides
    • H10N70/8836Complex metal oxides, e.g. perovskites, spinels

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

【課題】 200℃でも安定した動作を示す抵抗変化素子を提供すること。
【解決手段】 プラセオジウム(Pr)、カルシウム(Ca)、マンガン(Mn)を含む酸化物よりなる抵抗変化層(13)に電気的に接続された上部電極(14)と下部電極(12)とを備え、前記上部電極(14)と前記下部電極(13)との間に電気パルスを印加して前記抵抗変化層(13)の抵抗を変化させる抵抗変化素子であって、
前記抵抗変化層(13)と前記上部電極(14)および前記下部電極(12)の少なくとも一方との間に酸素欠損層(25)を有する抵抗変化素子。
【選択図】図2
PROBLEM TO BE SOLVED: To provide a resistance change element which shows stable operation even at 200 ° C.
An upper electrode (14) and a lower electrode (12) electrically connected to a resistance change layer (13) made of an oxide containing praseodymium (Pr), calcium (Ca), and manganese (Mn) are provided. A resistance change element that changes the resistance of the resistance change layer (13) by applying an electric pulse between the upper electrode (14) and the lower electrode (13),
A variable resistance element having an oxygen deficient layer (25) between the variable resistance layer (13) and at least one of the upper electrode (14) and the lower electrode (12).
[Selection] Figure 2

Description

本発明は不揮発メモリ等に使用される抵抗変化素子に関する。   The present invention relates to a resistance change element used in a nonvolatile memory or the like.

現在の不揮発メモリはフラッシュメモリに代表され、多くの電子機器に応用されている。しかし、フラッシュメモリは書き込み・消去速度が遅い、書き込み電圧が大きいなどの課題点を持つ。   The current non-volatile memory is represented by flash memory and is applied to many electronic devices. However, flash memory has problems such as a slow write / erase speed and a high write voltage.

フラッシュメモリに限らず従来のメモリは電荷容量Cの変化によりスイッチ動作するものが主流である。しかしながら、情報携帯端末の普及、さらに電子部品価格のデフレーション化に影響を受ける形で、これら機能素子の微細化への要求が高まってきている。   A conventional memory is not limited to a flash memory, and a memory that performs a switching operation by changing a charge capacity C is mainly used. However, there is an increasing demand for miniaturization of these functional elements because of the influence of the spread of portable information terminals and the deflation of electronic component prices.

従来の電荷蓄積型のメモリでは、電荷容量Cの低下を招くことになり、それを回避するために、様々なプロセスの工夫が検討されているが、将来的な技術的破綻が懸念されている。そこで現在、これらの欠点を解決する次世代不揮発メモリの開発が急務とされている。   In the conventional charge storage type memory, the charge capacity C is reduced. In order to avoid this, various devices have been studied. However, there are concerns about future technical failures. . Therefore, it is urgently required to develop next-generation nonvolatile memory that solves these drawbacks.

最近Pr0.7Ca0.3MnO3なる化学式で表されるぺロブスカイト酸化物材料を上部電極及び下部電極で挟んだ構成である図1を用いて、上部電極14と下部電極12との間に、電流あるいは電圧を印加することによってこれらの電極によって挟まれた前記Pr0.7Ca0.3MnO313の抵抗値が常温で2桁に及ぶ変化を示す現象が報告されており、この抵抗変化現象を用いた不揮発抵抗変化メモリが提案されている(特許文献1)。 Recently, a perovskite oxide material represented by a chemical formula of Pr 0.7 Ca 0.3 MnO 3 is sandwiched between an upper electrode and a lower electrode, and a current or an electric current between the upper electrode 14 and the lower electrode 12 is used. There has been reported a phenomenon in which the resistance value of the Pr 0.7 Ca 0.3 MnO 3 13 sandwiched between these electrodes by applying a voltage shows a change of two digits at room temperature, and the nonvolatile resistance using this resistance change phenomenon A change memory has been proposed (Patent Document 1).

このような抵抗変化を用いたメモリはフラッシュメモリで課題となっている書き込み・消去速度が遅い、書き込み電圧が大きいなどの課題点を克服できるに加えて、電荷容量Cではなく電気抵抗Rの変化を用いた動作原理であるので電荷容量に縛られることなく微細化に限界がない事から次世代不揮発メモリとしての実用が期待されている。
米国特許第6204139号明細書 Ignatiev et al. In Proceedings of 15h I nternational symposium on Integrat ed ferroelectronics(ISIF 2003) p.5 84−585 (2003)
The memory using such resistance change can overcome the problems such as slow write / erase speed and high write voltage, which are problems in the flash memory, and also the change in the electric resistance R instead of the charge capacity C. Therefore, it is expected to be used as a next-generation non-volatile memory because there is no limit to miniaturization without being restricted by the charge capacity.
US Pat. No. 6,204,139 Ignatiev et al. In Proceedings of 15h International Symposium on Integrated Ferroelectronics (ISIF 2003) p. 5 84-585 (2003)

しかし、図1に示すような基板11の上に、Pr0.7Ca0.3MnO3層13(以後抵抗変化層と呼ぶ)を下部電極12と上部電極14で挟んだ構成を有する従来の構成では、およそ100℃付近の温度からメモリ特性が劣化するという課題を有している。例えば引用文献1におけるイグナシェフらによる報告においても100℃付近からの抵抗変化率の減少が見られるといったメモリ特性の劣化が見受けられる。 However, in a conventional configuration having a configuration in which a Pr 0.7 Ca 0.3 MnO 3 layer 13 (hereinafter referred to as a resistance change layer) is sandwiched between a lower electrode 12 and an upper electrode 14 on a substrate 11 as shown in FIG. There is a problem that memory characteristics deteriorate from a temperature around 100 ° C. For example, in the report by Ignashev et al. In Cited Document 1, deterioration in memory characteristics such as a decrease in the rate of change in resistance from around 100 ° C. can be seen.

あらゆる機能分野で採用されるようになったメモリ等の電子部品において動作の不安定性が製品に及ぼす影響は重大である。メモリはその用途が多岐にわたるために環境温度の上昇に対してもその動作の安定性が要求されており、JISによる高温(耐熱性)試験方法(JIS C 0021)からも200℃での耐熱性が要求されている。従って100℃付近の温度からメモリ特性が劣化する従来の構成では電子部品として実用するにあたり、重大な課題が残されている。   In electronic components such as memories that have come to be adopted in all functional fields, the influence of instability of operation on products is significant. Since memory has a wide variety of uses, its operation is required to be stable even when the ambient temperature rises. The high temperature (heat resistance) test method by JIS (JIS C 0021) is also used. Is required. Therefore, in the conventional configuration in which the memory characteristics deteriorate from a temperature around 100 ° C., a serious problem remains in practical use as an electronic component.

上記課題を解決する本発明に係る抵抗変化素子は、プラセオジウム(Pr)、カルシウム(Ca)、マンガン(Mn)を含む酸化物よりなる抵抗変化層に電気的に接続された上部電極と下部電極とを備え、前記上部電極と前記下部電極との間に電気パルスを印加して前記抵抗変化層の抵抗を変化させる抵抗変化素子であって、前記抵抗変化層と前記上部電極および前記下部電極との少なくとも一方との間に酸素欠損層を有する。   The variable resistance element according to the present invention that solves the above problems includes an upper electrode and a lower electrode that are electrically connected to a variable resistance layer made of an oxide containing praseodymium (Pr), calcium (Ca), and manganese (Mn). A resistance change element that changes the resistance of the variable resistance layer by applying an electric pulse between the upper electrode and the lower electrode, and includes the variable resistance layer, the upper electrode, and the lower electrode. An oxygen deficient layer is provided between at least one of them.

従来では200℃における温度での動作が不安定であった従来の構成と比較して、200℃でも安定な動作を示す抵抗変化素子を提供する。したがって従来の構成の抵抗変化素子と比較してもより実用的な抵抗変化素子を提供できる。   Provided is a variable resistance element that exhibits stable operation even at 200 ° C. as compared with a conventional configuration, which has conventionally been unstable at 200 ° C. Therefore, a more practical resistance change element can be provided as compared with the resistance change element having the conventional configuration.

以下本発明の実施の形態について、図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

(実施の形態1)
図2に示すように、まず基板11の上に下部電極12を配した後、この下部電極12上に抵抗変化層13を配置し、この抵抗変化層13の表面に酸素欠損層25を形成する。次にこの酸素欠損層25の上に上部電極14を配置して本発明の抵抗変化素子を構成することが出来る。なお、図5に示すように酸素欠損層25は抵抗変化層13と下部電極12との界面に作成しても良い。
(Embodiment 1)
As shown in FIG. 2, after the lower electrode 12 is first disposed on the substrate 11, the resistance change layer 13 is disposed on the lower electrode 12, and the oxygen deficient layer 25 is formed on the surface of the resistance change layer 13. . Next, the resistance change element of the present invention can be configured by disposing the upper electrode 14 on the oxygen deficient layer 25. As shown in FIG. 5, the oxygen deficient layer 25 may be formed at the interface between the resistance change layer 13 and the lower electrode 12.

抵抗変化層13となる(Pr,Ca)MnO3の形成にはRFマグネトロンスパッタリング法を用いて作成することが出来る。具体的な条件は、成長温度は600℃〜900℃、スパッタリング投入電力は60W〜100W、雰囲気ガスは酸素とアルゴンの混合ガスでガス分圧比としてはO2/Ar=0.2〜0.5、雰囲気ガス圧力は1Pa〜5Paである。RFマグネトロンスパッタリング法の他にもパルスレーザーデポジション(PLD)、イオンビームデポジション(IBD)、クラスターイオンビーム又はDC、ECR、へリコン、ICPまたは対向ターゲットなどのスパッタリング法、MBE、イオンプレーティング法等のPVD(Physical Vapor Deposion)法や、CVD(Chemical Vapor Deposion)法、めっき法、あるいは金属有機化合物堆積法(MOD:Metallorganic Decomposion)やゾルゲル法などで作成することが出来る。 The (Pr, Ca) MnO 3 to be the resistance change layer 13 can be formed using an RF magnetron sputtering method. Specifically, the growth temperature is 600 ° C. to 900 ° C., the sputtering input power is 60 W to 100 W, the atmospheric gas is a mixed gas of oxygen and argon, and the gas partial pressure ratio is O 2 /Ar=0.2 to 0.5. The atmospheric gas pressure is 1 Pa to 5 Pa. In addition to the RF magnetron sputtering method, pulsed laser deposition (PLD), ion beam deposition (IBD), cluster ion beam or sputtering method such as DC, ECR, helicon, ICP or counter target, MBE, ion plating method It is possible to create by a PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, a plating method, a metal organic compound deposition method (MOD: Metallic Deposition), a sol-gel method, or the like.

下部電極12は導電材料であって、かつ下部電極12上に抵抗変化層13が配置できる材料であれば良い。例としてはプラチナ(Pt)、イリジウム(Ir)の他、酸化物材料としてはSrTiO3に一部NbやCr、Laが含まれた物やSrRuO3などの導電性酸化物等が挙げられる。これらは、抵抗変化層13である(Pr,Ca)MnO3と同系の結晶構造を有しているために好ましい。 The lower electrode 12 may be a conductive material as long as the variable resistance layer 13 can be disposed on the lower electrode 12. Examples include platinum (Pt) and iridium (Ir), and examples of oxide materials include those in which Nb, Cr, and La are partly contained in SrTiO 3 and conductive oxides such as SrRuO 3 . These are preferable because they have a crystal structure similar to (Pr, Ca) MnO 3 which is the resistance change layer 13.

上部電極14に用いる材料としては、導電材料であればいずれでも良い。例としては銀(Ag)、金(Au)、プラチナ(Pt)、ルテニウム(Ru)、イリジウム(Ir)、アルミニウム(Al)、銅(Cu)、タンタル(Ta)や、錫添加インジウム酸化物(ITO)などが好ましい。   The material used for the upper electrode 14 may be any conductive material. Examples include silver (Ag), gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), aluminum (Al), copper (Cu), tantalum (Ta), tin-doped indium oxide ( ITO) and the like are preferable.

上部電極14及び下部電極12の堆積方法としてはRFマグネトロンスパッタリング法の他にもパルスレーザーデポジション(PLD)、イオンビームデポジション(IBD)、クラスターイオンビーム又はDC、ECR、へリコン、ICPまたは対向ターゲットなどのスパッタリング法、MBE、イオンプレーティング法等のPVD(Physical Vapor Deposion)法や、CVD(Chemical Vapor Deposion)法、めっき法、あるいは金属有機化合物堆積法(MOD:Metallorganic Decomposion)やゾルゲル法でも作成することが出来る。   In addition to the RF magnetron sputtering method, the deposition method of the upper electrode 14 and the lower electrode 12 includes pulsed laser deposition (PLD), ion beam deposition (IBD), cluster ion beam or DC, ECR, helicon, ICP or facing. Sputtering methods such as targets, MBE, ion plating, and other PVD (Physical Vapor Deposition) methods, CVD (Chemical Vapor Deposition) methods, plating methods, metal organic compound deposition (MOD) and sol-gel methods. Can be created.

次に本発明における酸素欠損層25の作成方法について説明する。酸素欠損層25の作成には例えば以下の様なa)〜c)の方法がある。(a)抵抗変化層13の表面を逆スパッタリングする方法、(b)抵抗変化層13の堆積時の酸素分圧を調節する方法、(c)窒素雰囲気中に代表される不活性ガス雰囲気下で抵抗変化層13の表面をアニールする方法などが挙げられる。   Next, a method for creating the oxygen deficient layer 25 in the present invention will be described. For example, the following methods a) to c) can be used to create the oxygen deficient layer 25. (A) A method of reverse sputtering the surface of the resistance change layer 13, (b) a method of adjusting the oxygen partial pressure during deposition of the resistance change layer 13, and (c) under an inert gas atmosphere typified by a nitrogen atmosphere. For example, a method of annealing the surface of the resistance change layer 13 may be used.

(a)逆スパッタリング法を用いて抵抗変化層13表面に酸素欠損層25を作成する場合においては、基板11の上に配した下部電極12に抵抗変化層13を堆積させた後、抵抗変化層13表面を常温〜300℃において逆スパッタリングする。すなわち、下部電極12上に堆積した抵抗変化層13をターゲットとしてスパッタリング投入電力としては40W〜80、スパッタリングガスとしては例えば水素等の還元性ガスを用い、雰囲気ガス圧力は1Pa〜10Paでスパッタリングを施す。抵抗変化層13の表面はイオンで物理的にエッチングされ、中でも酸素の脱離が激しいために抵抗変化層13表面には酸素欠損層25が生じる。逆スパッタリングの後に上部電極14を堆積させる。   (A) In the case where the oxygen deficient layer 25 is formed on the surface of the resistance change layer 13 using the reverse sputtering method, the resistance change layer 13 is deposited on the lower electrode 12 disposed on the substrate 11 and then the resistance change layer. 13 Surface is reverse-sputtered at room temperature to 300 ° C. That is, the resistance change layer 13 deposited on the lower electrode 12 is used as a target, sputtering power is 40 W to 80, a reducing gas such as hydrogen is used as the sputtering gas, and the atmospheric gas pressure is 1 Pa to 10 Pa. . The surface of the resistance change layer 13 is physically etched with ions, and oxygen desorption is severe, so that an oxygen deficient layer 25 is generated on the surface of the resistance change layer 13. After the reverse sputtering, the upper electrode 14 is deposited.

(b)次に抵抗変化層13の堆積時に酸素雰囲気ガスを調整して酸素欠損層25を作成する場合には、酸素欠損層25を作成したい箇所において酸素分圧を一時的に減らすことで作成することが出来る。具体的には基板11上に下部電極12を配した後、抵抗変化層13を堆積させる。RFマグネトロンスパッタリング法を用いた抵抗変化層13の堆積にはアルゴンと酸素のガス分圧比O2/Arをおよそ0.2〜0.5に固定するが、酸素欠損層25を作成する場合にはこのガス分圧比を0.04〜0.1にまで減らして堆積する。酸素欠損層25の堆積の後、上部電極14を配置する。   (B) Next, when the oxygen deficient layer 25 is formed by adjusting the oxygen atmosphere gas when depositing the variable resistance layer 13, it is created by temporarily reducing the oxygen partial pressure at the location where the oxygen deficient layer 25 is to be formed. I can do it. Specifically, after the lower electrode 12 is disposed on the substrate 11, the resistance change layer 13 is deposited. For deposition of the resistance change layer 13 using the RF magnetron sputtering method, the gas partial pressure ratio O2 / Ar of argon and oxygen is fixed to about 0.2 to 0.5. Deposition is performed by reducing the gas partial pressure ratio to 0.04 to 0.1. After the oxygen deficient layer 25 is deposited, the upper electrode 14 is disposed.

(c)窒素雰囲気中で抵抗変化層13の表面をアニールする場合には、まず基板11上に下部電極12を配し、この抵抗変化層13を堆積させた後、高速熱処理をするために1分で500℃〜600℃まで加熱し3分間維持した後、ヒーターの電源を切って急冷した。その結果、抵抗変化層13の表面に酸素欠損層25を作成することが出来、アニールを行った後で上部電極14を堆積させる。   (C) In the case where the surface of the resistance change layer 13 is annealed in a nitrogen atmosphere, first, the lower electrode 12 is disposed on the substrate 11, the resistance change layer 13 is deposited, and then 1 is used for rapid heat treatment. After heating to 500 ° C. to 600 ° C. for 3 minutes and maintaining for 3 minutes, the heater was turned off and rapidly cooled. As a result, the oxygen deficient layer 25 can be formed on the surface of the resistance change layer 13, and the upper electrode 14 is deposited after annealing.

次に、実際にメモリ特性を測定する際の素子について以下の方法で作成する。   Next, an element for actually measuring memory characteristics is created by the following method.

図3(a)に示すように基板11の上に下部電極12を配し、下部電極12上にSiO2などの絶縁酸化膜36を堆積する(図3(b))。次に下部電極12へのコンタクトのためのコンタクトホール38を作成し(図3(c))、下部電極12上に抵抗変化層13を堆積することでコンタクトホール38を埋め(図3(d))、また必要ならば表面の平坦化(CMP処理など)を行い(図3(e))、このような方法を用いて抵抗変化層13の表面に酸素欠損層25を作成した後(図3(f))、所望のメモリ素子を構成するように上部電極14を設けてメモリ素子を実現する(図3(g))。   As shown in FIG. 3A, the lower electrode 12 is disposed on the substrate 11, and an insulating oxide film 36 such as SiO 2 is deposited on the lower electrode 12 (FIG. 3B). Next, a contact hole 38 for contact with the lower electrode 12 is created (FIG. 3C), and the resistance change layer 13 is deposited on the lower electrode 12 to fill the contact hole 38 (FIG. 3D). If necessary, the surface is planarized (CMP treatment or the like) (FIG. 3E), and the oxygen deficient layer 25 is formed on the surface of the resistance change layer 13 using such a method (FIG. 3). (F)) The upper electrode 14 is provided so as to constitute a desired memory element, thereby realizing the memory element (FIG. 3G).

図3に示す方法に代えて、図4(a)に示すように基板11の上に下部電極12を配し、この下部電極12上に抵抗変化層13を堆積する(図4(b))。次に抵抗変化層13の表面に前記の方法で酸素欠損層25を作成する(図4(c))。さらに酸素欠損層25の上に上部電極14を作成し(図4(d))、レジスト材37を配置する(図4(e))。イオンミリング等でレジスト材37に被覆されなかった上部電極14、酸素欠損層25、抵抗変化層13、下部電極12を削る。その後、絶縁膜36を堆積する(図4(g))。最後にリフトオフ法等で絶縁膜36及びその上に位置するレジスト材37を除去(図4(h))することでメモリ素子を実現することが出来る。   Instead of the method shown in FIG. 3, a lower electrode 12 is arranged on a substrate 11 as shown in FIG. 4A, and a resistance change layer 13 is deposited on the lower electrode 12 (FIG. 4B). . Next, the oxygen deficient layer 25 is formed on the surface of the resistance change layer 13 by the method described above (FIG. 4C). Further, the upper electrode 14 is formed on the oxygen deficient layer 25 (FIG. 4D), and a resist material 37 is disposed (FIG. 4E). The upper electrode 14, the oxygen deficient layer 25, the resistance change layer 13, and the lower electrode 12 that are not covered with the resist material 37 are removed by ion milling or the like. Thereafter, an insulating film 36 is deposited (FIG. 4G). Finally, the memory element can be realized by removing the insulating film 36 and the resist material 37 positioned thereon by a lift-off method or the like (FIG. 4H).

あるいは、図6に示すように基板11の上に下部電極12を配し(図6(a))、この下部電極上12の上にSiO2等の絶縁膜36を堆積する(図6(b)。次に下部電極12へのコンタクトのためのコンタクトホール38を作成し(図6(c))、その上にまずは酸素欠損層25を形成し、さらにこの酸素欠損層25の上に抵抗変化層13を堆積することでコンタクトホール38を埋め(図6(d))、また必要ならば表面の平坦化(CMP処理など)を行い(図6(e))、所望のメモリ素子を構成するように上部電極14を設けてメモリ素子を実現する(図6(f))。   Alternatively, as shown in FIG. 6, the lower electrode 12 is disposed on the substrate 11 (FIG. 6A), and an insulating film 36 such as SiO 2 is deposited on the lower electrode 12 (FIG. 6B). Next, a contact hole 38 for making contact with the lower electrode 12 is formed (FIG. 6C), an oxygen deficient layer 25 is first formed thereon, and a resistance change layer is formed on the oxygen deficient layer 25. 13 is deposited to fill the contact hole 38 (FIG. 6D), and if necessary, the surface is flattened (CMP treatment or the like) (FIG. 6E) to form a desired memory element. Is provided with an upper electrode 14 to realize a memory element (FIG. 6F).

なおここで絶縁膜36は、上部電極14及び下部電極12(下部配線および上部配線)を分離するため、SiO2やAl23などの絶縁材料から構成されることが望ましく、いくつかの材料の積層体でも構わない。またレジスト材のようなものも、スピナーコーティングなどで簡便に作れる上、凹凸のある表面にも平坦に作製できる上で好ましい。 Here, the insulating film 36 is preferably made of an insulating material such as SiO 2 or Al 2 O 3 in order to separate the upper electrode 14 and the lower electrode 12 (lower wiring and upper wiring). It may be a laminated body. A resist material is also preferable because it can be easily formed by spinner coating or the like and can be formed flat on an uneven surface.

各層である下部電極12や抵抗変化層13、上部電極14、絶縁層25の各層の形成には、パルスレ−ザデポジション(PLD)、イオンビ−ムデポジション(IBD)、クラスタ−イオンビ−ムまたはRF、DC、ECR、ヘリコン、ICPまたは対向タ−ゲットなどのスパッタリング法、MBE、イオンプレ−ティング法等のPVD(Physical Vapor Deposition)法や、CVD(Chemical Vapor Deposition)法、MOCVD(Metal Organic Chemical Vapor Deposition)法、メッキ法あるいは金属有機化合物堆積法(MOD:Metallorganic Decomposition)やゾルゲル法で作製することができる。   For forming each layer of the lower electrode 12, the resistance change layer 13, the upper electrode 14, and the insulating layer 25, which are each layer, pulse laser deposition (PLD), ion beam deposition (IBD), cluster ion beam or RF, Sputtering methods such as DC, ECR, helicon, ICP or counter target, PVD (Physical Vapor Deposition) methods such as MBE, ion plating method, CVD (Chemical Vapor Deposition) method, MOCVD (Metal Organic ChemistryDepth) It can be manufactured by a method, a plating method, a metal organic compound deposition method (MOD: Metallographic Decomposition) or a sol-gel method.

また微細加工としては、半導体プロセスや、GMRやTMR磁気ヘッドや磁気メモリ(MRAM)などの磁性デバイス作製プロセス等で用いられるイオンミリング、RIE(Reactive Ion Etching)、FIB(Focuced Ion Beam)等の物理的あるいは化学的エッチング法や、微細パタ−ン形成のためにステッパ−、EB(Electron Beam)法等を用いたフォトリソグラフィ−技術を組み合わせることで達成できる。また層間絶縁層や導電層等の膜の表面平坦化には、CMP(Chemical Mechanical Polishing)や、クラスタ−イオンビ−ムエッチングを用いることも効果的である。   As microfabrication, physical processes such as semiconductor processes, ion milling used in magnetic device manufacturing processes such as GMR, TMR magnetic heads, and magnetic memories (MRAM), RIE (Reactive Ion Etching), FIB (Focused Ion Beam), etc. This can be achieved by combining a photolithography technique using a stepper, an EB (Electron Beam) method, or the like for forming a fine pattern. It is also effective to use CMP (Chemical Mechanical Polishing) or cluster ion beam etching for planarizing the surface of films such as interlayer insulating layers and conductive layers.

続いて本構成の抵抗変化素子の書き込みと読み出しについて説明する。上部電極14と下部電極12との間に電流あるいは電圧を印加することで抵抗変化層13の抵抗値が変化する。電流あるいは電圧の印加はパルスで行うのが好ましい。下部電極12に対して、上部電極14を正バイアスにおいてパルスの印加を行うことで抵抗変化層13が高抵抗から低抵抗に変化し、パルスの極性を逆にすることで抵抗値の変化を反転させることが出来る。   Next, writing and reading of the variable resistance element of this configuration will be described. By applying a current or a voltage between the upper electrode 14 and the lower electrode 12, the resistance value of the resistance change layer 13 changes. The application of current or voltage is preferably performed by pulses. By applying a pulse to the lower electrode 12 with the upper electrode 14 having a positive bias, the resistance change layer 13 changes from a high resistance to a low resistance, and the change in resistance value is reversed by reversing the polarity of the pulse. It can be made.

抵抗変化素子の抵抗変化の測定は下部電極12と上部電極14の間にパルスジェネレータを用いてパルス電圧を印加する。抵抗変化の読み出しに用いた電圧は抵抗変化素子への書き込み電圧に対して、1/1000〜1/4程度の十分小さな電圧を用いて行い、一例としてパルス電圧5V,パルス幅250nsecの電圧を用いてスイッチし、抵抗値の読み出しにはパルス電圧0.1V、パルス幅250nsecのパルス電圧を用いて、その際の電流値の変化を読み出す。   The resistance change of the resistance change element is measured by applying a pulse voltage between the lower electrode 12 and the upper electrode 14 using a pulse generator. The voltage used for reading the resistance change is a sufficiently small voltage of about 1/1000 to 1/4 with respect to the write voltage to the resistance change element. For example, a voltage having a pulse voltage of 5 V and a pulse width of 250 nsec is used. In order to read out the resistance value, a pulse voltage having a pulse voltage of 0.1 V and a pulse width of 250 nsec is used, and a change in the current value at that time is read out.

その抵抗変化率(%)を(Rmax−Rmin)/Rmin×100で定義し、Rmax及びRminはそれぞれ印加電圧/印加電流で求める。本発明においては、この抵抗変化率が600%以上であることが好ましい。   The rate of change in resistance (%) is defined by (Rmax−Rmin) / Rmin × 100, and Rmax and Rmin are respectively obtained as applied voltage / applied current. In the present invention, this resistance change rate is preferably 600% or more.

また抵抗変化の読み出しは75℃から200℃までを恒温槽の中で行い、25℃毎に温度を変化させ、目的温度を15分保持した後で抵抗変化の読み出しを行う。   Further, the resistance change is read out from 75 ° C. to 200 ° C. in a thermostat, the temperature is changed every 25 ° C., and the resistance change is read out after holding the target temperature for 15 minutes.

(実施例1)
実施例1においては、図2の構成の素子を図3に示す方法で作成し、メモリ特性の測定を行った。まず、RFマグネトロンスパッタリング法を用いてMgOからなる基板11上に下部電極12を作成した。材料としてはPtを用いて、200nm堆積させ、作成条件は室温、スパッタリング投入電力は80W、雰囲気ガスはアルゴンガスを用い、成長時のガス圧は1Paで形成した(図3(a))。
(Example 1)
In Example 1, an element having the configuration shown in FIG. 2 was prepared by the method shown in FIG. 3, and the memory characteristics were measured. First, the lower electrode 12 was produced on the board | substrate 11 which consists of MgO using RF magnetron sputtering method. As a material, Pt was used to deposit 200 nm, forming conditions were room temperature, sputtering input power was 80 W, atmospheric gas was argon gas, and the gas pressure during growth was 1 Pa (FIG. 3A).

続いて絶縁膜36としてSiO2膜をRFマグネトロンスパッタリング法を用いて作成した(図3(b))。基板温度は100℃でスパッタリング投入電力は100W、雰囲気ガスにはアルゴンを用い、雰囲気ガス圧は0.1Paで作成した。 Subsequently, an SiO 2 film was formed as the insulating film 36 by using an RF magnetron sputtering method (FIG. 3B). The substrate temperature was 100 ° C., the sputtering input power was 100 W, the atmosphere gas was argon, and the atmosphere gas pressure was 0.1 Pa.

次に抵抗変化層13の下部電極12へのコンタクトのためにRIEを用いて直径0.5μmの大きさのコンタクトホール38を作成した(図3(c))。   Next, for contact with the lower electrode 12 of the resistance change layer 13, a contact hole 38 having a diameter of 0.5 μm was formed using RIE (FIG. 3C).

このコンタクトホール38の上に抵抗変化層13となるPr0.7Ca0.3MnO3をRFマグネトロンスパッタリング法を用いて300nm堆積した(図3(d))。スパッタリングしたターゲットはプラセオジウム、カルシウム、マンガンからなる酸化物で、化学式Pr0.7Ca0.3MnO3で表されるものであった。堆積にはRFマグネトロンスパッタリング法を用いてスパッタリング投入電力は80W、基板温度700℃で成長時のガス圧は3Paとし、雰囲気ガスは酸素とアルゴンをO2/Ar〜0.25の割合で混合させたガスを用いた。Pr0.7Ca0.3MnO3はX線回折の結果、多結晶膜であった。 On the contact hole 38, Pr 0.7 Ca 0.3 MnO 3 serving as the resistance change layer 13 was deposited by 300 nm by RF magnetron sputtering (FIG. 3D). The sputtered target was an oxide composed of praseodymium, calcium, and manganese and represented by the chemical formula Pr 0.7 Ca 0.3 MnO 3 . The RF magnetron sputtering method is used for deposition, the sputtering input power is 80 W, the substrate temperature is 700 ° C., the growth gas pressure is 3 Pa, and the atmosphere gas is a mixture of oxygen and argon in a ratio of O 2 / Ar to 0.25. Gas was used. Pr 0.7 Ca 0.3 MnO 3 was a polycrystalline film as a result of X-ray diffraction.

コンタクトホール38を埋め込んだ後にCMP処理を行い(図3(e))、その表面を逆スパッタリングすることで抵抗変化層13の表面に酸素欠損層25を作成した(図3(f))。逆スパッタリングにはRFマグネトロンスパッタリング法を用いて、条件としては300℃においてスパッタリング投入電力40W、雰囲気ガスは水素ガスを用いて雰囲気ガス圧は5Paの条件で行った。また印加電圧の周波数を100MHzにして逆スパッタリングすることで極めて安定したメモリ動作を示す素子を作成することが出来た。   After filling the contact hole 38, CMP was performed (FIG. 3E), and the oxygen deficient layer 25 was formed on the surface of the resistance change layer 13 by reverse sputtering the surface (FIG. 3F). The reverse sputtering was performed using an RF magnetron sputtering method under the conditions that the sputtering input power was 40 W at 300 ° C., the atmosphere gas was hydrogen gas, and the atmosphere gas pressure was 5 Pa. In addition, by performing reverse sputtering with the applied voltage frequency set to 100 MHz, an element exhibiting extremely stable memory operation could be produced.

その上に上部電極14を50nmのAgをマグネトロンスパッタリング法で作成した。上部電極14は室温、スパッタリング投入電力は80W、雰囲気ガスにはアルゴンを用い、成長時のガス圧は1Paとした(図3(g))。以上の方法で構成した抵抗変化素子のメモリ特性を測定した。   On top of this, 50 nm of Ag was formed by the magnetron sputtering method as the upper electrode 14. The upper electrode 14 was at room temperature, the sputtering input power was 80 W, the atmosphere gas was argon, and the gas pressure during growth was 1 Pa (FIG. 3G). The memory characteristics of the variable resistance element configured by the above method were measured.

比較例として従来と同様の図1の構成を有する抵抗変化素子を作成し、比較例Aとした。酸素欠損層25を除き、上記実施例1と同じ条件で作成し、絶縁膜36等の構成についても同様にして作成した。   As a comparative example, a variable resistance element having the same configuration as in FIG. Except for the oxygen deficient layer 25, it was formed under the same conditions as in Example 1, and the structure of the insulating film 36 and the like was also formed in the same manner.

酸素欠損層25と上部電極14の界面から基板11方向への酸素欠損層25の深さが異なる場合のメモリ動作の違いについても調べるために、逆スパッタリングの時間を100〜200秒で調節し、酸素欠損層25の基板11方向への深さが異なる素子も作成した。   In order to investigate the difference in memory operation when the depth of the oxygen deficient layer 25 differs from the interface between the oxygen deficient layer 25 and the upper electrode 14 toward the substrate 11, the reverse sputtering time is adjusted to 100 to 200 seconds, Elements having different depths of the oxygen deficient layer 25 in the direction of the substrate 11 were also produced.

次に実施例1と比較例Aのメモリ特性を確認するために以下の手順で抵抗変化の測定を行った。まず、実施例1と比較例Aの素子を恒温槽の中に入れて75℃から200℃まで昇温させ、25℃おきに抵抗変化を測定した。抵抗変化の測定は以下の手順で行った。抵抗変化素子の抵抗変化の測定は下部電極12と上部電極14の間にパルスジェネレータを用いてパルス電圧を印加した。高抵抗から低抵抗及び低抵抗から高抵抗への変化にはパルス電圧5V,パルス幅250nsecの電圧を用いて抵抗をスイッチし、抵抗値の読み出しにはパルス電圧0.1V、パルス幅250nsecのパルス電圧を用いて、その際の電流値の変化を読み出して行った。その抵抗変化率(%)を(Rmax−Rmin)/Rmin×100で定義し、Rmax及びRminはそれぞれ印加電圧/印加電流で求めた。結果を以下の表1に示す。   Next, in order to confirm the memory characteristics of Example 1 and Comparative Example A, the resistance change was measured by the following procedure. First, the elements of Example 1 and Comparative Example A were placed in a thermostatic bath, the temperature was raised from 75 ° C. to 200 ° C., and the resistance change was measured every 25 ° C. The resistance change was measured according to the following procedure. The resistance change of the resistance change element was measured by applying a pulse voltage between the lower electrode 12 and the upper electrode 14 using a pulse generator. To change from high resistance to low resistance and from low resistance to high resistance, the resistance is switched using a voltage of 5V and a pulse width of 250nsec, and a resistance value is read out by a pulse having a pulse voltage of 0.1V and a pulse width of 250nsec. Using voltage, the change in current value at that time was read out. The rate of change in resistance (%) was defined by (Rmax−Rmin) / Rmin × 100, and Rmax and Rmin were respectively determined as applied voltage / applied current. The results are shown in Table 1 below.

Figure 2008060091
本実施例に基づいて作成した素子のメモリ特性を測定した結果、逆スパッタリングを100秒施した素子の抵抗変化率が最も大きく、200℃まで安定したメモリ特性を示し、逆スパッタリング時間を200秒と長くすると抵抗変化は小さくなるが200℃まで安定した動作を示した。
Figure 2008060091
As a result of measuring the memory characteristics of the element produced based on this example, the resistance change rate of the element subjected to reverse sputtering for 100 seconds was the largest, and showed stable memory characteristics up to 200 ° C., and the reverse sputtering time was 200 seconds. The longer the resistance, the smaller the change in resistance, but it showed stable operation up to 200 ° C.

一方、酸素欠損層25を有しない比較例Aは25℃においては大きな抵抗変化を示すものの、100℃、200℃の温度では抵抗変化率の著しい劣化が見られた。これらの結果より、酸素欠損層25は抵抗変化層13の表面になるべく薄く形成する方が好ましいと思われる。また本実施例において酸素欠損層25の形成条件として、逆スパッタリングの温度、投入電力、雰囲気ガス圧力などを変えて実験したところ同様の結果を得ることが出来た。   On the other hand, Comparative Example A having no oxygen deficient layer 25 showed a large resistance change at 25 ° C., but a remarkable deterioration in the resistance change rate was observed at temperatures of 100 ° C. and 200 ° C. From these results, it seems that it is preferable to form the oxygen deficient layer 25 as thin as possible on the surface of the resistance change layer 13. Further, in the present example, when the experiment was carried out by changing the reverse sputtering temperature, input power, atmospheric gas pressure, etc. as the formation conditions of the oxygen deficient layer 25, the same results could be obtained.

(実施例2)
実施例2においては、図2の構成の素子を図4に示す通りに作成し、メモリ特性を測定した。
(Example 2)
In Example 2, an element having the configuration shown in FIG. 2 was prepared as shown in FIG. 4, and the memory characteristics were measured.

まず、Siからなる基板11の上に抵抗変化素子を以下のように作成した。下部電極12をマグネトロンスパッタリング法で配置した。材料としてはPtを用いて、200nm堆積させ、作成条件は室温、スパッタリング投入電力は80W、成雰囲気ガスはアルゴンで、ガス圧は1Paで作成した(図4(a))。   First, a variable resistance element was formed on a substrate 11 made of Si as follows. The lower electrode 12 was disposed by magnetron sputtering. Pt was used as the material to deposit 200 nm, the production conditions were room temperature, sputtering input power was 80 W, the atmosphere gas was argon, and the gas pressure was 1 Pa (FIG. 4A).

続いて抵抗変化層13となるPr0.7Ca0.3MnO3をRFマグネトロンスパッタリング法で300nm堆積した(図4(b))。スパッタリングするターゲットはプラセオジウム、カルシウム、マンガンからなる酸化物で、化学式Pr0.7Ca0.3MnO3で表されるものであった。実際に堆積する際には基板温度700℃でスパッタリング投入電力は80W、雰囲気ガスは酸素とアルゴンをO2/Ar〜0.25の割合で混合させたガスを用い、雰囲気ガス圧は3Paとした。その後、酸素とアルゴンの混合比O2/Arを小さくして酸素欠損層25を形成した。また混合比O2/Arは0.08から0.1まで変化させることで酸素が欠損した部分における酸素量の異なる素子を作成した。またPr0.7Ca0.3MnO3はX線回折の結果、多結晶膜であった。 Subsequently, Pr 0.7 Ca 0.3 MnO 3 to be the resistance change layer 13 was deposited by 300 nm by RF magnetron sputtering (FIG. 4B). The target to be sputtered was an oxide composed of praseodymium, calcium, and manganese and represented by the chemical formula Pr 0.7 Ca 0.3 MnO 3 . In the actual deposition, the substrate temperature was 700 ° C., the sputtering input power was 80 W, the atmospheric gas was a gas in which oxygen and argon were mixed at a ratio of O 2 / Ar to 0.25, and the atmospheric gas pressure was 3 Pa. Thereafter, the oxygen deficient layer 25 was formed by reducing the oxygen / argon mixing ratio O 2 / Ar. Further, by changing the mixing ratio O 2 / Ar from 0.08 to 0.1, elements having different oxygen amounts in the portion where oxygen was lost were prepared. Pr 0.7 Ca 0.3 MnO 3 was a polycrystalline film as a result of X-ray diffraction.

さらにその上に上部電極14を50nmのAgをマグネトロンスパッタリング法を用いて作成した(図4(d))。上部電極14は室温、スパッタ投入電力としては80Wとし、雰囲気ガスはアルゴンガスを用い、成長時のガス圧は1Paとした。   Further thereon, an upper electrode 14 was made of 50 nm Ag by magnetron sputtering (FIG. 4D). The upper electrode 14 was at room temperature, the sputtering input power was 80 W, the atmosphere gas was argon gas, and the gas pressure during growth was 1 Pa.

次に上部電極14の上にレジスト材37を配置し、イオンミリングを用いてレジスト材37に被覆されなかった上部電極14、酸素欠損層25、抵抗変化層13、上部電極12を削った後(図4(f))、絶縁膜36となるSiO2膜をマグネトロンスパッタリング法により堆積した(図4(g))。基板温度は100℃でスパッタリング投入 、雰囲気ガスにはアルゴンを用い、雰囲気ガス圧は0.1Paで作成した。最後にリフトオフ法を用いて、レジスト材37及びその上に位置する絶縁体36を取り除いた(図4(h))。以上の手順で作成した構成を用いて実施例2の抵抗変化素子のメモリ特性を測定した。 Next, a resist material 37 is disposed on the upper electrode 14, and the upper electrode 14, the oxygen deficient layer 25, the resistance change layer 13, and the upper electrode 12 that are not covered with the resist material 37 are removed by ion milling ( 4 (f)), an SiO 2 film to be the insulating film 36 was deposited by magnetron sputtering (FIG. 4 (g)). Sputtering was performed at a substrate temperature of 100 ° C., argon was used as the atmospheric gas, and the atmospheric gas pressure was 0.1 Pa. Finally, the resist material 37 and the insulator 36 located thereon were removed using a lift-off method (FIG. 4 (h)). The memory characteristics of the variable resistance element of Example 2 were measured using the configuration created by the above procedure.

比較例として従来の構成の抵抗変化素子を作成し、比較例Bとした。酸素欠損層25を除き、上記実施例1と同じ条件で作成し、絶縁膜36等の構成や作成手法についても同様にして作成した。また酸素欠損層25の酸素量が異なる場合のメモリ動作の違いについても調べるために、酸素欠損層25を作る際の酸素ガス分圧比を少なくして素子を作成した。   As a comparative example, a variable resistance element having a conventional configuration was created and used as comparative example B. Except for the oxygen deficient layer 25, it was formed under the same conditions as in Example 1 above, and the configuration and preparation method of the insulating film 36 and the like were also prepared in the same manner. Further, in order to investigate the difference in memory operation when the amount of oxygen in the oxygen deficient layer 25 is different, an element was produced by reducing the oxygen gas partial pressure ratio when forming the oxygen deficient layer 25.

次に実施例と比較例Bのメモリ特性を確認するために以下の手順で抵抗変化の測定を行った。まず、実施例2と比較例Bの素子を恒温槽の中に入れて75℃から200℃まで昇温させ、25℃おきに抵抗変化を測定した。抵抗変化の測定は以下の手順で行った。抵抗変化素子の抵抗変化の測定は下部電極12と上部電極14の間にパルスジェネレータを用いてパルス電圧を印加した。高抵抗から低抵抗及び低抵抗から高抵抗への変化にはパルス電圧5V,パルス幅250nsecの電圧を用いて抵抗をスイッチし、抵抗値の読み出しにはパルス電圧0.1V、パルス幅250nsecのパルス電圧を用いて、その際の電流値の変化を読み出して行った。その抵抗変化率(%)を(Rmax−Rmin)/Rmin×100で定義し、Rmax及びRminはそれぞれ印加電圧/印加電流で求めた。結果を以下の表2に示す。   Next, in order to confirm the memory characteristics of the example and the comparative example B, the resistance change was measured by the following procedure. First, the elements of Example 2 and Comparative Example B were put in a thermostatic bath, the temperature was raised from 75 ° C. to 200 ° C., and the resistance change was measured every 25 ° C. The resistance change was measured according to the following procedure. The resistance change of the resistance change element was measured by applying a pulse voltage between the lower electrode 12 and the upper electrode 14 using a pulse generator. To change from high resistance to low resistance and from low resistance to high resistance, the resistance is switched using a voltage of 5V and a pulse width of 250nsec, and a resistance value is read out by a pulse having a pulse voltage of 0.1V and a pulse width of 250nsec. Using voltage, the change in current value at that time was read out. The rate of change in resistance (%) was defined by (Rmax−Rmin) / Rmin × 100, and Rmax and Rmin were respectively determined as applied voltage / applied current. The results are shown in Table 2 below.

Figure 2008060091
抵抗変化率の測定結果である表2について説明する。酸素欠損層25の作成時に用いた酸素分圧比O2/Arを変えた場合の抵抗変化率を25℃、100℃、200℃とそれぞれの温度について測定した。比較例Bは比較例Aと同様にして25℃においては大きな抵抗変化率を示すものの100℃、200℃の温度では抵抗変化率に著しい劣化が見られた。一方、O2/Arが0.08及び0.1の実施例においては25℃から200℃に至るまで大きく安定した抵抗変化率が見られた。
Figure 2008060091
Table 2 which is a measurement result of the resistance change rate will be described. The resistance change rate when the oxygen partial pressure ratio O2 / Ar used when the oxygen deficient layer 25 was formed was measured at each temperature of 25 ° C., 100 ° C., and 200 ° C. In the same manner as Comparative Example A, Comparative Example B showed a large rate of change in resistance at 25 ° C., but significant deterioration was observed in the rate of change in resistance at temperatures of 100 ° C. and 200 ° C. On the other hand, in the examples where O2 / Ar was 0.08 and 0.1, a large and stable resistance change rate was observed from 25 ° C to 200 ° C.

(実施例3)
実施例3においては、図5の構成の素子を、図6に示す方法で作成し、メモリ特性の測定を行った。図5は抵抗変化層13と下部電極12の間に酸素欠損層25を作成し、この抵抗変化層13の上に上部電極14を配した構成の図である。この実施例3の抵抗変化素子の作成方法を図6と共に説明する。
(Example 3)
In Example 3, an element having the configuration shown in FIG. 5 was prepared by the method shown in FIG. 6, and the memory characteristics were measured. FIG. 5 is a diagram showing a configuration in which an oxygen deficient layer 25 is formed between the resistance change layer 13 and the lower electrode 12, and the upper electrode 14 is disposed on the resistance change layer 13. A method for producing the variable resistance element according to Example 3 will be described with reference to FIG.

マグネトロンスパッタリング法を用いてMgOからなる基板11の上に抵抗変化素子を作成した。下部電極12の材料としてはPtを用いて、200nm堆積させ、作成条件は室温、スパッタリング投入電力としては80Wとし、雰囲気ガスはアルゴンガスを用い、成長時のガス圧は1Paで作成した(図6(a))。   A resistance change element was formed on the substrate 11 made of MgO by using a magnetron sputtering method. The lower electrode 12 is made of Pt and deposited to a thickness of 200 nm, the production conditions are room temperature, the sputtering input power is 80 W, the atmosphere gas is argon gas, and the growth gas pressure is 1 Pa (FIG. 6). (A)).

続いて絶縁膜36としてSiO2膜をマグネトロンスパッタリング法を用いて作成した(図6(b))。基板温度は100℃でスパッタリング投入電力は100W、雰囲気ガスにはアルゴンを用い、雰囲気ガス圧は0.1Paで作成した。次に下部電極12へのコンタクトのためにRIEを用いて直径0.5μmの大きさのコンタクトホール38を作成した(図6(c))。このコンタクトホールにまず、酸素欠損層25をRFマグネトロンスパッタリング法を用いて作成する。条件としては基板温度700℃でスパッタリング投入電力は80W、雰囲気ガスは酸素とアルゴンをO2/Ar〜0.1の割合で混合させたガスを用い、成長時の雰囲気ガス圧は3Paとした。その後、酸素とアルゴンをO2/Ar〜0.25に戻して抵抗変化層13となるPr0.7Ca0.3MnO3を300nm堆積した(図6(d))。スパッタリングするターゲットはプラセオジウム、カルシウム、マンガンからなる酸化物で、化学式Pr0.7Ca0.3MnO3で表されるものであった。また作成したPr0.7Ca0.3MnO3はX線回折の結果、多結晶膜であった。その後、コンタクトホール38を埋め込んだ後にCMP処理を行い(図6−(e))、この上に上部電極14を50nmのAgをマグネトロンスパッタリング法で作成した。上部電極14は室温、スパッタリング投入電力としては80Wとし、雰囲気ガスはアルゴンガスを用い、成長時のガス圧は1Paであった(図6(g))。以上の構成を持って実施例3の抵抗変化素子のメモリ特性を測定した。 Subsequently, a SiO 2 film was formed as the insulating film 36 by using a magnetron sputtering method (FIG. 6B). The substrate temperature was 100 ° C., the sputtering input power was 100 W, the atmosphere gas was argon, and the atmosphere gas pressure was 0.1 Pa. Next, for contact with the lower electrode 12, a contact hole 38 having a diameter of 0.5 μm was formed using RIE (FIG. 6C). First, an oxygen deficient layer 25 is formed in this contact hole by using an RF magnetron sputtering method. As conditions, the substrate temperature was 700 ° C., the sputtering input power was 80 W, the atmosphere gas was a gas in which oxygen and argon were mixed at a ratio of O 2 / Ar to 0.1, and the atmosphere gas pressure during growth was 3 Pa. Thereafter, oxygen and argon were returned to O 2 / Ar to 0.25, and Pr 0.7 Ca 0.3 MnO 3 serving as the resistance change layer 13 was deposited to a thickness of 300 nm (FIG. 6D). The target to be sputtered was an oxide composed of praseodymium, calcium, and manganese and represented by the chemical formula Pr 0.7 Ca 0.3 MnO 3 . The prepared Pr 0.7 Ca 0.3 MnO 3 was a polycrystalline film as a result of X-ray diffraction. Then, after filling the contact hole 38, CMP processing was performed (FIG. 6- (e)), and 50 nm of Ag was formed thereon by magnetron sputtering. The upper electrode 14 was at room temperature, the sputtering input power was 80 W, the atmosphere gas was argon gas, and the gas pressure during growth was 1 Pa (FIG. 6G). With the above configuration, the memory characteristics of the variable resistance element of Example 3 were measured.

実施例3においても実施例1と同様に比較例Cを作成した。この比較例Cの作成条件及び構成は酸素欠損層25を除き、上記実施例3における比較例Cと同様である。   In Example 3, Comparative Example C was prepared in the same manner as Example 1. The preparation conditions and configuration of Comparative Example C are the same as those of Comparative Example C in Example 3 except for the oxygen deficient layer 25.

次に実施例3と比較例Cのメモリ特性を確認するために以下の手順で抵抗変化の測定を行った。まず、実施例3と比較例Cの素子を恒温槽の中に入れて75℃から200℃まで昇温させ、25℃おきに抵抗変化を測定した。抵抗変化の測定は以下の手順で行った。抵抗変化素子の抵抗変化の測定は下部電極12と上部電極14の間にパルスジェネレータを用いてパルス電圧を印加した。高抵抗から低抵抗及び低抵抗から高抵抗への変化にはパルス電圧5V,パルス幅250nsecの電圧を用いて抵抗をスイッチし、抵抗値の読み出しにはパルス電圧0.1V、パルス幅250nsecのパルス電圧を用いて、その際の電流値の変化を読み出して行った。その抵抗変化率(%)を(Rmax−Rmin)/Rmin×100で定義し、Rmax及びRminはそれぞれ印加電圧/印加電流で求めた。結果を以下の表3に示す。   Next, in order to confirm the memory characteristics of Example 3 and Comparative Example C, resistance change was measured by the following procedure. First, the elements of Example 3 and Comparative Example C were placed in a thermostatic bath, the temperature was raised from 75 ° C. to 200 ° C., and the resistance change was measured every 25 ° C. The resistance change was measured according to the following procedure. The resistance change of the resistance change element was measured by applying a pulse voltage between the lower electrode 12 and the upper electrode 14 using a pulse generator. To change from high resistance to low resistance and from low resistance to high resistance, the resistance is switched using a voltage of 5V and a pulse width of 250nsec, and a resistance value is read out by a pulse having a pulse voltage of 0.1V and a pulse width of 250nsec. Using voltage, the change in current value at that time was read out. The rate of change in resistance (%) was defined by (Rmax−Rmin) / Rmin × 100, and Rmax and Rmin were respectively determined as applied voltage / applied current. The results are shown in Table 3 below.

Figure 2008060091
実施例3における構成のメモリ特性を測定した結果、比較例Cの抵抗変化素子は200℃の温度においてメモリ特性の明らかな劣化が見られた。一方、実施例3の構成を有する抵抗変化素子では200℃においても抵抗変化率600%以上であり、室温と同様の安定したメモリ特性が得られた。
Figure 2008060091
As a result of measuring the memory characteristics of the configuration in Example 3, the resistance change element of Comparative Example C showed a clear deterioration in memory characteristics at a temperature of 200 ° C. On the other hand, the resistance change element having the configuration of Example 3 had a resistance change rate of 600% or more even at 200 ° C., and stable memory characteristics similar to those at room temperature were obtained.

(実施例4)
実施例2と同様の構成を持つ素子を図4に示す方法で形成し、メモリ特性を測定した。
Example 4
An element having the same configuration as in Example 2 was formed by the method shown in FIG. 4, and the memory characteristics were measured.

まずSiからなる基板11の上に抵抗変化素子を以下のようにして作成した。下部電極12をマグネトロンスパッタリング法で配置した。材料としてはPtを用いて、200nm堆積させ、作成条件は室温、スパッタリング投入電力としては80Wとし、雰囲気ガスはアルゴンガスを用い、成長時のガス圧は1Paとした(図4(a))。   First, a variable resistance element was formed on a substrate 11 made of Si as follows. The lower electrode 12 was disposed by magnetron sputtering. Pt was used as the material and deposited to 200 nm, the preparation conditions were room temperature, the sputtering input power was 80 W, the atmosphere gas was argon gas, and the growth gas pressure was 1 Pa (FIG. 4A).

続いて抵抗変化層13となるPr0.7Ca0.3MnO3をRFマグネトロンスパッタリング法で300nm堆積した(図4(b))。スパッタリングするターゲットはプラセオジウム、カルシウム、マンガンからなる酸化物で、化学式Pr0.7Ca0.3MnO3で表されるものであった。実際に堆積する際には基板温度700℃でスパッタリング投入電力は80W、雰囲気ガスは酸素とアルゴンをO2/Ar〜0.25の割合で混合させたガスを用い、成長時の雰囲気ガス圧は3Paとした。またPr0.7Ca0.3MnO3はX線回折の結果、多結晶膜であった。 Subsequently, Pr 0.7 Ca 0.3 MnO 3 to be the resistance change layer 13 was deposited by 300 nm by RF magnetron sputtering (FIG. 4B). The target to be sputtered was an oxide composed of praseodymium, calcium, and manganese and represented by the chemical formula Pr0.7Ca0.3MnO3. When actually depositing, the substrate temperature is 700 ° C., the sputtering input power is 80 W, the atmospheric gas is a gas in which oxygen and argon are mixed at a ratio of O 2 / Ar to 0.25, and the atmospheric gas pressure during growth is 3 Pa. It was. Pr0.7Ca0.3MnO3 was a polycrystalline film as a result of X-ray diffraction.

その後、酸素欠損層25を作成するために抵抗変化層13を有する素子を窒素雰囲気中にて高速熱処理した。まず1分で500℃まで素子を加熱し3分間維持した後、ヒーターの電源を切って急冷した。その結果、表面に酸素欠損層25を作成することが出来た(図4(c))。   Thereafter, in order to form the oxygen deficient layer 25, the element having the resistance change layer 13 was subjected to rapid heat treatment in a nitrogen atmosphere. First, the element was heated to 500 ° C. in 1 minute and maintained for 3 minutes, and then the heater was turned off and rapidly cooled. As a result, the oxygen deficient layer 25 could be created on the surface (FIG. 4C).

さらにその上に上部電極14を50nmのAgをマグネトロンスパッタリング法を用いて作成した(図4(d))。上部電極14は室温、スパッタリング投入電力としては80Wとし、雰囲気ガスはアルゴンガスを用いて成長時のガス圧は1Paとした。   Further thereon, an upper electrode 14 was made of 50 nm Ag by magnetron sputtering (FIG. 4D). The upper electrode 14 was at room temperature, the sputtering input power was 80 W, the atmosphere gas was argon gas, and the gas pressure during growth was 1 Pa.

次に上部電極14の上にレジスト材37を配置し、イオンミリングを用いてレジスト材37に被覆されなかった上部電極14、酸素欠損層25、抵抗変化層13、下部電極12を削った後、絶縁膜36となるSiO2膜をマグネトロンスパッタリング法を用いて堆積した(図4(g))。基板温度は100℃でスパッタ電力は100W、雰囲気ガスにはアルゴンを用い、雰囲気ガス圧は0.1Paで作成した。最後にリフトオフ法を用いて、レジスト材37及びその上に位置する絶縁体36を取り除いた(図4(h))。以上の手順で作成した構成を用いてこの実施例4の抵抗変化素子のメモリ特性を測定した。 Next, a resist material 37 is disposed on the upper electrode 14, and after cutting the upper electrode 14, the oxygen deficient layer 25, the resistance change layer 13, and the lower electrode 12 that are not covered with the resist material 37 using ion milling, A SiO 2 film to be the insulating film 36 was deposited by using a magnetron sputtering method (FIG. 4G). The substrate temperature was 100 ° C., the sputtering power was 100 W, the atmosphere gas was argon, and the atmosphere gas pressure was 0.1 Pa. Finally, the resist material 37 and the insulator 36 located thereon were removed using a lift-off method (FIG. 4 (h)). The memory characteristics of the variable resistance element of Example 4 were measured using the configuration created by the above procedure.

比較例として従来の構成の抵抗変化素子を作成し、比較例Dとした。この比較例Dは酸素欠損層25を除き、上記実施例1と同じ条件で作成し、絶縁膜36等の構成や作成手法についても同様にして作成した。   As a comparative example, a variable resistance element having a conventional configuration was created and used as comparative example D. This Comparative Example D was prepared under the same conditions as in Example 1 except for the oxygen deficient layer 25, and the configuration and preparation method of the insulating film 36 and the like were also prepared in the same manner.

次に実施例4と比較例Dのメモリ特性を確認するために以下の手順で抵抗変化の測定を行った。まず、実施例4と比較例Dの素子を恒温槽の中に入れて75℃から200℃まで昇温させ、25℃おきに抵抗変化を測定した。抵抗変化の測定は以下の手順で行った。抵抗変化素子の抵抗変化の測定は下部電極12と上部電極14の間にパルスジェネレータを用いてパルス電圧を印加した。高抵抗から低抵抗及び低抵抗から高抵抗への変化にはパルス電圧5V,パルス幅250nsecの電圧を用いて抵抗をスイッチし、抵抗値の読み出しにはパルス電圧0.1V、パルス幅250nsecのパルス電圧を用いて、その際の電流値の変化を読み出して行った。その抵抗変化率(%)を(Rmax−Rmin)/Rmin×100で定義し、Rmax及びRminはそれぞれ印加電圧/印加電流で求めた。結果を以下の表4に示す。   Next, in order to confirm the memory characteristics of Example 4 and Comparative Example D, the resistance change was measured by the following procedure. First, the elements of Example 4 and Comparative Example D were placed in a thermostatic bath, the temperature was raised from 75 ° C. to 200 ° C., and the resistance change was measured every 25 ° C. The resistance change was measured according to the following procedure. The resistance change of the resistance change element was measured by applying a pulse voltage between the lower electrode 12 and the upper electrode 14 using a pulse generator. To change from high resistance to low resistance and from low resistance to high resistance, the resistance is switched using a voltage of 5V and a pulse width of 250nsec, and a resistance value is read out by a pulse having a pulse voltage of 0.1V and a pulse width of 250nsec. Using voltage, the change in current value at that time was read out. The rate of change in resistance (%) was defined by (Rmax−Rmin) / Rmin × 100, and Rmax and Rmin were respectively determined as applied voltage / applied current. The results are shown in Table 4 below.

Figure 2008060091
抵抗変化率の測定結果である表4について説明する。酸素欠損層25の作成した素子の抵抗変化率と作成しない素子の抵抗変化率を25℃、100℃、200℃とそれぞれの温度について測定した。比較例Dは比較例Aと同様に25℃においては大きな抵抗変化率を示すものの100℃、200℃の温度では抵抗変化率に著しい劣化が見られた。熱処理した素子においては25℃、100℃、200℃において大きく安定した抵抗変化率が見られた。
Figure 2008060091
Table 4 which is a measurement result of the resistance change rate will be described. The resistance change rate of the element formed with the oxygen deficient layer 25 and the resistance change rate of the element not formed were measured at 25 ° C., 100 ° C., and 200 ° C., respectively. As in Comparative Example A, Comparative Example D showed a large resistance change rate at 25 ° C., but the resistance change rate was significantly deteriorated at temperatures of 100 ° C. and 200 ° C. In the heat-treated element, a large and stable resistance change rate was observed at 25 ° C., 100 ° C., and 200 ° C.

本発明の抵抗変化素子は(Pr,Ca)MnO3なる化学式で表される抵抗変化層13及び、この抵抗変化層13を挟む上部電極14と下部電極12で構成されている。本構成素子に電圧または電流を印加することで抵抗変化層13の抵抗値が変化し、この抵抗変化層13の抵抗値が保持されることを利用して抵抗メモリの界面に酸素欠損層25を作成することで200℃を経ても安定した動作が得られるため、実用的な不揮発メモリとして利用できる。 The variable resistance element according to the present invention includes a variable resistance layer 13 represented by a chemical formula (Pr , Ca) MnO 3, and an upper electrode 14 and a lower electrode 12 sandwiching the variable resistance layer 13. The resistance value of the resistance change layer 13 is changed by applying a voltage or a current to the component, and the resistance value of the resistance change layer 13 is retained, so that the oxygen deficient layer 25 is formed at the interface of the resistance memory. Since a stable operation can be obtained even after passing through 200 ° C., it can be used as a practical nonvolatile memory.

以下、本発明をまとめる:
1.
プラセオジウム(Pr)、カルシウム(Ca)、マンガン(Mn)を含む酸化物よりなる抵抗変化層(13)に電気的に接続された上部電極(14)と下部電極(12)とを備え、前記上部電極(14)と前記下部電極(13)との間に電気パルスを印加して前記抵抗変化層(13)の抵抗を変化させる抵抗変化素子であって、
前記抵抗変化層(13)と前記上部電極(14)および前記下部電極(12)の少なくとも一方との間に酸素欠損層(25)を有する抵抗変化素子。
The following summarizes the present invention:
1.
An upper electrode (14) and a lower electrode (12) electrically connected to a resistance change layer (13) made of an oxide containing praseodymium (Pr), calcium (Ca), and manganese (Mn), A resistance change element that applies an electric pulse between an electrode (14) and the lower electrode (13) to change the resistance of the resistance change layer (13);
A variable resistance element having an oxygen deficient layer (25) between the variable resistance layer (13) and at least one of the upper electrode (14) and the lower electrode (12).

2.
前記抵抗変化層(13)と前記上部電極(14)との間に酸素欠損層(25)を有する前記項1に記載の抵抗変化素子。(図2)
3.
前記抵抗変化層(13)と前記下部電極(12)との間に酸素欠損層(25)を有する前記項1に記載の抵抗変化素子。(図5)
4.
前記抵抗変化層(13)と前記上部電極(14)および前記下部電極(12)の両方との間にそれぞれ酸素欠損層(25)を前記項1に記載の抵抗変化素子。
2.
Item 2. The variable resistance element according to Item 1, wherein an oxygen deficient layer (25) is provided between the variable resistance layer (13) and the upper electrode (14). (Figure 2)
3.
Item 2. The variable resistance element according to Item 1, wherein an oxygen deficient layer (25) is provided between the variable resistance layer (13) and the lower electrode (12). (Fig. 5)
4).
The variable resistance element according to Item 1, wherein an oxygen deficient layer (25) is provided between the variable resistance layer (13) and both the upper electrode (14) and the lower electrode (12).

5.
下部電極(12)を形成する下部電極形成工程、
前記下部電極(12)の表面にプラセオジウム(Pr)、カルシウム(Ca)、マンガン(Mn)を含む酸化物よりなる抵抗変化層(13)を形成する抵抗変化層形成工程、
前記抵抗変化層(13)の表面を逆スパッタリングする逆スパッタリング工程、および
前記逆スパッタリングされた抵抗変化層(13)の表面に上部電極(14)を形成する上部電極形成工程
を順に有する、抵抗変化素子の製造方法。
5.
A lower electrode forming step for forming the lower electrode (12);
A variable resistance layer forming step of forming a variable resistance layer (13) made of an oxide containing praseodymium (Pr), calcium (Ca), and manganese (Mn) on the surface of the lower electrode (12);
Resistance change, comprising a reverse sputtering step of reverse sputtering the surface of the variable resistance layer (13) and an upper electrode formation step of forming an upper electrode (14) on the surface of the reverse-sputtered variable resistance layer (13). Device manufacturing method.

6.
前記逆スパッタリングにより酸素欠損層(25)が形成される、前記項5に記載の抵抗変化素子の製造方法。
6).
Item 6. The method for manufacturing a resistance change element according to Item 5, wherein the oxygen deficient layer (25) is formed by the reverse sputtering.

7.
下部電極(12)を形成する下部電極形成工程、
前記下部電極(12)の表面にプラセオジウム(Pr)、カルシウム(Ca)、マンガン(Mn)を含む酸化物よりなる抵抗変化層(13)を酸素雰囲気下で形成する抵抗変化層形成工程、
前記抵抗変化層(13)の表面に上部電極(14)を形成する上部電極形成工程
を順に有し、
前記抵抗変化層形成工程において、前記抵抗変化層(13)の表面となる部分を形成する際には酸素の濃度を減らす、抵抗変化素子の製造方法。
7).
A lower electrode forming step for forming the lower electrode (12);
A resistance change layer forming step of forming a resistance change layer (13) made of an oxide containing praseodymium (Pr), calcium (Ca), and manganese (Mn) on the surface of the lower electrode (12) in an oxygen atmosphere;
An upper electrode forming step of sequentially forming an upper electrode (14) on the surface of the variable resistance layer (13);
A method of manufacturing a resistance change element, wherein, in the resistance change layer forming step, the oxygen concentration is reduced when forming a portion to be a surface of the resistance change layer (13).

8.
前記酸素の濃度を減らした際に形成された前記抵抗変化層(13)の表面が酸素欠損層(25)となる、前記項7に記載の抵抗変化素子の製造方法。
8).
Item 8. The method for manufacturing a resistance change element according to Item 7, wherein the surface of the variable resistance layer (13) formed when the oxygen concentration is reduced becomes an oxygen deficient layer (25).

9.
下部電極(12)を形成する下部電極形成工程、
前記下部電極(12)の表面にプラセオジウム(Pr)、カルシウム(Ca)、マンガン(Mn)を含む酸化物よりなる抵抗変化層(13)を酸素雰囲気下で形成する抵抗変化層形成工程、
前記抵抗変化層(13)の表面に上部電極(14)を形成する上部電極形成工程
を順に有し、
前記抵抗変化層形成工程の開始直後において酸素の濃度を減らす、抵抗変化素子の製造方法。
9.
A lower electrode forming step for forming the lower electrode (12);
A resistance change layer forming step of forming a resistance change layer (13) made of an oxide containing praseodymium (Pr), calcium (Ca), and manganese (Mn) on the surface of the lower electrode (12) in an oxygen atmosphere;
An upper electrode forming step of sequentially forming an upper electrode (14) on the surface of the variable resistance layer (13);
A method of manufacturing a resistance change element, wherein the oxygen concentration is reduced immediately after the start of the resistance change layer forming step.

10.
前記酸素の濃度を減らした際に形成された部分の前記抵抗変化層(13)が酸素欠損層(25)となる、前記項9に記載の抵抗変化素子の製造方法。
10.
Item 10. The method for manufacturing a resistance change element according to Item 9, wherein the portion of the resistance change layer (13) formed when the oxygen concentration is reduced becomes an oxygen deficient layer (25).

11.
下部電極(12)を形成する下部電極形成工程、
前記下部電極(12)の表面にプラセオジウム(Pr)、カルシウム(Ca)、マンガン(Mn)を含む酸化物よりなる抵抗変化層(13)を形成する抵抗変化層形成工程、
前記抵抗変化層(13)の表面を不活性ガス雰囲気下でアニールするアニール工程、および
前記逆スパッタリングされた抵抗変化層(13)の表面に上部電極(14)を形成する上部電極形成工程
を順に有する、抵抗変化素子の製造方法。
11.
A lower electrode forming step for forming the lower electrode (12);
A variable resistance layer forming step of forming a variable resistance layer (13) made of an oxide containing praseodymium (Pr), calcium (Ca), and manganese (Mn) on the surface of the lower electrode (12);
An annealing process for annealing the surface of the variable resistance layer (13) in an inert gas atmosphere, and an upper electrode forming process for forming an upper electrode (14) on the surface of the reverse-sputtered variable resistance layer (13) are sequentially performed. A method of manufacturing a resistance change element.

12.
前記不活性ガス雰囲気下でアニールすることにより酸素欠損層(25)が形成される、前記項11に記載の抵抗変化素子の製造方法。
12
Item 12. The method for manufacturing a resistance change element according to Item 11, wherein the oxygen deficient layer (25) is formed by annealing in the inert gas atmosphere.

従来の構成における抵抗変化素子の構成概略図Schematic configuration diagram of variable resistance element in conventional configuration 本発明の実施の形態における抵抗変化素子の構成概略図Configuration schematic diagram of variable resistance element according to an embodiment of the present invention 本発明のメモリ構成素子の作成方法の図Diagram of a method for creating a memory component of the present invention 本発明のメモリ構成素子の作成方法の図Diagram of a method for creating a memory component of the present invention 本発明の実施例2における抵抗変化素子の構成概略図Configuration schematic diagram of variable resistance element in Example 2 of the present invention 本発明のメモリ構成素子の作成方法の図Diagram of a method for creating a memory component of the present invention

符号の説明Explanation of symbols

11 基板
12 下部電極
13 抵抗変化層
14 上部電極
25 酸素欠損層
36 絶縁膜
37 レジスト材
38 コンタクトホール

11 Substrate 12 Lower electrode 13 Variable resistance layer 14 Upper electrode 25 Oxygen deficient layer 36 Insulating film 37 Resist material 38 Contact hole

Claims (1)

プラセオジウム(Pr)、カルシウム(Ca)、マンガン(Mn)を含む酸化物よりなる抵抗変化層に電気的に接続された上部電極と下部電極とを備え、前記上部電極と前記下部電極との間に電気パルスを印加して前記抵抗変化層の抵抗を変化させる抵抗変化素子であって、
前記抵抗変化層と前記上部電極および前記下部電極の少なくとも一方との間に酸素欠損層を有する抵抗変化素子。
An upper electrode and a lower electrode electrically connected to a resistance change layer made of an oxide containing praseodymium (Pr), calcium (Ca), and manganese (Mn) are provided, and between the upper electrode and the lower electrode A variable resistance element that changes the resistance of the variable resistance layer by applying an electric pulse,
A variable resistance element having an oxygen deficient layer between the variable resistance layer and at least one of the upper electrode and the lower electrode.
JP2005007379A 2005-01-14 2005-01-14 Variable resistance element Pending JP2008060091A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005007379A JP2008060091A (en) 2005-01-14 2005-01-14 Variable resistance element
PCT/JP2006/300142 WO2006075574A1 (en) 2005-01-14 2006-01-10 Resistance change element and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005007379A JP2008060091A (en) 2005-01-14 2005-01-14 Variable resistance element

Publications (1)

Publication Number Publication Date
JP2008060091A true JP2008060091A (en) 2008-03-13

Family

ID=36677599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005007379A Pending JP2008060091A (en) 2005-01-14 2005-01-14 Variable resistance element

Country Status (2)

Country Link
JP (1) JP2008060091A (en)
WO (1) WO2006075574A1 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006324447A (en) * 2005-05-19 2006-11-30 Sharp Corp Nonvolatile memory element and its manufacturing method
JP2006344875A (en) * 2005-06-10 2006-12-21 Sharp Corp Method of manufacturing variable resistive element
JP2009130344A (en) * 2007-11-28 2009-06-11 Sony Corp Memory element and storage device
WO2010087000A1 (en) * 2009-01-30 2010-08-05 株式会社 東芝 Process for fabricating nonvolatile storage
JP2011165883A (en) * 2010-02-09 2011-08-25 Toshiba Corp Semiconductor memory device, and method of manufacturing the same
JP2012517102A (en) * 2009-02-04 2012-07-26 マイクロン テクノロジー, インク. Method of forming memory cell using gas cluster ion beam
US8471325B2 (en) 2008-03-28 2013-06-25 Kabushiki Kaisha Toshiba Nonvolatile memory device and method for manufacturing the same
KR101528094B1 (en) * 2011-06-10 2015-06-10 가부시키가이샤 아루박 Variable resistance element, and method for producing same

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008038365A1 (en) * 2006-09-28 2008-04-03 Fujitsu Limited Variable-resistance element
US8766224B2 (en) 2006-10-03 2014-07-01 Hewlett-Packard Development Company, L.P. Electrically actuated switch
JP4805865B2 (en) * 2007-03-19 2011-11-02 シャープ株式会社 Variable resistance element
JP2008309567A (en) * 2007-06-13 2008-12-25 Yamaha Corp Magnetic sensor and manufacturing method of the same
KR20140061468A (en) * 2007-06-29 2014-05-21 쌘디스크 3디 엘엘씨 Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US8233308B2 (en) 2007-06-29 2012-07-31 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US8295123B2 (en) 2007-07-18 2012-10-23 Panasonic Corporation Current rectifying element, memory device incorporating current rectifying element, and fabrication method thereof
JP5170107B2 (en) * 2007-12-07 2013-03-27 富士通株式会社 Resistance change type memory device, nonvolatile memory device, and manufacturing method thereof
CN101978496B (en) 2008-07-11 2012-11-07 松下电器产业株式会社 Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor device incorporating nonvolatile memory element
JP5476686B2 (en) * 2008-07-24 2014-04-23 富士通株式会社 Resistance change element and resistance change element manufacturing method
CN101836296B (en) * 2008-08-20 2012-09-19 松下电器产业株式会社 Resistance variable nonvolatile memory device and method for forming memory cell
JP5395799B2 (en) * 2008-09-12 2014-01-22 株式会社東芝 Nonvolatile memory device
KR101528657B1 (en) 2008-10-29 2015-06-12 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. Electrically actuated device and method of controlling the formation of dopants therein
CN102239557B (en) * 2008-12-03 2014-03-26 松下电器产业株式会社 Nonvolatile storage device and method for manufacturing the device
WO2010064410A1 (en) * 2008-12-04 2010-06-10 パナソニック株式会社 Nonvolatile memory element
WO2010064444A1 (en) * 2008-12-05 2010-06-10 パナソニック株式会社 Nonvolatile memory element and manufacturing method therefor
US8188833B2 (en) 2009-04-14 2012-05-29 Panasonic Corporation Variable resistance element and manufacturing method of the same
US8581225B2 (en) 2010-04-28 2013-11-12 Panasonic Corporation Variable resistance nonvolatile memory device and method of manufacturing the same
CN102782846B (en) * 2010-06-10 2015-05-20 松下电器产业株式会社 Non-volatile memory element and non-volatile memory device equipped with same
US9018083B2 (en) 2011-05-04 2015-04-28 Hewlett-Packard Development Company, L.P. Electrically actuated device and method of controlling the formation of dopants therein
CN103270592B (en) * 2011-10-24 2016-01-06 松下电器产业株式会社 Non-volatile memory device and Nonvolatile memory devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6927120B2 (en) * 2003-05-21 2005-08-09 Sharp Laboratories Of America, Inc. Method for forming an asymmetric crystalline structure memory cell
US6972238B2 (en) * 2003-05-21 2005-12-06 Sharp Laboratories Of America, Inc. Oxygen content system and method for controlling memory resistance properties
JP4460363B2 (en) * 2004-06-08 2010-05-12 シャープ株式会社 Semiconductor device and manufacturing method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006324447A (en) * 2005-05-19 2006-11-30 Sharp Corp Nonvolatile memory element and its manufacturing method
JP2006344875A (en) * 2005-06-10 2006-12-21 Sharp Corp Method of manufacturing variable resistive element
JP2009130344A (en) * 2007-11-28 2009-06-11 Sony Corp Memory element and storage device
US8471325B2 (en) 2008-03-28 2013-06-25 Kabushiki Kaisha Toshiba Nonvolatile memory device and method for manufacturing the same
WO2010087000A1 (en) * 2009-01-30 2010-08-05 株式会社 東芝 Process for fabricating nonvolatile storage
JP2012517102A (en) * 2009-02-04 2012-07-26 マイクロン テクノロジー, インク. Method of forming memory cell using gas cluster ion beam
US8614499B2 (en) 2009-02-04 2013-12-24 Micron Technology, Inc. Memory cell having heater material and variable resistance material embedded within insulating material
JP2011165883A (en) * 2010-02-09 2011-08-25 Toshiba Corp Semiconductor memory device, and method of manufacturing the same
KR101528094B1 (en) * 2011-06-10 2015-06-10 가부시키가이샤 아루박 Variable resistance element, and method for producing same
US9281477B2 (en) 2011-06-10 2016-03-08 Ulvac, Inc. Resistance change element and method for producing the same

Also Published As

Publication number Publication date
WO2006075574A1 (en) 2006-07-20

Similar Documents

Publication Publication Date Title
JP2008060091A (en) Variable resistance element
JP4857014B2 (en) Resistance change element and resistance change type memory using the same
CN100477225C (en) Resistance variable element and manufacturing method thereof
KR100672274B1 (en) RMAM memory cell electrode
EP1555693B1 (en) Method to produce a nonvolatile semiconductor memory device
US7580276B2 (en) Nonvolatile memory element
JP4829502B2 (en) Manufacturing method of semiconductor memory device
TWI292216B (en) Structure and manufacturing method of semiconductor memory device
JPWO2004008535A1 (en) Nonvolatile memory and manufacturing method thereof
US7473612B2 (en) Method for fabricating a variable-resistance element including heating a RMCoO3 perovskite structure in an oxygen atmosphere
JP2008021750A (en) RESISTANCE CHANGE ELEMENT, ITS MANUFACTURING METHOD, AND RESISTANCE CHANGE TYPE MEMORY USING THE SAME
TW200532898A (en) Method for manufacturing nonvolatile semiconductor memory device
JP2004273656A (en) Epir element and semiconductor device using the same
TW200830545A (en) Phase-change material layer and phase-change memory device including the phase-change material layer
US8410540B2 (en) Non-volatile memory device including a stacked structure and voltage application portion
JP2006080259A (en) Resistance change element, nonvolatile memory using the same, and manufacturing method thereof
JPWO2006013819A1 (en) Resistance change element and resistance change type memory using the same
KR101141008B1 (en) Phase-change memory element, phase-change memory cell, vacuum treatment device, and method for manufacturing phase-change memory element
JP2005311356A (en) Deposition method for non-volatile resistance switching memory
JP2005123361A (en) Resistance change type nonvolatile memory and its manufacturing method, and method of forming resistance change layer
JP4939414B2 (en) Variable resistance element
JP2010199348A (en) Semiconductor memory and method for manufacturing the same
WO2007055071A1 (en) Process for producing nonvolatile semiconductor memory device comprising variable resistive element
WO2010029645A1 (en) Nonvolatile storage device and method for manufacturing the same
JP2007088147A (en) Semiconductor device and manufacturing method thereof
点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载