JP2006163507A - Reference potential generating circuit and display device having the same - Google Patents

Abstract

A reference potential generation circuit capable of adjusting a reference potential while suppressing an increase in circuit scale and ensuring sufficient accuracy is provided.
A reference potential generating circuit includes a voltage dividing resistor array 10 composed of n + 1 resistor elements connected in series with each other and an adjustment resistor array 10a composed of 2 ^m +1 resistor elements connected in series with each other. Thin film transistors TFT (1) to TFT (2 ^m ) as 2 ^m switching elements respectively connected to 2 ^m connection points between the resistance elements in the adjustment resistor array 10a, and the first potential It has a first terminal T1 to which Va is applied and a second terminal T2 to which a second potential Vss is applied (Va> Vb). The voltage dividing resistor array 10 has one end connected to one end of the adjusting resistor array 10a and the other end connected to the second terminal T2, and the other end of the adjusting resistor array 10a connected to the first terminal T1. The source terminals of the thin film transistors TFT (1) to TFT (2 ^m ) are connected to the power supply line Lvdd.
[Selection] Figure 1

Description

  The present invention relates to a reference potential generation circuit that generates a reference potential by a voltage dividing resistor string composed of a plurality of resistance elements connected in series with each other, and more particularly, includes a circuit for adjusting a reference potential to be generated. The present invention relates to a reference potential generating circuit.

  Conventionally, a reference potential generating circuit that generates a desired reference potential by using a resistor string (voltage dividing resistor string) as a voltage dividing circuit composed of a plurality of resistance elements connected in series with each other has been used in various devices. . The reference potential to be generated in this reference potential generating circuit may need to be adjusted depending on circumstances peculiar to the device in which it is used.

  For example, when realizing a reset circuit that generates a reset signal only at the rise of a power supply in a semiconductor integrated circuit, a reference having a voltage dividing resistor array as described above to generate a reference potential to be compared with the power supply voltage. A potential generation circuit is used. In this case, it is necessary to adjust the reference potential to be generated by the voltage dividing resistor string in order to correct the element variation caused by the variation in the manufacturing process of the semiconductor integrated circuit. On the other hand, in Japanese Patent Laid-Open No. 5-346827, as a voltage adjustment circuit device for adjusting such a reference potential, as shown in FIG. 23, five resistors R1, R2, R3 connected in series are connected. An apparatus (hereinafter referred to as “first conventional example”) including voltage adjusting means comprising R4, R5 and transistors Tr1, Tr2, Tr3, Tr4 which are switching elements connected in series or in parallel to these transistors is disclosed. Has been. In this apparatus, correction data stored in an EEPROM (Electrically Erasable and Programmable Read Only Memory) 1 is read out by the control circuit 2, and a signal as correction data output from the control circuit 2 passes through a register 3 and is converted into a transistor Tr 1. Applied to the gate of .about.Tr4. Thereby, the on / off of the transistors Tr1 to Tr4 is controlled, whereby the resistance value of the voltage dividing resistor string is adjusted, and accordingly, the reference potential (resistors R4 and R5) to be compared with the power supply voltage V by the comparator 4 is adjusted. Is also adjusted.

Japanese Patent Laid-Open No. 3-247120 discloses a first switching element as shown in FIG. 24 in order to share a reference voltage generating circuit with a successive approximation A / D converter and a resistance voltage dividing D / A converter. A P-channel MOS (Metal Oxide Semiconductor) transistor 11, an N-channel MOS transistor 12 as a second switching element, seven resistance elements 3 having a resistance value R, and a resistance element having a resistance value R / 2 A reference voltage generating circuit (hereinafter referred to as “second conventional example”) configured to include 4 and 5 is disclosed. This reference potential generating circuit switches the reference voltage output obtained at each of the terminals 52 to 59 by setting the control signal 13 to the gates of the P channel MOS transistor 11 and the N channel MOS transistor 12 to a high level or a low level. Thus, it can be shared between the successive approximation A / D converter and the resistance voltage dividing D / A converter.
JP-A-5-346827 JP-A-3-247120

  As can be seen from the first and second conventional examples, in the conventional reference potential generating circuit, the connection relationship of the resistive elements in the voltage dividing resistor array for generating the reference voltage and the resistive elements introduced for adjustment are divided. The reference potential is adjusted by changing the connection relationship with the piezoresistive string by turning on / off a switching element such as a MOS transistor. Therefore, the value of the on-resistance (conducting resistance) of the switching element used for adjusting the reference potential is set as the resistance element constituting the voltage dividing resistor string for generating the reference potential or the resistance introduced for adjustment. It is necessary to make it sufficiently smaller than the resistance value of the element.

  When a MOS transistor is used as a switching element, as a method for reducing the on-resistance, an increase in channel width, a reduction in channel length, an increase in drive voltage, and the like are conceivable. Here, the channel length and the driving voltage are uniquely determined from the viewpoint of the manufacturing process of the MOS transistor and the system in which the reference potential generating circuit is used. Therefore, in order to reduce the on-resistance of the MOS transistor, the channel width is actually increased, which results in an increase in the element area.

  In addition, when the reference potential is adjusted using the switching element as described above in the conventional reference potential generation circuit, in order to generate the reference potential with high accuracy, it is necessary to minimize the variation in the on-resistance of the switching element. There is. However, for example, when a gradation voltage generation circuit or the like as a reference potential generation circuit is formed on a substrate constituting a liquid crystal panel or the like as a reference potential generation circuit by a thin film transistor, the thin film transistor as an adjustment switching element is turned on. Due to the variation in resistance, sufficient accuracy cannot be ensured in the generation of the reference potential.

  Therefore, an object of the present invention is to provide a reference potential generation circuit capable of adjusting a reference potential while suppressing an increase in circuit scale and ensuring sufficient accuracy.

The first invention has a resistor string composed of a plurality of resistor elements connected in series with each other, and a first predetermined potential is applied to one end of the resistor array and a second predetermined potential is applied to the other end. A reference potential generating circuit for generating a reference potential by resistance voltage division,
A switching element provided corresponding to at least one connection point between the resistance elements constituting the resistance string;
The at least one connection point is connected to a power line via the corresponding switching element;
The reference potential is adjusted by turning on / off the switching element.

The second invention has a resistor string composed of a plurality of resistor elements connected in series to each other, and a first predetermined potential is applied to one end of the resistor array and a second predetermined potential is applied to the other end. A reference potential generating circuit,
The resistor string is
A voltage dividing resistor string for generating a reference potential;
An adjustment resistor string for adjusting the reference potential,
A switching element is provided corresponding to at least one connection point between the resistance elements constituting the adjustment resistor string,
The at least one connection point is connected to a power line via the corresponding switching element;
One end of the voltage dividing resistor string is connected to one end of the adjusting resistor string,
The voltage dividing resistor string generates the reference potential based on the first and second predetermined potentials and on / off of the switching element.

According to a third invention, in the second invention,
A resistor element inserted between the connection point between the resistor elements constituting the adjustment resistor string and the power supply line so as to be connected in series with the switching element corresponding to the connection point; Features.

4th invention is 2nd or 3rd invention,
The first predetermined potential is higher than the second predetermined potential;
A potential of the power supply line is higher than the first predetermined potential.

A fifth invention is the second or third invention, wherein
The first predetermined potential is lower than the second predetermined potential;
A potential of the power supply line is lower than the first predetermined potential.

The sixth invention has a resistor string composed of a plurality of resistance elements connected in series to each other, and a first predetermined potential is applied to one end of the resistor array and a second predetermined potential is applied to the other end. A reference potential generating circuit,
The resistor string is
A voltage dividing resistor string for generating a reference potential;
And first and second adjustment resistor strings for adjusting the reference potential,
A first switching element is provided corresponding to at least one connection point between the resistance elements constituting the first adjustment resistor string;
A second switching element is provided corresponding to at least one connection point between the resistance elements constituting the second adjustment resistor string;
One end of the voltage dividing resistor string is connected to one end of the first adjusting resistor string,
The other end of the voltage dividing resistor string is connected to one end of the second adjusting resistor string,
The other end of the first adjustment resistor string is given the first predetermined potential,
The other end of the second adjustment resistor string is given the second predetermined potential,
A connection point between the resistance elements constituting the first adjustment resistor string is connected to the first power supply line via the corresponding first switching element,
The connection point between the resistance elements constituting the second adjustment resistor string is connected to the second power supply line via the corresponding second switching element,
The voltage dividing resistor string generates the reference potential based on the first and second predetermined potentials and the on / off states of the first and second switching elements.

A seventh invention is the sixth invention, wherein
Inserted between a connection point between the resistance elements constituting the first adjustment resistor string and the first power supply line so as to be connected in series with the first switching element corresponding to the connection point. It is further characterized by further comprising a resistance element.

In an eighth aspect based on the sixth aspect,
Inserted between the connection point between the resistance elements constituting the second adjustment resistor string and the second power supply line so as to be connected in series with the second switching element corresponding to the connection point It is further characterized by further comprising a resistance element.

According to a ninth invention, in any of the sixth to eighth inventions,
The second predetermined potential is higher than the potential of the second power supply line,
The first predetermined potential is higher than the second predetermined potential;
A potential of the first power supply line is higher than the first predetermined potential.

According to a tenth invention, in any one of the first to ninth inventions,
A first power source for generating the first predetermined potential;
And a second power source for generating the second predetermined potential.

An eleventh aspect of the invention is any one of the first to ninth aspects of the invention,
A constant voltage circuit including a Zener diode having a breakdown voltage corresponding to the first predetermined potential, and generating the first predetermined potential based on the breakdown voltage;
And a second power source for generating the second predetermined potential.

In a twelfth aspect of the invention, any one of the first to ninth aspects of the invention,
A first power source for generating the first predetermined potential;
A zener diode having a breakdown voltage corresponding to the second predetermined potential, and further comprising a constant voltage circuit for generating the second predetermined potential based on the breakdown voltage.

In a thirteenth invention according to any one of the first to ninth inventions,
A first constant voltage circuit including a Zener diode having a breakdown voltage corresponding to the first predetermined potential, and generating the first predetermined potential based on the breakdown voltage;
And a second constant voltage circuit including a Zener diode having a breakdown voltage corresponding to the second predetermined potential, and generating the second predetermined potential based on the breakdown voltage.

A fourteenth invention is a display device,
A reference potential generating circuit according to any one of the first to thirteenth inventions is provided.

According to a fifteenth aspect, a plurality of pixel forming portions for forming an image to be displayed and a plurality of data signals that are analog voltage signals representing the image to be displayed are transmitted to the plurality of pixel forming portions. A data signal line driving circuit of a display device including a plurality of data signal lines,
A reference voltage generation circuit according to any one of the first to thirteenth aspects includes a gradation voltage generation circuit that generates a plurality of gradation voltages, and generates the plurality of data signals based on the plurality of gradation voltages. It is characterized by doing.

In a sixteenth aspect of the invention, a plurality of pixel forming portions for forming an image to be displayed and a plurality of video signals that are analog voltage signals representing the image to be displayed are transmitted to the plurality of pixel forming portions. In a display device comprising a data signal line and a data signal line driving circuit for sequentially applying the video signal to the plurality of data signal lines, a digital video signal input from the outside as a signal representing the image to be displayed A video circuit for generating the video signal based on:
A reference voltage generation circuit according to any one of the first to thirteenth aspects includes a gradation voltage generation circuit that generates a plurality of gradation voltages, and the digital video signal is converted into an analog voltage based on the plurality of gradation voltages. The video signal is generated by converting into a signal.

A seventeenth aspect of the invention is a clock signal generation circuit for generating a high amplitude clock signal from a low amplitude clock signal,
A reference potential generation circuit according to any one of claims 1 to 13,
And a comparator for generating the high-amplitude clock signal by comparing the potential of the low-amplitude clock signal with the reference potential generated by the reference potential generation circuit.

  According to the first aspect of the invention, compared to the resistance value from the connection point connected to the power supply line through the switching element among the connection points between the resistance elements constituting the resistance string to one end or the other end of the resistance string. The on-resistance of the switching element can be set to be sufficiently large. Further, if the on-resistance of the switching element is set to be sufficiently large, the influence on the reference potential due to the variation of the on-resistance is reduced. Accordingly, it is possible to adjust the reference potential by setting the switching element on / off while suppressing a decrease in accuracy of the reference potential. In addition, since the on-resistance of the switching element can be set sufficiently high, the circuit scale of the reference potential generating circuit can be reduced.

  In the second aspect of the invention, one end of the adjustment resistor string is connected to the voltage dividing resistor string, and the first predetermined potential is applied to the other end. Thus, by setting the on-resistance of the switching element to be sufficiently larger than the resistance value of the adjustment resistor string, it is connected to the power supply line via the switching element that is turned on among the connection points between the resistance elements in the adjustment resistor string. The potential of the connection point to be connected can be made approximately equal to the first predetermined potential. According to such setting, the reference potential is mainly determined by the resistance values of the voltage dividing resistor string and the adjusting resistor string, and the on-resistance of the switching element is not directly related. The influence on the reference potential is also reduced. Therefore, it is possible to provide a reference potential generation circuit capable of adjusting the reference potential while suppressing an increase in circuit scale and ensuring sufficient accuracy.

  According to the third aspect of the invention, the resistance element is inserted between the connection point between the resistance elements constituting the adjustment resistor string and the power supply line so as to be connected in series with the switching element corresponding to the connection point. Therefore, even if the on-resistance of the switching element is not sufficiently high, the same effect as that of the second invention can be obtained.

  In the fourth aspect, the reference potential is generated mainly according to the difference between the first predetermined potential and the second predetermined potential, and the reference potential is adjusted by turning on / off the switching element connected to the power supply line. . The potential of the power supply line is higher than the first predetermined potential. This is advantageous for switching operation when, for example, a P-channel transistor is used as a switching element. Therefore, the reference potential is adjusted by turning on / off the switching element. It can be done well.

  Also in the fifth aspect, the reference potential is generated mainly in accordance with the difference between the first predetermined potential and the second predetermined potential, and the reference potential is adjusted by turning on / off the switching element connected to the power supply line. The The potential of the power supply line is lower than the first predetermined potential. This is advantageous for switching operation when, for example, an N-channel transistor is used as a switching element. Therefore, the reference potential is adjusted by turning on / off the switching element. It can be done well.

  According to the sixth invention, the first and second adjustment resistor strings and the first and second switching elements corresponding to the first and second adjustment resistor strings have the same effect as the second invention, and the circuit scale is increased. It is possible to provide a reference potential generation circuit that can suppress the reference potential and adjust the reference potential while ensuring sufficient accuracy. In addition, the reference potential can be adjusted in a wider range by controlling on / off of both the first and second switching elements.

  According to the seventh aspect, the switching element corresponding to the connection point is connected in series between the connection point between the resistance elements constituting the first adjustment resistor string and the first power supply line. Thus, even if the on-resistance of the first switching element is not sufficiently high, the same effect as in the sixth invention can be obtained.

  According to the eighth aspect, the switching element corresponding to the connection point is connected in series between the connection point between the resistance elements constituting the second adjustment resistor string and the second power supply line. Thus, even if the on-resistance of the second switching element is not sufficiently high, the same effect as that of the sixth invention can be obtained.

  According to the ninth aspect, the reference potential is generated mainly in accordance with the difference between the first predetermined potential and the second predetermined potential, and the first and second power sources connected to the first and second power supply lines, respectively. The reference potential is adjusted by turning on / off the two switching elements. Here, the potential of the first power supply line is higher than the first predetermined potential, and the potential of the second power supply line is lower than the second predetermined potential. As in the fourth and fifth inventions, Since it works advantageously in the switching operation, the reference potential can be adjusted well by turning on / off the switching element.

  According to the tenth aspect of the invention, the first predetermined potential is applied by the first power supply, and the second predetermined potential is applied by the second power supply. Play.

  According to the eleventh invention, since the first predetermined potential is applied by the constant voltage circuit using the Zener diode, the same effects as those of the first to ninth inventions can be obtained while reducing the number of power supplies.

  According to the twelfth invention, since the second predetermined potential is applied by the second constant voltage circuit using a Zener diode, the same effects as those of the first to ninth inventions can be obtained while reducing the number of power supplies. Can do.

  According to the thirteenth invention, since the first and second predetermined potentials are given by the first and second constant voltage circuits using a Zener diode, the first to ninth inventions are further reduced while further reducing the number of power supplies. The same effect can be obtained.

  According to the fourteenth aspect of the present invention, in the reference potential generating circuit used for generating the gradation voltage required for the display device, an increase in circuit scale is suppressed and the on-resistance of the switching element is varied. Therefore, it is possible to adjust the reference potential while ensuring sufficient accuracy. Therefore, the present invention is effective when a reference potential generation circuit as a gradation voltage generation circuit is formed by a thin film transistor integrally with a display portion on a substrate constituting a liquid crystal panel or the like.

  According to the fifteenth aspect of the present invention, in the reference potential generating circuit used for generating the gradation voltage required in the data signal line driving circuit of the display device, an increase in circuit scale is suppressed and the switching element is turned on. Regardless of the variation in resistance, the reference potential can be adjusted while ensuring sufficient accuracy. Therefore, the present invention is effective when a data signal line driving circuit is formed of a thin film transistor integrally with a display portion on a substrate constituting a liquid crystal panel or the like.

  According to the sixteenth aspect of the present invention, in the reference potential generating circuit used for generating the gradation voltage required in the video circuit of the display device, an increase in circuit scale is suppressed and the on-resistance variation of the switching element is varied. Regardless of this, the reference potential can be adjusted while ensuring sufficient accuracy. Therefore, the present invention is effective when a video circuit is formed of a thin film transistor integrally with a display portion on a substrate constituting a liquid crystal panel or the like.

  According to the seventeenth aspect, the generated reference potential can be adjusted in accordance with the offset voltage caused by the variation in the transistors constituting the comparator operating as the level shifter, the variation in the level of the low-amplitude clock signal, and the like. it can. In addition, it is possible to adjust the reference potential while suppressing an increase in circuit scale in the reference potential generation circuit and ensuring sufficient accuracy regardless of variations in the on-resistance of the switching elements.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
<1.1 Configuration and operation>
FIG. 1 is a circuit diagram showing a configuration of a reference potential generating circuit according to the first embodiment of the present invention. As will be described later, this reference potential generation circuit is realized by using a thin film transistor as a switching element, for example, for generating a gradation voltage on a substrate constituting a liquid crystal panel or the like. However, the present invention is not limited to this. For example, it may be realized by using a MOS transistor or the like as a switching element in an IC (Integrated Circuit) chip.

As shown in FIG. 1, this reference potential generating circuit is for voltage division comprising n + 1 resistance elements R (1), R (2),..., R (n), R (n + 1) connected in series with each other. Resistor string 10 and adjusting resistor string 10a composed of 2 ^m +1 resistor elements Ra (1), Ra (2), ..., Ra (2 ^m ), Ra (2 ^m +1) connected in series with each other If, 2 ^m pieces of P-channel thin-film transistor TFT as 2 ^m pieces of switching elements connected respectively to the connection point (hereinafter referred to as "adjustment switching element") between the resistive elements constituting the adjusting resistor array 10a (1 ), TFT (2),..., TFT (2 ^m ), and as a terminal to which a predetermined potential is to be applied from the outside, a first terminal T1 to which a first potential Va is to be applied and a second potential Vss. And a second terminal T2 to provide 2 ^m control terminals Tc (1), Tc (2),..., Tc (2 ^m ) as terminals to which a control signal for adjusting the power reference potential is to be supplied (where m and n Is a natural number. The voltage dividing resistor array 10 has one end connected to one end of the adjustment resistor array 10a and the other end connected to the second terminal T2. The other end of the adjustment resistor row 10a is connected to the first terminal T1. The 2 ^m transistors TFT (1) to TFT (2 ^m ) constituting the adjustment switching element group have drain terminals at 2 ^m connection points between the resistance elements in the adjustment resistor array 10a. These source terminals are connected to the power supply line Lvdd, and their gate terminals are connected to the control terminals Tc (1) to Tc (2 ^m ), respectively.

  When the reference potential generating circuit configured as described above is operated, the first potential Va is supplied from the predetermined power source to the first terminal T1, and the second potential Vss is supplied to the second terminal T2 from the predetermined power source. Or the second terminal T2 is grounded (see FIG. 2). In the present embodiment, the first potential Va is higher than the second potential Vss, and the potential Vdd of the power supply line Lvdd to which the adjustment switch element group is connected is higher than the first potential Va (the power supply line Lvdd The potential Vdd may be lower than the first potential Va, but it is preferable that the potential Vdd is higher than the first potential Va for the operation of the P-channel transistors constituting the adjustment switch element group. Further, in order to give the first potential Va to the first terminal T1, a constant voltage circuit that generates the first potential Va using the Zener diode Dz as shown in FIG. 3 is used instead of the power source. Also good. This constant voltage circuit includes a Zener diode Dz whose anode is grounded, and a resistance element Rcv having one end connected to the power supply line Lvdd and the other end connected to the cathode of the Zener diode Dz. The Zener diode Dz and the resistance element Rcv Is connected to the first terminal T1 in the reference potential generating circuit. According to such a configuration, by using a Zener diode whose breakdown voltage is equal to the first potential Va as the Zener diode Dz, the first terminal T1 in the reference potential generation circuit can be connected to the reference potential generating circuit without preparing a separate power source. The first potential Va can be applied. When the breakdown voltage of one Zener diode is lower than the first potential Va to be applied to the first terminal T1, a plurality of Zener diodes are connected in series with each other and the sum of the breakdown voltages is the first. It may be made equal to the potential Va of 1 (the same applies to other embodiments and modifications described below).

On the other hand, 2 ^m pieces of control terminal Tc (1) to any one of to Tc (2 ^m) is given a low-level signal, a high level signal is applied to the other control terminal. As a result, only the P-channel transistor (of the gate terminal) connected to the control terminal to which the low level signal is given is turned on in the adjustment switching element group (hereinafter, the transistor in the on state is referred to as “ON transistor”. ”), Only the connection point to which the ON transistor is connected among the connection points between the resistance elements in the adjustment resistor array 10a is electrically connected to the power supply line Lvdd via the ON transistor. Since the number of P-channel transistors constituting the adjustment switching element group and the number of control terminals to which signals for controlling on / off thereof are 2 ^m are given, if an m-bit selection signal is given, Only any one P-channel transistor constituting the adjustment switching element group can be turned on. Specifically, a decoder may be provided which receives an m-bit selection signal as an input and outputs a signal to be given to each of the control terminals Tc (1) to Tc (2 ^m ) as a control signal.

In the present embodiment, as described above, the first potential Va is applied to the first terminal T1, and the second potential Vss is applied to the second terminal T2, respectively. The control is performed by the m-bit selection signal as described above. Only one of the terminals Tc (1) to Tc (2 ^m ) is given a low level signal, and the other control terminals are given a high level signal. Thereby, based on the first potential Va and the second potential Vss and the resistance values of the resistance elements R (1) to R (n + 1) constituting the voltage dividing resistor array 10, the connection point between the resistance elements is determined. The potentials are determined, and these potentials are output as reference potentials Vref (1) to Vref (n). As shown in FIG. 1, an adjustment resistor string 10a is connected between the first terminal T1 and the voltage dividing resistor string 10, and the resistance elements Ra (1) to Ra (R) in the adjustment resistor string 10a are connected. since between 2 ^m +1) connection point between the power supply line Lvdd adjustment switching element ^{TFT (1) ~TFT (2 m} ) are connected, the reference voltage Vref generated as described above ( 1) to Vref (n) are the resistance values of the resistance elements Ra (1) to Ra (2 ^m +1) in the adjustment resistor string 10a and the positions of the ON transistors in the adjustment switching element group (this is the selection of the above m bits) Depends on the signal). Therefore, the reference potentials Vref (1) to Vref (n) output from the voltage dividing resistor array 10 can be adjusted by changing the ON transistor in the adjustment switching element group according to the selection signal.

  In the configuration shown in FIG. 1, a constant voltage circuit using a power supply or a Zener diode for supplying the first and second potentials Va and Vss to the first and second terminals T1 and T2, respectively, or an adjustment switching element A decoder or the like for generating a control signal to be given to the group is not included in the reference potential generation circuit, but may be included in the reference potential generation circuit (in this regard, other embodiments and modifications described below) The same applies to.

FIG. 4 shows output characteristics when the ON transistor is changed in the reference potential generating circuit according to the present embodiment. In FIG. 4, a straight line CL (1) is a straight line connecting points indicating the reference potentials Vref (1) to Vref (n) when the transistor TFT (1) farthest from the voltage dividing resistor array 10 is an ON transistor. The straight line CL (2 ^m ) is a straight line connecting points indicating the reference potentials Vref (1) to Vref (n) when the transistor TFT (2 ^m ) closest to the voltage dividing resistor array 10 is an ON transistor. is there. Therefore, by changing the ON transistor in the adjustment switching element group by setting the m-bit selection signal, each reference potential Vref (in the range sandwiched between these two straight lines CL (1) and CL (2 ^m ). 1) to Vref (n) can be adjusted.

<1.2 Simulation>
As described above, in this embodiment, the reference potentials Vref (1) to Vref (n) output from the voltage dividing resistor string 10 can be adjusted by changing the ON transistor in the adjustment switching group. In the case of the configuration in which the reference potential is adjusted by turning on / off the switching element as in this embodiment, variation in the on-resistance of the switching element affects the reference potential. It is preferable to reduce the influence of resistance variation as much as possible. Therefore, in order to investigate the influence on the reference potential (the influence on the output characteristics) due to the variation in the ON resistance of the switching element for adjustment, the inventor of the present application and the reference potential generation circuit corresponding to the first embodiment and the first A computer simulation was performed on the conventional reference potential generation circuit corresponding to the first embodiment.

  FIG. 5A shows a circuit configuration corresponding to the present embodiment (hereinafter referred to as “first circuit configuration”) among the circuit configurations targeted for the simulation. The first circuit configuration includes one resistor element of 5.6 kΩ corresponding to the voltage dividing resistor string 10, a resistor string consisting of ten resistor elements of 18Ω corresponding to the adjusting resistor string 10a, and these Thin film transistors TFT (1) to TFT (9) as nine switching elements respectively connected between nine connection points between the resistance elements and an 8V power supply line, and an adjustment resistor array 10a The potential at the connection point between the resistor string composed of 10 resistor elements corresponding to 18Ω and the resistor element corresponding to 5.6 kΩ corresponding to the voltage dividing resistor string is output as a reference potential. Further, 3.0V is applied as the first potential, and 0V is applied as the second potential (a terminal corresponding to the second terminal T2 is grounded). The on-resistance Ron1 of the thin film transistors TFT (1) to TFT (9) is 8 kΩ ± 10% (variation is ± 10% around 8 kΩ).

  FIG. 5B shows a circuit configuration corresponding to a conventional reference potential generating circuit (hereinafter referred to as “second circuit configuration”) among the circuit configurations targeted for this simulation. The second circuit configuration includes a resistor string composed of an 8 kΩ resistor element corresponding to a voltage dividing resistor string and a 5.15 kΩ resistor element, and a resistor string composed of nine 50 Ω resistor elements corresponding to an adjusting resistor string. Thin film transistors TFT (1) to TFT (9) as nine switching elements respectively connected between nine connection points between these resistance elements and an 8V power supply line. The potential at the connection point between the 8 kΩ resistor element and the 5.15 kΩ resistor element constituting the pressure resistor string is output as the reference potential. The voltage dividing resistor string has one end connected to one end of the adjusting resistor string and the other end grounded. Unlike the first circuit configuration, the other end of the adjusting resistor string is externally connected. No potential is applied. It is assumed that the on-resistance Ron2 of the thin film transistors TFT (1) to TFT (9) constituting the adjustment switching element group is 500Ω ± 10%.

  FIGS. 6A and 6B are diagrams showing the results of the simulation. Among these, FIG. 6A shows a change in the output voltage as the reference potential when the ON transistor is changed in the adjustment switching element group. In FIG. 6A, “◯” indicates the output voltage in the first circuit configuration corresponding to the present embodiment, and “X” indicates the output voltage in the second circuit configuration corresponding to the conventional example. . The solid line shows the change in the output voltage (reference potential) when the ON transistor is changed when the ON resistance is the original set value (18Ω in the first circuit configuration, 50Ω in the second circuit configuration). The chain line shows a change in the output voltage (reference potential) when the ON transistor is changed when the on-resistance is 10% smaller than the original set value, and the dotted line shows a 10% larger on-resistance than the original set value. In the case of the value, the change in the output voltage (reference potential) when the ON transistor is changed is shown.

  According to such a simulation result shown in FIG. 6A, in both the first and second circuit configurations, the output voltage is about 90 mV of 2.92 V to 3.01 V by changing the ON transistor. (Hereinafter referred to as “adjustment range”). The fluctuation range of the output voltage due to the variation when the on-resistance varies by 10% (hereinafter referred to as “error width”) is, according to the first circuit configuration corresponding to this embodiment, the first corresponding to the conventional example. It is reduced as compared with the case of the circuit configuration of 2. That is, the error width of the output voltage due to the variation of the ON resistance by 10% is as shown in FIG. 6B according to the change of the ON transistor. This corresponds to the present embodiment, whereas the error width of the output voltage due to the 10% variation in the on-resistance is about 20 mV over the adjustment range in the second circuit configuration corresponding to the conventional example. The first circuit configuration indicates that the adjustment range is approximately 3 mV to 19 mV. Thus, according to this simulation, it can be seen that in this embodiment, the error width of the output voltage due to variations in the on-resistance of the adjustment switching element is reduced.

  When the adjustment switching element is realized by a thin film transistor, the second circuit configuration corresponding to the conventional example has an on-resistance of 500Ω and a channel width of several hundreds μm to several thousand μm. In the corresponding first circuit configuration, the on-resistance is 8 kΩ and the channel width is several μm to several tens μm. Therefore, this embodiment is much more advantageous than the conventional example in terms of circuit area for realization. In the second circuit configuration corresponding to the conventional example (FIG. 5B), when the ON resistance of the thin film transistor as the adjustment switching element is reduced from 500Ω to about 100Ω to 200Ω, the ON resistance variation (10% ) Is smaller than that in the first configuration example corresponding to the present embodiment. However, in this case, the channel width of the thin film transistor as the switching element in the second circuit configuration is about several mm to 10 mm, which is impractical.

<1.3 Effect>
As described above, in the present embodiment, as shown in FIG. 1, the adjustment resistor string 10a has one end connected to the voltage dividing resistor string 10 and the other end connected to the first terminal T1, A first potential Va is applied to the first terminal T1 from an external power source or a constant voltage circuit using a Zener diode. Thus, the resistance in the adjustment resistor row 10a is set by setting the on-resistance of each of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching device sufficiently larger than the resistance value of the adjustment resistor row 10a. Of the connection points between the elements, the potential at the point where the ON transistor, which is one of the adjustment switch elements, is connected (hereinafter referred to as “ON transistor connection point”) can be made substantially equal to the first potential Va (however, (It is assumed that the resistance value of the voltage dividing resistor string 10 is sufficiently larger than the resistance value of the adjusting resistor string 10a). For example, in the first circuit configuration as the object of the simulation, as shown in FIG. 5A, the on-resistances of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching elements are 8 kΩ ± 10 %, Which is sufficiently larger than 18Ω × 10 = 180Ω, which is the resistance value of the entire adjustment resistor row 10a (in this example, the resistance value (5.6 kΩ) of the voltage dividing resistor row 100 is also higher than that of the adjustment resistor row 10a. It is sufficiently larger than the resistance value (180Ω). According to such a setting, the resistor string between the ON transistor connection point and the second terminal T2 to which the second potential Vss is to be applied, that is, the connection point of the ON transistor TFT (j) and the voltage dividing resistor string 10 The reference potentials Vref (1) to Vref (n) as output voltages are determined by a resistor string obtained by adding the adjusting resistor elements Ra (j + 1) to Ra (2 ^m +1) to the voltage dividing resistor string 10 (Where j is a natural number of 2 ^m or less). Therefore, the reference potentials Vref (1) to Vref (n) can be adjusted by changing the ON transistors in the switching element group according to the selection signal.

With the above configuration, the on-resistance of each of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching element is set to a larger value than the on-resistance of the adjustment switching element in the conventional reference potential generation circuit. The Therefore, as is clear from the above description regarding the comparison between the first circuit configuration and the second circuit configuration as the object of the above simulation, the reference potential generation circuit according to the present embodiment has a conventional reference potential. Compared with the generation circuit, the circuit area required for realization can be reduced.

In addition, according to the present embodiment, the voltage dividing resistor string 10 is connected to one end of the adjusting resistor string 10a, and the first potential Va is applied to the other end by a power source or a constant voltage circuit to generate a reference potential. Therefore, the on-resistances of the adjustment switching elements TFT (1) to TFT (2 ^m ) are not directly included in the resistance string (voltage dividing resistor string 10 and adjustment resistor string 10a). For this reason, the influence on the reference potential due to the variation in the on-resistance of each of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching element is reduced. As a result, as is apparent from the simulation results described above, according to the present embodiment, the fluctuation range (error width) of the output voltage due to the variation in on-resistance is reduced, so that the conventional reference having the adjustment switching element is used. The reference potential can be generated with higher accuracy than the potential generation circuit.

  According to the present embodiment, the generated reference potentials Vref (1) to Vref (n) mainly divide the potential difference between the first potential Va and the second potential Vss by the voltage dividing resistor array 10. Therefore, when it is desired to greatly change the reference potential instead of a relatively small reference potential change by the adjustment resistor array 10a and the adjustment switching element, one of the first potential Va and the second potential Vss or Change both sides. Therefore, according to the present embodiment, the generated reference potential can be easily changed as compared with the conventional case.

<1.4 Modification>
Hereinafter, various modifications of the first embodiment will be described. In the following, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

FIG. 7 is a circuit diagram showing a configuration of a first modification of the first embodiment. In this modification, N-channel thin film transistors are used instead of P-channel thin film transistors as the thin film transistors TFT (1) to TFT (2 ^m ) constituting the adjustment switching element group, and the control terminals Tc (1) to Tc are correspondingly used. Only one of (2 ^m ) is given a high level signal, and the other control terminals are given a low level signal. An N-channel thin film transistor connected to a control terminal having a high level (a gate terminal) becomes an ON transistor. Other configurations in this modification are the same as those in the first embodiment. Also by this modification, the same effect as that of the first embodiment can be obtained. When the potential Vdd of the power supply line Lvdd to which the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching elements are connected is higher than the first potential Va, as in the first embodiment. Use of a P-channel transistor as the adjustment switching element is preferable in terms of operation as a switching element. However, when the potential Vdd of the power supply line Lvdd is lower than the first potential Va, an N-channel is used as the adjustment switching element. It is preferable to use a transistor.

FIG. 8 is a circuit diagram showing a configuration of a second modification of the first embodiment. In this modification, the thin film transistors TFT (1) to TFT (2 ^m ) constituting the adjustment switching element group between 2 ^m connection points between the resistance elements in the adjustment resistor row 10a and the power supply line Lvdd. Is different from the first embodiment in that resistance elements Rc (1) to Rc (2 ^m ) are inserted in series. As described above, in the first embodiment, the on-resistances of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching elements are sufficiently larger than the resistance value of the adjustment resistor array 10a. However, when the on-resistance of the thin film transistor actually formed as the adjustment switching element is not sufficiently high, the thin film transistors TFT (1) to TFT (2 ^m ) are connected in series as in this modification. What is necessary is just to set it as the structure which inserts a resistive element. As a result, the same effects as those of the first embodiment can be obtained even in a configuration in which the on-resistances of the thin film transistors TFT (1) to TFT (2 ^m ) are not sufficiently large.

FIG. 9 is a circuit diagram showing a configuration of a third modification of the first embodiment. In this modification, in the first modification shown in FIG. 7, an adjustment switching element group is configured between 2 ^m connection points between the resistance elements in the adjustment resistor array 10a and the power supply line Lvdd. each thin film transistor ^{TFT (1) ~TFT (2 m} ) and a resistor in series with element ^{Rc (1) ~Rc (2 m} ) is in the inserted configuration for. When the on-resistance of the thin film transistor actually formed as the adjustment switching element is not sufficiently large, the on-resistance of the thin film transistors TFT (1) to TFT (2 ^m ) is inserted by inserting a resistance element as in this modification. Even in a configuration in which is not sufficiently large, the same effect as in the first embodiment can be obtained.

<2. Second Embodiment>
<2.1 Configuration and operation>
FIG. 10 is a circuit diagram showing a configuration of a reference potential generating circuit according to the second embodiment of the present invention. This reference potential generation circuit is also realized by using a thin film transistor as a switching element, for example, for generating a gradation voltage on a substrate constituting a liquid crystal panel or the like, but is not limited to such an application or an implementation method. For example, it may be realized by using a MOS transistor or the like as a switching element in the IC chip. In the configuration of this embodiment, the same or corresponding parts as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 10, this reference potential generating circuit is for voltage division comprising n + 1 resistance elements R (1), R (2),..., R (n), R (n + 1) connected in series. Resistor string 10 and adjusting resistor string 10b composed of 2 ^m +1 resistor elements Rb (1), Rb (2), ..., Rb (2 ^m ), Rb (2 ^m +1) connected in series with each other When, N-channel thin-film transistor TFT as 2 ^m pieces of adjustment switching elements connected respectively to 2 ^m pieces of connection points between the resistor elements constituting the adjusting resistor array 10b (1), TFT (2 ), ... , TFT (2 ^m ), and a first terminal T1 to which a first potential Vb is to be applied and a second terminal T2 to which a second potential Vdd is to be applied as terminals to which a predetermined potential is to be applied from the outside. Control for adjusting the reference potential to be generated There are 2 ^m control terminals Td (1), Td (2),..., Td (2 ^m ) as terminals to which signals are to be applied. The voltage dividing resistor array 10 has one end connected to one end of the adjusting resistor array 10b and the other end connected to the second terminal T2. The other end of the adjustment resistor row 10b is connected to the first terminal T1. The 2 ^m transistors TFT (1) to TFT (2 ^m ) constituting the adjustment switching element group have their drain terminals connected to connection points between the resistance elements in the adjustment resistor row 10b, respectively. Are connected to a power supply line (low-voltage power supply line or ground line) Lvss, and their gate terminals are connected to the control terminals Td (1) to Td (2 ^m ), respectively.

  When operating the reference potential generating circuit configured as described above, the first potential Vb is supplied from the predetermined power source to the first terminal T1, and the second potential Vdd is supplied to the second terminal T2 from the predetermined power source. Given by. In the present embodiment, the first potential Vb is lower than the second potential Vdd, and the potential Vss of the power supply line Lvss to which the adjustment switch element group is connected is lower than the first potential Vb (the power supply line Lvss Although the potential Vss may be higher than the first potential Vb, it is preferable that the potential Vss is lower than the first potential Vb in the operation of the N-channel transistors constituting the adjustment switch element group. Further, in order to apply the first potential Vb to the first terminal T1, a constant voltage circuit that generates the first potential Vb using the Zener diode Dz2 as shown in FIG. 11 is used instead of the power source. Also good. This constant voltage circuit includes a Zener diode Dz2 whose anode is grounded, and a resistance element Rcv2 whose one end is connected to the power supply line (predetermined power supply) of the second potential Vdd and the other end is connected to the cathode of the Zener diode Dz2. Thus, the connection point between the Zener diode Dz2 and the resistance element Rcv2 is connected to the first terminal T1 in the reference potential generation circuit. According to such a configuration, a Zener diode having a breakdown voltage equal to the first potential Vb is used as the Zener diode Dz2, so that the first terminal T1 in the reference potential generating circuit can be connected to the reference potential generating circuit without preparing a separate power source. The first potential Vb can be applied.

On the other hand, any one of the 2 ^m control terminals Td (1) to Td (2 ^m ) is given a high level signal, and the other control terminals are given a low level signal. As a result, only the N-channel transistor (of the gate terminal) connected to the control terminal to which the high level signal is given is turned on in the adjustment switching element group (hereinafter, the transistor in the on state is also referred to as “ON transistor”. ”), Only the connection point to which the ON transistor is connected among the connection points between the resistance elements in the adjustment resistor row 10b is electrically connected to the power supply line Lvss via the ON transistor. Since the number of N-channel transistors constituting the adjustment switching element group and the number of control terminals to which signals for controlling on / off thereof are 2 ^m are given, if an m-bit selection signal is given, Only one of the N-channel transistors constituting the adjustment switching element group can be turned on. Specifically, a decoder may be provided that receives an m-bit selection signal as an input and outputs a signal to be given to each of the control terminals Td (1) to Td (2 ^m ) as a control signal.

In the present embodiment, as described above, the first potential Vb is applied to the first terminal T1, the second potential Vdd is applied to the second terminal T2, and the control terminal is controlled by the m-bit selection signal as described above. Only one of Tc (1) to Tc (2 ^m ) is given a high level signal, and the other control terminals are given a low level signal. As a result, based on the first potential Vb and the second potential Vdd and the resistance values of the resistance elements R (1) to R (n + 1) constituting the voltage dividing resistor array 10, the connection point between the resistance elements is determined. The potentials are determined, and these potentials are output as reference potentials Vref (1) to Vref (n). As shown in FIG. 10, an adjustment resistor string 10b is connected between the first terminal T1 and the voltage dividing resistor string 10, and the resistance elements Rb (1) to Rb ( An adjustment switching element group is connected between the connection point between 2 ^m +1) and the power supply line Lvss. Therefore, the reference potentials Vref (1) to Vref (n) generated as described above are the resistance values of the resistance elements Rb (1) to Rb (2 ^m +1) in the adjustment resistor row 10b and the adjustment switching. It also depends on the position of the ON transistor in the element group. Therefore, the reference potentials Vref (1) to Vref (n) output from the voltage dividing resistor array 10 can be adjusted by changing the ON transistor in the adjustment switching element group according to the selection signal.

FIG. 12 shows output characteristics when the ON transistor is changed in the reference potential generating circuit according to the present embodiment. In FIG. 12, a straight line CL (1) is a straight line connecting points indicating the respective reference potentials Vref (1) to Vref (n) when the transistor TFT (1) farthest from the voltage dividing resistor array 10 is an ON transistor. The straight line CL (2 ^m ) is a straight line connecting points indicating the reference potentials Vref (1) to Vref (n) when the transistor TFT (2 ^m ) closest to the voltage dividing resistor array 10 is an ON transistor. is there. Therefore, by changing the ON transistor according to the setting of the m-bit selection signal, the reference potentials Vref (1) to Vref (n) are within the range sandwiched between these two straight lines CL (1) and CL (2 ^m ). ) Can be adjusted.

<2.2 Effect>
As described above, in this embodiment, as shown in FIG. 10, the adjustment resistor string 10b has one end connected to the voltage dividing resistor string 10 and the other end connected to the first terminal T1. The first potential Tb is applied to the first terminal T1 from an external power source or a constant voltage circuit using a Zener diode. Thus, the resistance in the adjustment resistor row 10b is set by setting the on-resistance of each of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching elements sufficiently larger than the resistance value of the adjustment resistor row 10b. Of the connection points between the elements, the potential at the point where the ON transistor is connected (hereinafter referred to as “ON transistor connection point”) can be made substantially equal to the first potential Vb (however, the resistance value of the voltage dividing resistor array 10) Is assumed to be sufficiently larger than the resistance value of the adjustment resistor row 10b). According to such a setting, the resistance string between the ON transistor connection point and the second terminal T2 to which the second potential Vdd is to be applied, that is, the connection point of the ON transistor TFT (j) and the voltage dividing resistor string 10 The reference potentials Vref (1) to Vref (n) as output voltages are determined by a resistor string obtained by adding the adjusting resistor elements Rb (j + 1) to Rb (2 ^m +1) to the voltage dividing resistor string 10 (Where j is a natural number of 2 ^m or less). Therefore, the reference potentials Vref (1) to Vref (n) can be adjusted by changing the ON transistor in the switching element group according to the selection signal.

With the above configuration, the on-resistance of each of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching elements is the same as that of the first embodiment, and the on-resistance of the adjustment switching element in the conventional reference potential generation circuit is Since the reference potential generating circuit according to the present embodiment is set to a larger value than the resistance, the circuit area required for realization can be reduced as compared with the conventional reference potential generating circuit. Further, as in the first embodiment, the resistor strings (voltage dividing resistor string 10 and adjusting resistor string 10b) for generating the reference potential are connected to the adjustment switching elements TFT (1) to TFT (2 ^m ). Since the on-resistance is not directly included, the influence on the reference potential due to the variation in the on-resistance of each of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching element is reduced. As a result, according to the present embodiment, the fluctuation range (error width) of the output voltage due to variations in on-resistance is reduced, so that the reference potential can be obtained with higher accuracy than a conventional reference potential generation circuit having a switching element for adjustment. Can be generated.

  According to the present embodiment, the generated reference potentials Vref (1) to Vref (n) mainly divide the potential difference between the first potential Vb and the second potential Vdd in the voltage dividing resistor array 10. Therefore, when it is desired to greatly change the reference potential instead of a relatively small reference potential change by the adjustment resistor array 10b and the adjustment switching element, one of the first potential Vb and the second potential Vdd or Change both sides.

<2.3 Modification>
Various modifications of the second embodiment will be described. In the following, the same or corresponding parts as those in the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

FIG. 13 is a circuit diagram showing a configuration of a first modification of the second embodiment. In this modification, P-channel thin film transistors are used instead of N-channel thin film transistors as the thin film transistors TFT (1) to TFT (2 ^m ) constituting the adjustment switching element group, and the control terminals Td (1) to Td are correspondingly used. Only one of (2 ^m ) is given a low level signal, and the other control terminals are given a high level signal. A P-channel thin film transistor connected to a control terminal having a low level (a gate terminal) becomes an ON transistor. Other configurations in this modification are the same as those in the second embodiment. Also by this modification, the same effect as that of the second embodiment can be obtained. When the potential Vss of the power supply line Lvss to which the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching elements are connected is lower than the first potential Vb, as in the second embodiment. The use of an N-channel transistor as the adjustment switching element is preferable in terms of operation as a switching element, but when the potential Vss of the power supply line Lvss is higher than the first potential Vb, the P-channel is used as the adjustment switching element. It is preferable to use a transistor.

FIG. 14 is a circuit diagram showing a configuration of a second modification of the second embodiment. In the present modification, the thin film transistors TFT (1) to TFT (2 ^m ) constituting the adjustment switching element group between 2 ^m connection points between the resistance elements in the adjustment resistor row 10b and the power supply line Lvss. Resistance elements Rd (1) to Rd (2 ^m ) are inserted in series. As described above, in the second embodiment, the on-resistances of the thin film transistors TFT (1) to TFT (2 ^m ) as the adjustment switching elements are sufficiently larger than the resistance value of the adjustment resistor row 10b. However, when the on-resistance of the thin film transistor actually formed as the adjustment switching element is not sufficiently high, the thin film transistors TFT (1) to TFT (2 ^m ) are connected in series as in this modification. What is necessary is just to set it as the structure which inserts a resistive element. As a result, even in the configuration in which the on-resistances of the thin film transistors TFT (1) to TFT (2 ^m ) are not sufficiently large, the same effect as in the second embodiment can be obtained.

FIG. 15 is a circuit diagram showing a configuration of a third modification of the second embodiment. In this modification, in the first modification shown in FIG. 13, an adjustment switching element group is formed between 2 ^m connection points between the resistance elements in the adjustment resistor string 10b and the power supply line Lvss. each thin film transistor ^{TFT (1) ~TFT (2 m} ) and a resistor in series with element ^{Rd (1) ~Rd (2 m} ) is in the inserted configuration for. When the on-resistance of a thin film transistor actually formed as an adjustment switching element is not sufficiently large, the same effect as in the second embodiment can be obtained by inserting a resistance element as in this modification. it can.

<3. Third Embodiment>
<3.1 Configuration and operation>
FIG. 16 is a circuit diagram showing a configuration of a reference potential generating circuit according to the third embodiment of the present invention. This reference potential generation circuit is also realized by using a thin film transistor as a switching element, for example, for generating a gradation voltage on a substrate constituting a liquid crystal panel or the like, but is not limited to such an application or an implementation method. Absent. Hereinafter, the same reference numerals are given to the same or corresponding parts of the configuration of the present embodiment as in the first or second embodiment, and detailed description thereof will be omitted.

The reference potential generating circuit according to this embodiment has a configuration in which the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 10 are combined. That is, as shown in FIG. 16, the reference potential generating circuit includes n + 1 resistance elements R (1), R (2),..., R (n), R (n + 1) connected in series to each other. For adjusting the high voltage side of the voltage resistor array 10 and 2 ^m +1 resistor elements Ra (1), Ra (2), ..., Ra (2 ^m ), Ra (2 ^m +1) connected in series with each other resistor array 10a and, 2 are connected in series with each other ^m +1 single resistor elements Rb (1), Rb (2 ), ......, Rb (2 m), Rb (2 m +1) low pressure side adjusting resistor consisting column 10b and, P-channel thin film transistor TFTH as 2 ^m pieces of the high pressure side adjustment switching elements connected respectively to 2 ^m pieces of connection points between the resistor elements forming the high-pressure side adjusting resistor array 10a (1), TFTH (2),..., TFTH (2 ^m ), and low-voltage side adjustment resistor string 1 N-channel thin film transistor TFTL as 2 ^m pieces of the low pressure side adjustment switching elements connected respectively to 2 ^m pieces of connection points between the resistor elements constituting the 0b (1), TFTL (2 ), ..., TFTL (2 m And a first terminal T1 to which the first potential Va is to be applied and a second terminal T2 to which the second potential Vb is to be provided, 2 ^m high-voltage side control terminals Tc (1), Tc (2),..., Tc (2 ^m ) and 2 ^m low-voltage terminals are terminals to which a control signal for adjusting the reference potential to be generated is to be given. Side control terminals Td (1), Td (2),..., Td (2 ^m ). The voltage dividing resistor string 10 has one end connected to one end of the high voltage side adjusting resistor string 10a and the other end connected to one end of the low voltage side adjusting resistor string 10b. The other end of the high voltage side adjustment resistor row 10a is connected to the first terminal T1, and the other end of the low voltage side adjustment resistor row 10b is connected to the second terminal T2. The 2 ^m transistors TFTH (1) to TFTH (2 ^m ) constituting the high-voltage side adjustment switching element group have drain terminals at connection points between the resistance elements in the high-voltage side adjustment resistor array 10a. These source terminals are connected to the power supply line Lvdd, and their gate terminals are connected to the high-voltage side control terminals Tc (1) to Tc (2 ^m ), respectively. Low pressure side adjusting constituting the switching element group 2 ^m pieces of transistors ^{TFTL (1) ~TFTL (2 m} ) have their drain terminals respectively connected to the connection point between the resistive element in the low-pressure side adjusting resistor array 10b These source terminals are connected to the low-voltage side power supply line (or ground line) Lvss, and their gate terminals are connected to the low-voltage side control terminals Td (1) to Td (2 ^m ), respectively.

  When operating the reference potential generating circuit configured as described above, the first potential Va is supplied from the predetermined power source to the first terminal T1, and the second potential Vb is supplied to the second terminal T2 from the predetermined power source. Given by. In the present embodiment, the first potential Va is higher than the second potential Vb and lower than the potential Vdd of the high-voltage power supply line Lvdd, and the potential Vss of the low-voltage power supply line Lvss is lower than the second potential Vb. (The potential Vdd of the high-voltage side power supply line Lvdd may be lower than the first potential Va, but the potential Vdd is the first potential Va from the operation of the P-channel transistors constituting the high-voltage side adjustment switch element group. In addition, the potential Vss of the low-voltage side power supply line Lvss may be higher than the second potential Vb, but in terms of the operation of the N-channel transistors constituting the low-voltage side adjustment switch element group. Vss is preferably lower than the second potential Vb). Further, in order to give the first potential Va to the first terminal T1, a constant voltage circuit that generates the first potential Va using the Zener diode Dz as shown in FIG. 3 is used instead of the power source. Alternatively, in order to apply the second potential Vb to the second terminal T2, a constant voltage circuit that generates the second potential Vb using the Zener diode Dz as shown in FIG. It may be used.

On the other hand, a low level signal is given to any one of the 2 ^m high voltage side control terminals Tc (1) to Tc (2 ^m ), and a high level signal is given to the other high voltage side control terminals. . As a result, only the P-channel transistor (of the gate terminal) connected to the control terminal to which the low level signal is applied in the high voltage side adjustment switching element group is turned on (hereinafter, the transistor in the on state is referred to as “ Among the connection points between the resistance elements in the high-voltage side adjustment resistor row 10a, only the connection point to which the high-voltage side ON transistor is connected is electrically connected to the high-voltage side power supply line Lvdd via the ON transistor. Connected to. In addition, a high level signal is given to any one of the 2 ^m low voltage side control terminals Td (1) to Td (2 ^m ), and a low level signal is given to the other low voltage side control terminals. . As a result, only the N-channel transistor (of the gate terminal) connected to the control terminal to which the high level signal is given in the low-voltage side adjustment switching element group is turned on (hereinafter, the transistor in the on state is referred to as “ Only the connection point to which the low voltage side ON transistor is connected among the connection points between the resistance elements in the low voltage side adjustment resistor string 10b is electrically connected to the low voltage side power line Lvss via the ON transistor. Connected to. Since the number of P-channel transistors and the number of high-voltage side control terminals constituting the high-voltage side adjustment switching element group are both 2 ^m , the high-voltage side adjustment switching element group is generated by an m-bit high-voltage side selection signal. The high-voltage side ON transistor can be designated at. Similarly, the low voltage side ON transistor can be specified in the low voltage side adjustment switching element group by the m-bit low voltage side selection signal.

In the present embodiment, as described above, the first potential Va is applied to the first terminal T1, the second potential Vb is applied to the second terminal T2, and the high-voltage side control terminal is supplied by the m-bit high-voltage side selection signal. A low level signal is given to only one of Tc (1) to Tc (2 ^m ), and a high level signal is given to the other control terminals. Only one of the control terminals Td (1) to Td (2 ^m ) is given a high level signal, and the other control terminals are given a low level signal. As a result, based on the first potential Va and the second potential Vb and the resistance values of the resistance elements R (1) to R (n + 1) constituting the voltage dividing resistor array 10, the connection point between the resistance elements is determined. The potentials are determined, and these potentials are output as reference potentials Vref (1) to Vref (n). Then, by changing the high voltage side ON transistor in the high voltage side adjustment switching element group by the high voltage side selection signal and / or by changing the low voltage side ON transistor in the low voltage side adjustment switching element group by the low voltage side selection signal The reference potentials Vref (1) to Vref (n) output from the voltage dividing resistor array 10 can be adjusted.

FIGS. 17A to 17C show output characteristics when the high-voltage side and low-voltage side ON transistors are changed in the reference potential generation circuit according to the present embodiment. FIG. 17A shows the adjustment range of each of the reference potentials Vref (1) to Vref (n) when one of the high-voltage side and low-voltage side ON transistors is fixed and the other is changed. That is, by changing the high-voltage side ON transistor in a state where the low-voltage side ON transistor is fixed to the central transistor TFTL (2 ^m-1 ) in the low-voltage side adjustment switching element group, two straight lines CL ( Each reference potential Vref (1) to Vref (n) can be adjusted in a range between 2 ^m−1 , 1) and CL (2 ^m−1 , 2 ^m ). In addition, by changing the low-voltage side ON transistor in a state where the high-voltage side ON transistor is fixed to the central transistor TFTH (2 ^m-1 ) in the high-voltage side adjustment switching element group, two straight lines CL ( The reference potentials Vref (1) to Vref (n) can be adjusted in a range sandwiched between ¹ , 2 ^m-1 ) and CL (2 ^m , 2 ^m-1 ). The bold dotted lines are generated when the low-voltage side and high-voltage side ON transistors are the transistors TFTL (2 ^m-1 ) and TFTH (2 ^m-1 ) in the middle of the low-voltage side and high-voltage side adjusting switching element groups, respectively. A straight line (output characteristic curve) connecting points indicating the respective reference potentials Vref (1) to Vref (n) is shown.

FIG. 17B shows the adjustment range of each of the reference potentials Vref (1) to Vref (n) when both the high voltage side and low voltage side ON transistors are sequentially changed in the same direction. Lines connecting the points indicating the generated reference potentials Vref (1) to Vref (n) (hereinafter referred to as “output characteristic curve”) indicate that the low-voltage side and high-voltage side ON transistors are switching elements for adjusting the low-voltage side and the high-voltage side, respectively. In the case of the transistor TFTL (2 ^m-1 ) and TFTH (2 ^m-1 ) at the center of the group, it is indicated by a thick dotted straight line CL (2 ^m-1 , 2 ^m-1 ). In the low-voltage side adjustment switching element group, the low-voltage side ON transistor is sequentially changed from the central transistor TFTL (2 ^m-1 ) to the transistor TFTL (1) farthest from the voltage dividing resistor array 10, and the high-voltage side adjustment switching element When the high-voltage side ON transistor is changed from the central transistor TFTH (2 ^m-1 ) in order to the transistor TFTH (1) farthest from the voltage dividing resistor array 10 in the group, the output characteristic curve becomes the thick dotted line CL (2 ^{m −1} , 2 ^m−1 ) to a thin dotted straight line CL (1, 1). On the other hand, in the low-voltage side adjustment switching element group, the low-voltage side ON transistor is sequentially changed from the central transistor TFTL (2 ^m-1 ) to the transistor TFTL (2 ^m ) closest to the voltage dividing resistor row 10 and the high-voltage side adjustment transistor. In the switching element group, when the high-voltage side ON transistor is sequentially changed from the central transistor TFTH (2 ^m-1 ) to the transistor TFTH (2 ^m ) closest to the voltage dividing resistor array 10, the output characteristic curve becomes a thick dotted straight line It changes from CL (2 ^m−1 , 2 ^m−1 ) toward a thin one-dot chain line CL (2 ^m , 2 ^m ). Therefore, by changing both the high-voltage side and low-voltage side ON transistors in order in the same direction, each reference potential Vref (in the range between the two dotted lines CL (1, 1) and CL (2 ^m , 2 ^m ) 1) to Vref (n) can be adjusted.

FIG. 17C shows the adjustment range of each of the reference potentials Vref (1) to Vref (n) when both the high-voltage side and low-voltage side ON transistors are sequentially changed in the reverse direction. Also in FIG. 17C, the low-voltage side and high-voltage side ON transistors are the transistors TFTL (2 ^m-1 ) and TFTH (2 ^m-1 ) in the middle of the low-voltage side and high-voltage side adjusting switching element groups, respectively. The output characteristic curve is indicated by a thick dotted straight line CL (2 ^m−1 , 2 ^m−1 ). In the low-voltage side adjustment switching element group, the low-voltage side ON transistor is sequentially changed from the central transistor TFTL (2 ^m-1 ) to the transistor TFTL (1) farthest from the voltage dividing resistor array 10, and the high-voltage side adjustment switching element When the high-voltage side ON transistor in the group is sequentially changed from the central transistor TFTH (2 ^m-1 ) to the transistor TFTH (2 ^m ) closest to the voltage dividing resistor array 10, the output characteristic curve becomes a thick dotted straight line CL (2 ^m-1 , 2 ^m-1 ) to a thin dotted straight line CL (1, 2 ^m ). On the other hand, in the low-voltage side adjustment switching element group, the low-voltage side ON transistor is sequentially changed from the central transistor TFTL (2 ^m-1 ) to the transistor TFTL (2 ^m ) closest to the voltage dividing resistor row 10 and the high-voltage side adjustment transistor. In the switching element group, when the high-voltage side ON transistor is sequentially changed from the central transistor TFTH (2 ^m-1 ) to the transistor TFTH (1) farthest from the voltage dividing resistor array 10, the output characteristic curve becomes a thick dotted line CL It changes from (2 ^m−1 , 2 ^m−1 ) toward a thin one-dot chain line CL (2 ^m , 1). Therefore, by changing both the high-voltage side and the low-voltage side ON transistors in the reverse direction in order, each reference potential Vref (in the range between the two dotted lines CL (1, 2 ^m ) and CL (2 ^m , 1)). 1) to Vref (n) can be adjusted.

<3.2 Effects>
As described above, in this embodiment, since the first embodiment and the second embodiment described above are combined, the reference potential is changed by changing the low-voltage side ON transistor by the low-voltage side selection signal. Vref (1) to Vref (n) can be adjusted, and the reference potentials Vref (1) to Vref (n) can be adjusted by changing the high-voltage side ON transistor according to the high-voltage side selection signal. This makes it possible to adjust the reference potentials Vref (1) to Vref (n) over a wider range, as is apparent from FIGS. 17 (a) to 17 (c).

  Further, according to the present embodiment, as in the first and second embodiments, the on-resistance of the adjustment switching element is set to a larger value than in the conventional case, so that the circuit area required for realization can be reduced. it can. Further, according to the present embodiment, as in the first and second embodiments, the fluctuation range (error width) of the output voltage (reference potential) due to the variation in the on-resistance of the adjustment switching element is reduced. The reference potential can be generated with higher accuracy than the conventional reference potential generation circuit having the switching elements.

<3.3 Modification>
In the third embodiment, the portion related to the high-voltage side adjustment switching element group can be modified in the same manner as in the first embodiment, and the part related to the low-voltage side adjustment switching element group is the same as in the second embodiment. Similar variations are possible. Therefore, as a modification of the present embodiment, the first to third modifications (FIGS. 7 to 9) of the first embodiment and the first to third modifications of the second embodiment (FIG. 13 to FIG. 13). Various modifications by combination with FIG. 15) can be configured.

For example, FIG. 18 shows a modification of the third embodiment, which is a combination of the second modification (FIG. 8) of the first embodiment and the second modification (FIG. 14) of the second embodiment. It is a circuit diagram which shows a structure. When the on-resistance of the thin film transistor actually formed as the adjustment switching element is not sufficiently high, the thin film transistors TFTH (1) to TFTH (2 ^m ) and the low voltage as the high-voltage side adjustment switching elements as in this modification. A configuration in which resistance elements Rc (1) to Rc (2 ^m ) and Rd (1) to Rd (2 ^m ) are inserted in series in the thin film transistors TFTL (1) to TFTL (2 ^m ) as the side adjustment switching elements. And it is sufficient. Thereby, even in the configuration in which the on-resistances of the thin film transistors TFT (1) to TFT (2 ^m ) and TFTL (1) to TFTL (2 ^m ) as switching elements for adjustment are not sufficiently large, Similar effects can be obtained.

<4. Application example of reference potential generation circuit>
Hereinafter, application examples of the reference potential generation circuit according to each of the above-described embodiments or modifications thereof (hereinafter referred to as “reference potential generation circuit according to the embodiment of the present invention”) will be described.

<4.1 First application example>
FIG. 19 is a block diagram showing a first liquid crystal display device using the reference potential generation circuit according to the embodiment of the present invention. This first liquid crystal display device adopts a digital drive system, and includes a power supply circuit 110, a timing generator 120, an LCD controller 130, a driver circuit 140, and a pixel array 180 as a display unit. Yes. The LCD controller 130 receives the control signals C1 and C2 to be given to the timing generator 120 and the driver circuit 140 and the digital video signal VD to be given to the driver circuit 140 based on the control signal and the video signal given from the outside of the liquid crystal display device. Generate. The timing generator 120 generates various control signals C3 and C4 for determining the operation timing of each unit based on the control signal C1 from the LCD controller 130. The power supply circuit 110 generates power supply voltages Ea, Ec and the like necessary for the operation of each unit of the liquid crystal display device based on the power supplied from the outside of the liquid crystal display device.

  The pixel array 180 is a matrix corresponding to each of the plurality of data signal lines, the plurality of scanning signal lines intersecting with the plurality of data signal lines, and the intersection of the plurality of data signal lines and the plurality of scanning signal lines. A plurality of pixel forming portions arranged in a shape, and each pixel forming portion is a switching element having a source terminal connected to a corresponding data signal line and a gate terminal connected to a corresponding scanning signal line A thin film transistor; a pixel electrode connected to a drain terminal of the thin film transistor; a common electrode provided in common to the plurality of pixel formation portions; and a pixel electrode provided in common to the plurality of pixel formation portions; A liquid crystal layer to which a voltage is applied by the common electrode.

  The driver circuit 140 should display a gate driver 142 as a scanning signal line driving circuit that applies a scanning signal SC for sequentially selecting the plurality of scanning signal lines in the pixel array 180 to the plurality of scanning signal lines. A source driver 144 is provided as a data signal line driving circuit for applying a plurality of data signals VA representing an image to the plurality of data signal lines in the pixel array 180, respectively. The source driver 144 includes a digital interface circuit 152 and a video circuit 154. The digital video signal VD is input to the digital interface circuit 152 as a serial signal in units of pixels from the LCD controller 130, and the digital interface circuit 152 performs serial-parallel conversion on the digital video signal VD for each horizontal period. Output an image signal for one line. The video circuit 154 generates the plurality of data signals VA by converting the image signal for one line output every horizontal period into an analog voltage signal, and the data signals VA are converted into the plurality of data signals VA in the pixel array 180. Applied to the data signal line.

  In this way, the pixel array 180 is configured such that the scanning signal SC is applied to the plurality of scanning signal lines and the plurality of data signals VA are applied to the plurality of data signal lines, whereby the pixel electrode is formed in each pixel formation. A voltage corresponding to the pixel value of the image to be displayed is held in the pixel capacitance formed by the common electrode. An image is displayed by applying a voltage held in each pixel capacitor to the liquid crystal layer and controlling the light transmittance of the liquid crystal layer.

  FIG. 20 is a block diagram showing a configuration of the video circuit 154 in the liquid crystal display device having the above configuration. The video circuit 154 includes a gradation voltage generation circuit 162, a gradation voltage selection circuit 164, and an output circuit 166. As the gradation voltage generation circuit 162, the above-described reference potential generation circuit according to the embodiment of the present invention is used, and a plurality of reference potentials are generated as gradation voltages based on the power supply voltage from the power supply circuit 110. By controlling on / off of the internal adjustment switching element based on a control signal from the LCD controller 130, a plurality of reference potentials output as gradation voltages are adjusted. The gradation voltage selection circuit 164 receives the digital video signal VD for one horizontal line (that is, the number of data signal lines in the pixel array 180) from the digital interface circuit 152, and the gradation voltage selection circuit 164 Based on the digital video signal (R (red), G (green), or B (blue) digital video signal) VD corresponding to the data signal line, among the plurality of grayscale voltages from the grayscale voltage generation circuit 162 Any one gradation voltage is selected. The gradation voltage selected for each data signal line in this manner is input to the output circuit 166, and is output from the source driver 144 as the data signal VA through a buffer such as a voltage follower in the output circuit 166.

  As described above, by using the reference potential generation circuit according to the embodiment of the present invention as the gradation voltage generation circuit 162 in the video circuit 154 in the liquid crystal display device, the circuit scale in the gradation voltage generation circuit 162 is increased. It is possible to appropriately adjust the gradation voltage to be generated while suppressing the on-resistance of the switching element and ensuring sufficient accuracy. Therefore, the application of the present invention for such an application is particularly effective when a gradation voltage generating circuit and a driver circuit including the same are formed by thin film transistors on a substrate constituting a liquid crystal panel or the like integrally with a display portion. is there.

<4.2 Second Application Example>
FIG. 21 is a block diagram showing a second liquid crystal display device using the reference potential generation circuit according to the embodiment of the present invention. This second liquid crystal display device adopts an analog drive system, and includes a power supply circuit 110, a timing generator 120, an LCD controller 130, a video circuit 160, a driver circuit 170, and a pixel array as a display unit. 180. Of the configuration of the second liquid crystal display device, the same or similar parts as those of the first liquid crystal display device are denoted by the same reference numerals, and detailed description thereof is omitted.

  The LCD controller 130 in the second liquid crystal display device supplies a digital video signal VD representing an image to be displayed to the video circuit 160 based on a video signal given from the outside of the liquid crystal display device. The video circuit 160 generates three analog video signals VA of R (red), G (green), and B (blue) based on the digital video signal VD, and supplies these to the driver circuit 170.

  The driver circuit 170 includes a source driver 174 as a data signal line driving circuit that sequentially applies an analog voltage signal VA representing an image to be displayed to a plurality of data signal lines in the pixel array 180, and a plurality of scanning signals in the pixel array 180. A gate driver 172 is provided as a scanning signal line driving circuit for applying a scanning signal SC for sequentially selecting lines to the plurality of scanning signal lines. The source driver 174 samples the analog video signal VA from the video circuit 160 and sequentially applies the sampled analog video signal VA to the plurality of data signal lines in the pixel array 180.

  In this manner, the pixel array 180 is configured such that the scanning signal SC is applied to the plurality of scanning signal lines and the analog video signal VA is sequentially applied to the plurality of data signal lines, so that each pixel forming unit A voltage corresponding to the pixel value of the image to be displayed is held in the pixel capacitance formed by the pixel electrode and the common electrode. An image is displayed by applying a voltage held in each pixel capacitor to the liquid crystal layer and controlling the light transmittance of the liquid crystal layer.

  The video circuit 160 in the second liquid crystal display device as described above does not generate an analog video signal for each data signal line, but R (red), G (green), B to be supplied to the source driver 174. Although it differs from the video circuit 154 in the first liquid crystal display device in that the three (blue) digital video signals VD are converted into analog video signals VA, the basic configuration is the same. That is, the video circuit 160 in the second liquid crystal display device also includes a gradation voltage generation circuit 162, a gradation voltage selection circuit 164, and an output circuit 166 as shown in FIG. Except for the difference in the number of analog video signals and the number of output analog video signals, the configuration and operation thereof are the same as those of the video circuit 154 in the first liquid crystal display device.

  As described above, by using the reference potential generation circuit according to the embodiment of the present invention as the gradation voltage generation circuit in the video circuit 160 in the liquid crystal display device, an increase in circuit scale in the gradation voltage generation circuit is suppressed. Therefore, it is possible to appropriately adjust the gradation voltage to be generated while ensuring sufficient accuracy regardless of the variation in the on-resistance of the switching element. Therefore, the application of the present invention for such an application is particularly effective when a gradation voltage generating circuit and a driver circuit including the same are formed by thin film transistors integrally with a display portion on a substrate constituting a liquid crystal panel. .

<4.3 Third application example>
FIG. 22 is a block diagram showing a configuration of a main part of a driver circuit using the reference potential generating circuit according to the embodiment of the present invention. The reference potential generation circuit according to the embodiment of the present invention can be used to generate a clock signal of a shift register in a source driver or a gate driver of a liquid crystal display device or the like. That is, as shown in FIG. 22, the main part of the driver circuit according to this application example includes a comparator 194 as a level shifter, and a reference potential generation circuit 192 for generating a reference potential Vref to be input to the comparator 194. The comparator 194 and the reference potential generation circuit 192 constitute a clock signal generation circuit that generates a high amplitude clock signal CKh for driving the shift register 196. The comparator 194 receives the low-amplitude clock signal CKl from the outside at its positive terminal, and receives the reference potential Vref from the reference potential generation circuit 192 at its negative terminal. Thereby, when the potential of the low amplitude clock signal CKl is equal to or lower than the reference potential Vref, the comparator 194 outputs a low level potential in the predetermined high amplitude signal, and the potential of the low amplitude clock signal CKl is the reference potential. When the potential is higher than the potential Vref, a high level potential in a predetermined high amplitude signal is output. In this way, the comparator 194 operates as a level shifter that converts the low amplitude clock signal CKl into the high amplitude clock signal CKh.

  As described above, the reference potential generation circuit according to the embodiment of the present invention may be used as the reference potential generation circuit 192 that generates the reference potential Vref for converting the low amplitude clock signal CKl into the high amplitude clock signal CKh. it can. At this time, in the reference potential generation circuit 192, on / off of the internal adjustment switching element is controlled based on a control signal from the LCD controller or the like. The generated reference potential is adjusted in accordance with the offset voltage, the level variation of the low amplitude clock signal CLl, and the like. As described above, by using the reference potential generation circuit according to the embodiment of the present invention, in the reference potential generation circuit 192 in the driver circuit, an increase in circuit scale is suppressed and regardless of variations in on-resistance of the switching elements. Sufficient accuracy can be ensured. Therefore, the application of the present invention for such applications is particularly effective when a driver circuit including the reference potential generation circuit 192 is formed integrally with a display portion on a substrate constituting a liquid crystal panel or the like using a thin film transistor. .

1 is a circuit diagram showing a configuration of a reference potential generation circuit according to a first embodiment of the present invention. 3 is a circuit diagram showing a power supply to be supplied to a reference potential generation circuit in the first embodiment. FIG. 2 is a circuit diagram showing a configuration of a constant voltage circuit for generating a potential to be applied to a reference potential generating circuit in the first embodiment. FIG. It is a characteristic view which shows the output characteristic in the said 1st Embodiment. It is a circuit diagram which shows the circuit structure made into the object of the simulation for investigating the output characteristic in the said 1st Embodiment. It is a characteristic view which shows the result of the said simulation. It is a circuit diagram which shows the structure of the 1st modification of the said 1st Embodiment. It is a circuit diagram which shows the structure of the 2nd modification of the said 1st Embodiment. It is a circuit diagram which shows the structure of the 3rd modification of the said 1st Embodiment. FIG. 5 is a circuit diagram showing a configuration of a reference potential generation circuit according to a second embodiment of the present invention. It is a circuit diagram which shows the structure of the constant voltage circuit for producing | generating the electric potential which should be given to a reference electric potential generation circuit in the said 2nd Embodiment. It is a characteristic view which shows the output characteristic in the said 2nd Embodiment. It is a circuit diagram which shows the structure of the 1st modification of the said 2nd Embodiment. It is a circuit diagram which shows the structure of the 2nd modification of the said 2nd Embodiment. It is a circuit diagram which shows the structure of the 3rd modification of the said 2nd Embodiment. FIG. 5 is a circuit diagram showing a configuration of a reference potential generation circuit according to a third embodiment of the present invention. It is a characteristic view which shows the output characteristic in the said 3rd Embodiment. It is a circuit diagram which shows the structure of the modification of the said 3rd Embodiment. It is a block diagram which shows the structure of the 1st liquid crystal display device using the reference potential generation circuit which concerns on embodiment etc. of this invention. It is a block diagram which shows the structure of the video circuit in the said 1st liquid crystal display device. It is a block diagram which shows the structure of the 2nd liquid crystal display device using the reference potential generation circuit which concerns on embodiment etc. of this invention. It is a block diagram which shows the structure of the principal part of the driver circuit using the reference potential generation circuit which concerns on embodiment etc. of this invention. It is a circuit diagram which shows a 1st prior art example. It is a circuit diagram which shows a 2nd prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Voltage dividing resistor row 10a ... (High voltage side) Adjustment resistor row 10b ... (Low voltage side) Adjustment resistor row 140, 170 ... Driver circuit 144, 174 ... Source driver (Data line drive circuit)
154, 160 ... Video circuit 162 ... Gradation voltage generation circuit 192 ... Reference potential generation circuit Dz ... Zener diode E1, E2 ... Power supply R (i) ... Resistance element (i = 1, 2, ..., n) in the voltage dividing resistor array , N + 1)
Ra (j) (high voltage side) resistance elements in the adjustment resistor array (j = 1, 2,..., 2 ^m +1)
Rb (j)... (Low voltage side) resistance elements in the adjusting resistor string (j = 1, 2,..., 2 ^m +1)
T1 ... 1st terminal T2 ... 2nd terminal Tc (k) ... High voltage side control terminal (k = 1, 2, ..., 2 ^m )
Td (k) ... low-voltage side control terminal (k = 1, 2, ..., 2 ^m )
Lvdd ... High voltage side power supply line Lvss ... Low voltage side power supply line TFT (k) ... Thin film transistor (switching element for adjustment)
(K = 1, 2,..., 2 ^m )
TFTH (k) ... Thin film transistor (switching element for high voltage side adjustment)
(K = 1, 2,..., 2 ^m )
TFTL (k) ... Thin film transistor (low-voltage side adjustment switching element)
(K = 1, 2,..., 2 ^m )
Va ... first potential Vb ... second potential Vdd ... high-voltage side power supply potential Vref (i) ... reference potential (i = 1, 2, ..., n)

Claims (17)

It has a resistor string composed of a plurality of resistor elements connected in series with each other, a first predetermined potential is given to one end of the resistor string, and a second predetermined potential is given to the other end. A reference potential generating circuit for generating a potential,
A switching element provided corresponding to at least one connection point between the resistance elements constituting the resistance string;
The at least one connection point is connected to a power line via the corresponding switching element;
The reference voltage generating circuit, wherein the reference potential is adjusted by turning on / off the switching element. A reference potential generating circuit having a resistor string composed of a plurality of resistor elements connected in series to each other, wherein a first predetermined potential is applied to one end of the resistor string and a second predetermined potential is applied to the other end. And
The resistor string is
A voltage dividing resistor string for generating a reference potential;
An adjustment resistor string for adjusting the reference potential,
A switching element is provided corresponding to at least one connection point between the resistance elements constituting the adjustment resistor string,
The at least one connection point is connected to a power line via the corresponding switching element;
One end of the voltage dividing resistor string is connected to one end of the adjusting resistor string,
The voltage dividing resistor array generates the reference potential based on the first and second predetermined potentials and on / off of the switching element.   A resistor element inserted between the connection point between the resistor elements constituting the adjustment resistor string and the power supply line so as to be connected in series with the switching element corresponding to the connection point; The reference potential generating circuit according to claim 2, wherein the reference potential generating circuit is characterized in that: The first predetermined potential is higher than the second predetermined potential;
4. The reference potential generation circuit according to claim 2, wherein the potential of the power supply line is higher than the first predetermined potential. The first predetermined potential is lower than the second predetermined potential;
4. The reference potential generation circuit according to claim 2, wherein the potential of the power supply line is lower than the first predetermined potential. A reference potential generating circuit having a resistor string composed of a plurality of resistor elements connected in series to each other, wherein a first predetermined potential is applied to one end of the resistor string and a second predetermined potential is applied to the other end. And
The resistor string is
A voltage dividing resistor string for generating a reference potential;
And first and second adjustment resistor strings for adjusting the reference potential,
A first switching element is provided corresponding to at least one connection point between the resistance elements constituting the first adjustment resistor string;
A second switching element is provided corresponding to at least one connection point between the resistance elements constituting the second adjustment resistor string;
One end of the voltage dividing resistor string is connected to one end of the first adjusting resistor string,
The other end of the voltage dividing resistor string is connected to one end of the second adjusting resistor string,
The other end of the first adjustment resistor string is given the first predetermined potential,
The other end of the second adjustment resistor string is given the second predetermined potential,
A connection point between the resistance elements constituting the first adjustment resistor string is connected to the first power supply line via the corresponding first switching element,
The connection point between the resistance elements constituting the second adjustment resistor string is connected to the second power supply line via the corresponding second switching element,
The voltage dividing resistor array generates the reference potential based on the first and second predetermined potentials and on / off of the first and second switching elements.   Inserted between a connection point between the resistance elements constituting the first adjustment resistor string and the first power supply line so as to be connected in series with the first switching element corresponding to the connection point. The reference potential generating circuit according to claim 6, further comprising a resistance element.   Inserted between the connection point between the resistance elements constituting the second adjustment resistor string and the second power supply line so as to be connected in series with the second switching element corresponding to the connection point The reference potential generating circuit according to claim 6, further comprising a resistance element. The second predetermined potential is higher than the potential of the second power supply line,
The first predetermined potential is higher than the second predetermined potential;
9. The reference potential generation circuit according to claim 6, wherein a potential of the first power supply line is higher than the first predetermined potential. 10. A first power source for generating the first predetermined potential;
10. The reference potential generation circuit according to claim 1, further comprising a second power source that generates the second predetermined potential. 11. A constant voltage circuit including a Zener diode having a breakdown voltage corresponding to the first predetermined potential, and generating the first predetermined potential based on the breakdown voltage;
10. The reference potential generation circuit according to claim 1, further comprising a second power source that generates the second predetermined potential. 11. A first power source for generating the first predetermined potential;
2. A constant voltage circuit including a Zener diode having a breakdown voltage corresponding to the second predetermined potential, and generating the second predetermined potential based on the breakdown voltage. Item 10. The reference potential generation circuit according to any one of Items 9 to 9. A first constant voltage circuit including a Zener diode having a breakdown voltage corresponding to the first predetermined potential, and generating the first predetermined potential based on the breakdown voltage;
And a second constant voltage circuit including a Zener diode having a breakdown voltage corresponding to the second predetermined potential, and generating the second predetermined potential based on the breakdown voltage. 10. The reference potential generating circuit according to claim 1, wherein the reference potential generating circuit is any one of claims 1 to 9.   A display device comprising the reference potential generation circuit according to claim 1. A plurality of pixel forming portions for forming an image to be displayed; a plurality of data signal lines for transmitting a plurality of data signals which are analog voltage signals representing the image to be displayed to the plurality of pixel forming portions; A data signal line driving circuit for a display device comprising:
14. A gradation voltage generation circuit that generates a plurality of gradation voltages by the reference potential generation circuit according to claim 1, wherein the plurality of data signals are based on the plurality of gradation voltages. Generating a data signal line driver circuit. A plurality of pixel forming portions for forming an image to be displayed; a plurality of data signal lines for transmitting a video signal which is an analog voltage signal representing the image to be displayed to the plurality of pixel forming portions; In a display device comprising a data signal line driving circuit for sequentially applying a video signal to the plurality of data signal lines, the video signal is based on a digital video signal inputted from the outside as a signal representing the image to be displayed. A video circuit to generate,
A gradation voltage generation circuit that generates a plurality of gradation voltages by the reference potential generation circuit according to any one of claims 1 to 13, wherein the digital video signal is generated based on the plurality of gradation voltages. A video circuit, wherein the video signal is generated by converting into an analog voltage signal. A clock signal generation circuit for generating a high amplitude clock signal from a low amplitude clock signal,
A reference potential generation circuit according to any one of claims 1 to 13,
A clock signal generation circuit comprising: a comparator for generating the high amplitude clock signal by comparing the potential of the low amplitude clock signal with a reference potential generated by the reference potential generation circuit.

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