JP2005091196A - Burn-in pattern creation method and apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to create a burn-in pattern signal relatively easily even for those who do not have specialized knowledge.
A setting information input to a control PC2 is converted, a command file 21 describing a command given to a semiconductor device to be tested and its detailed information (state of each signal line), an address range, A counter file 22 describing the number of executions, a pattern file 23 describing the execution order of commands, and a data file 24 describing data signals are generated. The burn-in pattern generation unit 11 generates control signals such as RAS and CAS given to the semiconductor device to be tested based on the files 21 and 23, generates an address signal based on the file 22, and stores the file 24 in the file 24. Based on this, a data signal is generated. The generated burn-in pattern signal is input to a semiconductor device to be tested mounted on the burn-in card 32 and a burn-in test is performed.
[Selection] Figure 2

Description

  The present invention relates to a burn-in pattern creation method and apparatus for creating a burn-in pattern signal to be applied to a semiconductor device in order to test the semiconductor device in a burn-in device for screening a defective semiconductor. The present invention relates to a burn-in pattern creation method and apparatus that can create a burn-in pattern relatively easily even for a person who does not have a mark.

When a semiconductor device is shipped and tested, a defective device is screened by storing the semiconductor device in a burn-in tank, inputting a burn-in signal from a signal generator to the semiconductor device, and performing burn-in.
FIG. 10 shows a schematic configuration of the burn-in apparatus.
The burn-in apparatus includes, for example, a burn-in tank 101, a characteristic monitor unit 102 including an IC tester, a temperature control apparatus 110 that controls the temperature in the burn-in tank 101, and the start / end of burn-in as shown in FIG. The burn-in control unit 104 is controlled.
A semiconductor device such as an LSI to be tested is mounted on an IC socket provided on the burn-in card 103, and the burn-in card 103 on which the semiconductor device is mounted is stored in the burn-in bath 101 and provided in the burn-in bath. Attached to the connector C.

Various sensors such as a temperature sensor 101a for measuring the temperature in the tank are provided in the burn-in tank 101. The temperature sensor 101a detects the temperature in the burn-in tank 101 and sends it to the temperature detection unit 110a of the temperature control device 110. The temperature control unit 110b controls a heater or the like (not shown) so that the temperature in the burn-in tank 101 input from the temperature detection unit 111 becomes a predetermined value.
The inside of the burn-in tank 101 is held at a predetermined temperature by the temperature controller 110, and a burn-in pattern signal is input from the characteristic monitor unit 102 to the semiconductor element 103b mounted on the burn-in card 103 via the connector 101b. Perform burn-in acceleration test.
The characteristic monitor unit 102 applies the burn-in pattern signal to each semiconductor device to be tested, checks whether each semiconductor element operates normally, and screens for defective ICs.

For example, the burn-in pattern signal is generated as follows.
(1) A burn-in pattern generation circuit storing a plurality of pattern signals in a storage medium is provided, and corresponding pattern signals are read out and generated from the storage medium according to test conditions or a semiconductor device to be tested (for example, Patent Document 1).
(2) A processing device for generating a burn-in pattern signal is provided, and a pattern signal corresponding to a test condition or a semiconductor device to be tested is generated by executing a pattern generation program (see, for example, Patent Document 2). .
JP 2000-131376 A JP 11-242610 A

When performing the burn-in test, various burn-in pattern signals are used according to the type of semiconductor device to be tested, the manufacturer, the test conditions, and the like. For this reason, for example, as described in Patent Document 1, when storing a pattern signal in a storage medium and reading out the corresponding pattern signal to generate a burn-in pattern signal, a plurality of types of pattern signals are prepared in advance. It must be stored in a storage medium.
Further, as described in Patent Document 2, even when a processing device is provided and a pattern generation program is executed to generate a burn-in pattern signal, data in which conditions and the like according to the generated burn-in pattern signal are set is created. There is a need.
The generation of the pattern signal and data for generating the burn-in pattern is usually performed by a person with specialized knowledge, and a lot of man-hours are required for debugging. For this reason, when creating a new burn-in pattern, for example, when performing a burn-in test on a new semiconductor device, it is necessary to ask a person with specialized knowledge to create the burn-in pattern. It was necessary.
The present invention has been made in view of the above circumstances, and provides a burn-in pattern creation method and apparatus capable of creating a burn-in pattern signal relatively easily even without special knowledge. For the purpose.

In the present invention, the above problem is solved as follows.
A command file describing the state of each signal line of the semiconductor device under test when the command given to the semiconductor device under test is converted, and the command is issued, and the test target A counter file that describes the address range and the number of times of execution, a pattern file that describes the execution order of commands given to the semiconductor device, and a data file that describes data signals to be input to the semiconductor device are generated.
A burn-in pattern signal for performing a burn-in test of the semiconductor device is generated based on information described in the command file, counter file, pattern file, and data file.
That is, based on the information set by the operator, the file group is generated, the execution order of the commands described in the pattern file, and the state of each signal line when each command described in the command file is issued Based on the above, the control signal input to the semiconductor device under test is generated, and the address signal is generated based on the branch information described in the command file, the address range described in the counter file, and the number of executions. Further, a data signal is generated based on the value of the data signal described in the data file.

In the present invention, a command file that describes a command given to the semiconductor device to be tested from the input setting information and a state of each signal line of the semiconductor device to be tested when the command is issued, Generate a counter file describing the address range to be tested, the number of executions, a pattern file describing the execution order of commands given to the semiconductor device, and a data file describing a data signal input to the semiconductor device, Based on the information described in this file group, the burn-in pattern signal for performing the burn-in test of the semiconductor device is generated, so even a person without specialized knowledge can create a burn-in pattern relatively easily. be able to.
For this reason, the labor and cost for creating the burn-in pattern can be reduced, and the time for creating can be shortened.

FIG. 1 is a diagram showing a configuration example of a burn-in apparatus according to an embodiment of the present invention.
In the figure, reference numeral 30 denotes a thermostatic chamber for performing a burn-in test. A backboard 31 is provided on the back surface of the thermostatic chamber 30, and a burn-in in which a semiconductor device to be tested is mounted on a connector of the backboard 31. A card 32 is inserted, and a burn-in pattern signal is applied to each semiconductor device via the back board 31.
The control unit 1 is connected to the backboard 31. The control unit 1 is provided with a control unit 1a, a driver 1b, and a power supply unit 1c. The control unit 1a is applied to a burn-in pattern generation unit that generates a burn-in pattern signal, which will be described later, and applied to a semiconductor device to be tested. A burn-in test control unit is provided for monitoring the voltage, current, etc., and controlling the temperature, burn-in time, and the like.
A control computer 2 is connected to the control unit 1, and various control conditions are set and burn-in tests are managed by the control computer 2 (hereinafter referred to as a control PC 2). Further, the control computer 2 creates various files for creating a burn-in pattern signal as will be described later.

FIG. 2 is a diagram illustrating a functional configuration of the control computer 2 and a schematic configuration of the burn-in pattern generation unit involved in creating the burn-in pattern according to the present embodiment.
The control PC 2 includes a data conversion unit 2a, and creates a pattern file 21, a command file 22, a counter file 23, and a data file 24 based on setting information set from an input unit or the like. Moreover, various test conditions, such as the temperature of a thermostat, burn-in time, are set by control PC2.
The control unit 1a of the control unit 1 includes a burn-in pattern generation unit 11 that generates a burn-in pattern signal based on the pattern file 21, command file 22, counter file 23, and data file 24 created by the control PC 2, and the control PC 2. A burn-in test control unit 12 is provided for controlling the burn-in test based on the test conditions set by.
The burn-in pattern generation unit 11 includes register groups 111 to 114 that store data of the pattern file 21, command file 22, counter file 23, and data file 24, and a waveform output control unit 115. The waveform output control unit 115 includes: A burn-in pattern signal is generated based on the data set in the registers 111 to 114 in accordance with the output control signal of the burn-in test control unit 12. This burn-in pattern signal is applied to the backboard 31 via the driver 1b, and is applied to the burn-in card 32 on which the semiconductor device to be tested is mounted.

Hereinafter, creation of a burn-in pattern according to an embodiment of the present invention will be described. In the following, the creation of a burn-in pattern when testing an SDRAM will be described, but the creation of a burn-in pattern for testing other memories such as a DRAM can be similarly performed.
FIG. 3 is a diagram showing a procedure for creating a burn-in pattern according to this embodiment.
In order to create a burn-in pattern, the operator inputs setting information for creating a command file 21, a counter file 22, a pattern file 23, and a data file 24 to the control PC 2, as shown in FIG. The control PC 2 converts the setting information by the conversion means 2a to generate a command file 21, a counter file 22, a pattern file 23, and a data file 24.
FIG. 4 is a diagram illustrating an example of the command file 21. FIG. 4A shows a command group of the SDRAM. The command file includes a command used for the burn-in test selected from the command group and each signal line when the selected command is issued. The logic level (hereinafter referred to as command details) is set.
FIG. 2B shows an example of details of the command. The example in the figure shows the logic level of each signal line when the command “ACT” is issued. As shown in the figure, when “ACT” is issued, CS is 0, RAS is 0, CAS is 1 and WE is 1.

FIG. 5 is a diagram illustrating an example of the counter file 22. In the counter file, as shown in FIG. 5A, the maximum value of the ROW address, the maximum value of the COLUMN address, the counter value of the ROW address, and the counter value of the COLUMN address are set.
The value of the ROW address and the COLUMN address is incremented by 1. When the value of the ROW address exceeds the maximum value, the address value returns to the initial value 1. Similarly, when the value of the COLUMN address exceeds the maximum value, The value returns to the initial value 1. For example, as shown in FIG. 5B, when the memory cell is a 4 × 4 matrix, the maximum value of the ROW address is 4 and the maximum value of the COLUMN address is 4.
Further, the counter value of the ROW address and the counter value of the COLUMN address are the number of executions in the ROW address direction and the COLUMN address direction. For example, when the memory cell is a 4 × 4 matrix as shown in FIG. When the same data is written to the memory cell in the range of the ROW address 1 to 4 and the COLUMN address 1 to 4, the number of executions is set to 4 as shown in FIG. For example, 0 is written to the memory cell when the ROW address is 1 to 2 and the COLUMN address is 1 to 2, and 1 is written to the memory cell when the ROW address is 3 to 4 and the COLUMN address is 3 to 4. In this case, the number of executions is set to 2. Then, as will be described later, when the number of executions in the ROW address direction and the COLUMN address direction reaches a set value, for example, data written in the semiconductor element is inverted.

FIG. 6 is a diagram illustrating an example of the pattern file 23. In the pattern file, the execution order of commands input to the semiconductor device to be tested in the burn-in test is set. In the example of FIG. 6, the pattern name A is first set by “PAT A”, and then the command “MRS” for setting the mode register of the semiconductor device to be tested is set.
Next, “ABC:” which is the label name of the branch destination is set, and then a command which is repeatedly given to the semiconductor device to be tested during the burn-in test is set.
In this example, the commands “ACT”, “WRITE”, and “PRE” are executed to write data to the semiconductor element, and the operation of returning to the label “ABC:” with “JUMP1” and “JUMP2” is repeated.
Here, whenever “JUMP1” and “JUMP2” jump to the label ABC, the ROW address counter value is incremented by one, and when the counter value exceeds the number of executions set in the counter file, the initial value is returned to 1. Each time the counter value exceeds the number of executions, the counter value of the above-mentioned COLUMN address is incremented by 1, and when the counter value exceeds the number of executions set in the counter file, the initial value is returned to 1.
The ROW address and COLUMN address values are set according to the ROW address counter value and the COLUMN address counter value, and before the ROW address and the COLUMN address value reach the maximum value of the address set in the counter file, When the counter value reaches the execution count (for example, when the maximum value of the address is set to 4 and the execution count of the counter is set to 2), the value of the ROW address and the COLUMN address is incremented by 1 until the maximum value is reached. When the maximum value is reached, the initial value 1 is restored.

Although not shown, the data file 24 is set with a value (1 or 0) of data written to the semiconductor device to be tested.
The input of the setting information in the control PC 2 may be performed by an operator by inputting the setting information of a command file, a counter file, a pattern file, and a data file. By doing so, it becomes possible to set relatively easily.
(i) For each semiconductor device to be tested, information such as detailed command information, address range, command execution order, etc. is set in advance and stored in the control PC 2 as a library. A semiconductor device to be tested is selected on the menu screen or the like, and the command information, counter information, pattern information, or the like is set on the menu screen or the like.
(ii) Store the setting information of the existing command file, counter file, pattern file, and data file, and the operator calls these existing setting information and edits a part to create the setting information. To do.

Returning to FIG. 3, when the command file 21, counter file 22, pattern file 23, and data file 24 are generated as described above, the information set in the file is sent to the control unit 1, and the command data register 111, counter The data register 112, the pattern data register 113, and the data register 114 are set.
The waveform output control unit 115 of the burn-in pattern generation unit 11 creates a burn-in pattern signal based on the information set in the registers 111 to 114, and this burn-in pattern signal is output to the backboard 31 to determine the test target. Is applied to the semiconductor device, and a burn-in test is performed.

FIG. 7 is a diagram showing a configuration example of the waveform output control unit 115 provided in the burn-in pattern generator 11.
In the figure, reference numeral 120 denotes a mode register setting signal generating unit. When the mode register setting command “MRS” is set in the pattern data register 111, the mode register setting signal generating unit 120 is connected to the semiconductor device to be tested. Outputs a signal to initialize the mode register.
The register setting unit 121 converts each command set in the pattern data register 113 to the logic level of each signal line based on the details of the command set in the command data register 111 and stores it in the control signal storage register 122. . Also, the label “ABC” and branch commands “JUMP1” and “JUMP2” are set in the control signal storage register 122.
The logic level of each signal line set in the control signal storage register 122 is sequentially output from the control signal generator 132 in accordance with the timing signal output from the generation timing controller 131.
The ROW direction execution count, COLUMN direction execution count, ROW address maximum value, and COLUMN address maximum value set in the counter data register 112 are respectively the ROW direction execution count register 123, the COLUMN direction execution count register 124, and the ROW address. The maximum value register 125 and the COLUMN address maximum value register 126 are set.
Further, the data value set in the data register 114 is output from the data generation unit 134 in accordance with the timing signal output from the generation timing control unit 132.

The JUMP1 register 127 counts up when the count-up signal is output from the control signal storage register 122, and returns to the initial value when the count value exceeds the value set in the ROW direction execution count register 123 as described above. , The count-up signal of the JUMP2 register 128 is output. With this signal, the JUMP2 register 128 counts up and returns to the initial value when the count value exceeds the value set in the COLUMN direction execution count register 124 as described above.
When the values of the JUMP1 register 127 and JUMP2 register 128 exceed the number of executions described above, a signal for inverting the data is output when the value of data to be written is switched from 1 → 0, 0 → 1.
The value of the JUMP1 register 127 is set in the ROW address register 129. Each time the JUMP1 register 127 counts up, it is incremented and returns to the initial value when the address value exceeds the address value set in the ROW address maximum value register 125. .
Similarly, the value of the JUMP2 register 128 is set in the COLUMN address register 130. The value is incremented every time the JUMP2 register 128 counts up. Return to value.
The address value of the ROW address register 129 and the address value of the COLUMN address register 130 are output from the address generation unit 133 according to the timing signal output from the generation timing control unit 131.

FIG. 8 is a diagram for explaining changes in the ROW address and the COLUMN address when the maximum value of the ROW address and the maximum value of the COLUMN address are set to 4 when the memory cell is a 4 × 4 matrix.
As shown in FIGS. 5A and 5B, the column address register 130 is set to an initial value 1, the value of the row address register 129 is incremented by 1, and the value of the row address is changed in the state where the column address = 1. It varies from 1 to 4. Next, the value of the COLUMN address register 130 becomes 2, and the ROW address changes from 1 to 4 in a state where the COLUMN address = 2. Hereinafter, similarly, the value of the col address is changed from 1 to 4 while the value of the ROW address is changed from 1 to 4, and the value of the COLUMN address reaches the maximum value 4, and the value of the COLUMN address is set to the initial value 1. Return to repeat the above operation.

Next, the operation of the waveform output control unit 115 shown in FIG. 7 in the case where the data shown in FIGS. 5 and 6 is set in the counter file and the pattern file will be described.
(i) In response to the command MRS stored in the pattern data register 113, the mode register setting signal generator 120 sets the mode register setting signal of the semiconductor device to be tested.
(ii) The label “ABC:” stored in the pattern data register 113 is set in the control storage register 122. Further, referring to the command data register 111, the logic level of each signal line (CLK, RAS, CAS, etc.) when the commands “ACT”, “WRITE”, “PRE” are issued is obtained, and this is used as the command. Are arranged in the execution order, and are set in the control storage register 122.
In FIG. 9, CLK (clock), RAS (row address strobe), CAS (column address strobe), WE (write enable), and CE (chip) when the above commands “ACT”, “WRITE”, and “PRE” are executed. Enable), DATA (data), and ADDR (address) signals.
As shown in the figure, in the ACT command, an address signal is output in synchronization with RAS, and in the WRITE command, ADDR (address) and DATA (data) are output in synchronization with CAS.

(iii) JUMP 1 and JUMP 2 are set in the control signal storage register 113.
(iv) The initial value “1” is set in the JUMP1 register 127, the JUMP2 register 128, the ROW address register 129, and the COLUMN address register 130.
(v) The ROW and COLUMN direction execution counts set in the counter data register 112 are set in the ROW direction execution count register 123 and the COLUMN direction execution count register 124. The ROW address maximum value and the COLUMN address maximum value are set in the ROW address maximum value register 125 and the COLUMN address maximum value register 126, respectively.
(vi) When the output control signal is given from the burn-in test control unit 12, the generation timing control unit 131 first generates a mode setting signal from the mode register setting signal generation unit 120. Next, the logic logic levels of the signal lines of the commands “ACT”, “WRITE”, and “PRE” are sequentially read from the control signal storage register 122 and output from the control signal generator 132 in order.
Further, the data set in the data register 114 is output from the data generator 134 at the timing shown in FIG.
Further, the ROW address is output from the ROW address register 129 at the timing shown in FIG. 9, and the COLUM address is output from the COLUM address register 130 at the timing shown in FIG.

(vii) When JUMP is read from the control signal storage register 122 by the generation timing control unit 131, the JUMP1 register 127 is counted up (+1), and this value is set in the ROW address register 129.
Then, the control signal storage register 122 returns to the position labeled “ABC:”, and similarly to the above, the logic logic level of each signal line is read sequentially from the control signal storage register 122, and the control signal is output from the control signal generator 132. Output. Similarly to the above, data and address are output.
(viii) The above operation is repeated, and every time JUMP is read from the control signal storage register, the JUMP1 register is counted up (+1), and the count value of the JUMP1 register 127 is the value set in the ROW direction execution count register 123 When 4 is exceeded, the JUMP1 register returns to the initial value 1, and the JUMP2 register 128 is incremented (+1). Also, the value of the JUMP2 register 128 is set in the COLUMN address register 130.
When the value of the JUMP2 register 128 exceeds the value 4 set in the COLUMN direction execution count register 130, the JUMP2 register 128 is returned to the initial value 1.

Here, when the JUMP1 register 127 and the JUMP2 register 128 are returned to the initial values as described above, the values of the ROW address register 129 and the COLUM address register 130 are the values of the ROW address maximum value register 125 and the COLUM address maximum value register 126, respectively. If it does not exceed, the values of the ROW address register 125 and the COLUM address register 126 are incremented by 1 each time the JUMP1 register 127 and the JUMP2 register 128 are counted up until the values of these registers exceed the maximum value.
When the values of the ROW address register 129 and the COLUM address register 130 exceed the values of the ROW address maximum value register 125 and the COLUM address maximum value register 126, the values of these registers are returned to the initial values.
Further, when the JUMP1 register 127 and the JUMP2 register 128 are returned to the initial values, the DATA value is inverted according to the setting.
In the above embodiment, the case where the waveform output control unit is configured by hardware has been described. However, the waveform output control unit is configured by a processor and the above processing is performed by software to generate a burn-in pattern signal. Also good.

It is a figure which shows the structural example of the burn-in apparatus of the Example of this invention. It is a figure which shows the function structure of control PC of a present Example, and the schematic structure of a burn-in pattern generation part. It is a figure which shows the preparation procedure of the burn-in pattern of a present Example. It is a figure which shows an example of a command file. It is a figure which shows an example of a counter file. It is a figure which shows an example of a pattern file. It is a figure which shows the structural example of a waveform output control part. It is a figure explaining the change of a ROW address and a COLUMN address. It is a figure which shows CLK, RAS, CAS, WE, CE, DATA, and ADDR signals in ACT, WRITE, and PRE. It is a figure which shows the structural example of a burn-in apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control unit 1a Control part 1b Driver 1c Power supply unit 11 Burn-in pattern generation part 12 Burn-in test control part 111 Pattern data register 112 Command data register 113 Counter data register 114 Data register 115 Waveform output control part 2 Control computer (control PC)
2a Data conversion means 21 Pattern file 22 Command file 23 Counter file 30 Constant temperature bath 31 Backboard 32 Burn-in card

Claims (3)

A burn-in pattern signal in a burn-in apparatus that inputs a burn-in pattern signal output from a signal generator to a semiconductor device to be tested stored in a burn-in tank and burns in the semiconductor device,
A command file that converts the input setting information and gives the command given to the semiconductor device, the state of each signal line of the semiconductor device to be tested when the command is issued, and the address range to be tested Generating a counter file describing the number of executions, a pattern file describing the execution order of commands given to the semiconductor device, and a data file describing a data signal input to the semiconductor device,
A burn-in pattern generation method for generating a burn-in pattern signal for performing a burn-in test of the semiconductor device based on information described in the command file, counter file, pattern file, and data file. A burn-in pattern signal generating device in a burn-in apparatus that inputs a burn-in pattern signal output from a signal generator to a semiconductor device to be tested stored in a burn-in tank and burns in the semiconductor device,
A command file that converts the input setting information and gives the command given to the semiconductor device, the state of each signal line of the semiconductor device to be tested when the command is issued, and the address range to be tested A counter file describing the number of executions, a pattern file describing the execution order of commands given to the semiconductor device, and means for generating a data file describing values of data signals input to the semiconductor device;
Burn-in pattern signal generation means for generating a burn-in pattern signal for performing a burn-in test of the semiconductor device based on the value of the data signal described in the command file, the counter file, the pattern file, and the data file. A burn-in pattern creation device characterized by that. The burn-in pattern generating means is:
Generates control signals to be input to the semiconductor device under test based on the execution order of the commands described in the pattern file and the state of each signal line when each command described in the command file is issued Control signal generating means for
Based on the branch information described in the command file, the address range described in the counter file, the number of executions, the address signal generating means for generating an address signal, and the value of the data signal described in the data file, 3. The burn-in pattern generation apparatus according to claim 2, further comprising data signal generation means for generating a data signal.

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