JP2002341378A - Thin film transistor panel and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT(thin film transistor) panel in which the probability of occurrence of a failure caused by the abnormal shot of a laser beam is made to be small as much as possible and a liquid crystal display device. SOLUTION: In this TFT panel, transistors are formed in a polycrystalline silicon film on a substrate and the polycrystalline film is formed by irradiating the amorphous silicon film formed on the substrate with a laser-beam shot 17 having a slender rectangular section by shifting the shot in its width direction and, in the driving circuit area 19 of the TFT panel, first and second transistors 30 in the transistors are arranged so as to form a line along a line of a straight line parallel with the longitudinal direction of the section of the laser beam by making the channel width direction of the transistors 30 to be parallel with the longitudinal direction of the laser beam.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor
The present invention relates to an active matrix type TFT panel provided with (TFT: Thin Film Transistor) and a liquid crystal display device.

[0002]

2. Description of the Related Art (1) Driving Circuit of Liquid Crystal Display First, a driving circuit of an active matrix type liquid crystal display will be described. FIG. 7 is a diagram illustrating an outline of a wiring system of the liquid crystal display device. In the display area 110, signal lines 105 and scanning lines 106 are arranged so as to intersect in a matrix. A liquid crystal display element 109 including a pixel portion switching element, a pixel electrode, and a liquid crystal is provided at an intersection of the signal line and the scanning line. This display area 110
Is divided into, for example, four blocks together with the signal lines. The driving circuit includes a signal line driving circuit 119 disposed in the X-side driving circuit area along the X-axis and a scanning line driving circuit 1 disposed in the Y-side driving circuit area along the Y-axis.
02. The signal line driving circuits 119 are provided as many as the number of signal line driving circuits 119 so as to correspond to each block. Video signal 131, 132, 1 of each block
33 and 134 are supplied to each signal line drive circuit 119 via the I / O interface 129. The drive control signals 141, 142, 143, 144 of each block are also supplied to each signal block drive circuit 119 via the I / O interface 129. The scanning line drive control signal 130 for controlling the driving of the Y-side drive circuit is supplied to the shift register 1
51, the level shifter 152, and the buffer 153 are supplied to each scanning line 106.

One signal line driving circuit is responsible for driving 768 signal lines. The number of the signal lines can be changed according to the image quality grade. I / O interface 1
29, the video signal is supplied from the signal processing circuit 122 including the video signal rearranging circuit 124 to the signal drive circuit. Further, the I / O interface 129 is supplied with a drive synchronization signal from the timing circuit 121 including the drive direction switching timing output circuit 123 to the scan line drive circuit and the signal line drive circuit.

FIG. 8 is a schematic configuration diagram showing the contents of a signal line block driving circuit for blocks 1 and 2. The drive start signal is input via the input line 161, and the drive direction switching signal is transmitted via the drive direction switch signal line 118 to the drive direction switching circuit 1.
12 is input. The start signal and the switching signal are both output from the timing circuit 121. These two signals pass through the drive direction switching circuit 112 and are transmitted to the shift register 11.
3 and further via buffer circuit 114 to n
It is supplied to an analog switch 116 composed of a p-type transistor and a p-type transistor. These signals drive the signal lines in a predetermined direction. The video signal is input from the video signal input line 117 to the analog switch 116 via the video signal rearranging circuit, and applies the video signal voltage from the analog switch 116 to the pixel electrode in the display area. Each analog switch 116 supplies a video signal voltage to 24 signal lines. Since 32 analog switches 116 are arranged in each block, a total of 768 signal lines 1 are provided.
05 is included in one block. As described above, this number can be increased or decreased according to the target image quality grade. In the video signal, the video signal rearrangement circuit 124 included in the signal processing circuit 122 has already rearranged the video signal necessary for the reversal of the driving direction based on the signal provided from the timing circuit 121. . Therefore, even if the driving direction is reversed, the video signals are rearranged accordingly, and a normal screen is displayed.

The timing circuit is provided with a drive direction switching timing circuit 123 for determining the timing for switching the drive direction, and reverses the drive direction for each frame, for example.

FIG. 9 is a schematic configuration diagram of a portion from the shift register 113 to the analog switch 116. The analog switch control signal output from the shift register 113 is input to the buffer circuit 114 via the analog switch control signal line 173. In the buffer circuit, the p-type transistor and the n-type transistors 171 and 172 are operated according to the switching of the driving direction, and a positive voltage or a negative voltage is applied to the signal line. Such a reversal of the polarity of the voltage is usually performed in order to avoid the abnormal operation of the liquid crystal when one voltage is continuously applied to the liquid crystal.

The above signal line driving circuit and scanning line driving circuit include basic logic circuits such as an inverter circuit,
Flip-flop circuits and other logic circuits are periodically arranged for each signal line (scanning line) or for a predetermined number of signal lines (scanning lines). (2) Manufacturing Method of Liquid Crystal Display Device In a TFT panel in which a display region and a drive circuit region are integrated, polycrystalline silicon is used for at least the drive transistor, apart from the pixel transistor. TFT
When the polycrystalline silicon film is formed integrally over the display region and the drive circuit region of the panel, the following method is used. (A) An amorphous silicon film is formed on a substrate by a low pressure CVD method or the like. Then, as shown in FIG.
(B) Pulse laser 170 using an excimer laser device
Is irradiated on the amorphous silicon film 131 on the substrate 101 while being shifted in the width direction 126 to be crystallized into polycrystalline silicon 132. Normally, the energy distribution of the cross section of the laser shot has a distribution as shown in FIG. The peak width 175 of the beam cross section is, for example, generally 30
0-400 μm range, length 174 is 150-400 m
m. When laser irradiation is performed while shifting the laser shot in the width direction, as shown in FIG. 12, scanning is performed in the width direction at a constant width pitch P while overlapping the energy peak portions of the laser shot cross section.
That is, the longitudinal direction of the beam cross section is parallel to the Y direction of the display panel, and the width direction 126 is aligned with the X direction.
Pulse exposure is performed at a period of about 200 to 300 Hz while shifting in the X direction by 5 to 50 μm for each shot (pulse).

The reason why the thin film semiconductor is a polycrystalline silicon film is to ensure high mobility of charge carriers in a transistor. Since the mobility of charge carriers in amorphous silicon is much lower than that in polycrystalline silicon, amorphous silicon cannot be used for a driving transistor. Conventionally, when a display region and a drive circuit region were not formed integrally, amorphous silicon was used for a pixel transistor in the display region, and single crystal silicon was used for a drive transistor manufactured in a separate process. . Although the mobility of charge carriers in polycrystalline silicon is smaller than that in single crystal silicon, the required mobility can be secured by increasing the crystal grain size. For this reason, the energy density of the above-mentioned laser beam must be such that the amorphous silicon is polycrystallized and the crystal grain size is further appropriately increased. The energy density of a laser beam satisfying these conditions is limited to a narrow range having a height limit, but not so great as to cause a great difficulty in implementation.

However, the energy density of the above-mentioned laser beam does not fall within an appropriate range for all shots. That is, an abnormal shot occurs on the order of about once every tens of thousands of shots, and deviates from the above-described appropriate energy density range to a higher or lower side. At present, no means has been found to prevent this abnormal shot, which occurs at a very low frequency.

In areas where the adverse effects of the above-mentioned abnormal shots remain, a region having a width corresponding to one scan pitch, which is a shift distance between consecutive shots, generally does not have a sufficiently large crystal grain size. For example, when the pitch is 15 μm,
The grains do not become sufficiently coarse over a width of about 15 μm and a length of 150 to 400 mm. The phenomenon that the crystal grain size is insufficiently coarsened occurs, though varying in degree, when the energy density of the beam is too small or too large.

For this reason, when the beam is scanned in the channel length direction in an arrangement in which the channel width direction of the TFT is parallel to the longitudinal direction of the beam cross section, the following problem occurs.
That is, when an abnormal shot occurs in the TFT channel region, a region where crystal grain coarsening is insufficient is formed by blocking the channel region. As a result, charge carriers passing through the channel in this part of the transistor are:
When passing between the source and the drain, the crystal grains necessarily cross the region where the coarsening is insufficient. As a result,
This TFT cannot operate normally and becomes a defective product. Even if the region where the crystal grains are not sufficiently coarsened is over the channel region, if the channel region is not formed by blocking the channel region, the charge carriers pass only through the region where the crystal grains are sufficiently grown and cross the channel region. be able to.

The drive circuit is manufactured as an integrated circuit on the polycrystalline silicon film formed as described above. In the case where the transistors are connected in parallel as in an analog switch or the like, even if some of the transistors become defective, it is possible to operate the TFT without any serious trouble. For this reason, the transistors are arranged obliquely with respect to the longitudinal direction of the laser beam cross section, or are arranged in a zigzag direction which is a superposition of the oblique directions, and all transistors in one row at a time become defective. Can be avoided (Japanese Patent Application Laid-Open No. 11-87720, Japanese Patent Application No. 11-349010, etc.).

[0013]

However, the transistors occupying most of the driving circuit constitute a continuous logic circuit. In such a logic circuit, if even one of the transistors becomes defective, the entire logic circuit is hindered.

Usually, in a drive circuit, since inverters and analog switches are combined in any number of stages to form a circuit, the arrangement is such that the directions of the transistors are not aligned in a conscious manner. For example, as shown in FIG.
Are arranged without aligning the channels 151 sandwiched between them. In the case of FIG. 13, since the abnormal shot 147 of the laser has a width, any channel of any one of the three transistors is slightly interrupted. The length D in the laser pitch direction is the length of the three channel portions. It becomes larger than 3L.
The arrangement shown in FIG. 13 is an extreme case where the channels 151 of the three transistors are arranged continuously from one end to the other. If the channels are not aligned as described above, the channels are interrupted by an abnormal laser shot. The probability is high.

Further, in the above-mentioned driving circuit, an enormous number of logical circuits in which two transistors such as an inverter circuit are connected in series are naturally formed. Conventionally, in the inverter circuit provided in the signal line driving circuit region 119, the width direction of the channel of the transistor is parallel to the Y axis,
That is, the two transistors were along separate lines, parallel to the length of the laser shot. That is, as shown in FIG. 15 in which the B and C parts in FIG. 14 are enlarged,
The two series-connected transistors that constitute the inverter circuit are arranged on different straight lines along the channel width direction.

As shown in FIG. 16, the channel of the n-type transistor and the channel of the p-type transistor which constitute the inverter circuit arranged in the signal line driving circuit region are:
They were arranged so that they did not line up. When the period in the signal line drive circuit of the inverter circuit is S, in such an arrangement, the probability of the abnormal shot blocking the channel is proportional to the transistor arrangement factor (2L) / S. The defect caused by the abnormal shot actually depends on the probability that the excimer laser makes an abnormal shot.
When a failure occurs, the TFT panel cannot be used. Therefore, it is desired to reduce the probability of the failure as much as possible.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a TFT panel and a liquid crystal display device which minimize the probability of occurrence of a defect due to an abnormal laser shot in a drive circuit including a series connection.

[0018]

A TFT panel according to the present invention is a TFT panel having a display area and a drive circuit area formed on a substrate, and driving liquid crystal in a liquid crystal display device. In this TFT panel, a transistor on the TFT panel is formed on a polycrystalline silicon film on a substrate, and the polycrystalline silicon film is formed on an amorphous silicon film formed on the substrate by a thin rectangular cross section. This is formed by irradiating a laser beam shot while shifting it in the width direction. In the drive circuit region, the first transistor and the second transistor among the transistors are arranged so that the channel width direction is the rectangular cross section of the laser beam. Parallel to the longitudinal direction, and along one straight line parallel to the longitudinal direction.
They are arranged in a line (claim 1).

Further, the TFT panel of the present invention is a TFT panel having a display area and a drive circuit area formed on a substrate, and for driving a liquid crystal in a liquid crystal display device. In this TFT panel, in the drive circuit region, the first transistor and the second transistor among the transistors on the TFT panel have their channel width directions parallel to one straight line, and follow the one straight line. (Claim 2).

According to this configuration, two or more transistors in the drive circuit region are arranged in a line along the common virtual straight line with the channel width direction parallel to one common straight line. For this reason, the probability that the channel is cut off due to the abnormal shot can be reduced in any one of these transistors as compared with the case where two or more transistors are arranged along different straight lines.

The present inventors have completed an invention for preventing a plurality of transistors connected in parallel from interrupting a channel portion of a large number of transistors due to one abnormal shot by an abnormal shot (Japanese Patent Application Hei 11-349010).
However, in the driving circuit, the transistors are not limited to transistors connected in parallel. In particular, in the case of an inverter circuit formed by two transistors connected in series, it may be desirable to adopt a configuration different from the configuration of the transistors connected in parallel.

For example, if the channel of one of the TFTs connected in series is cut off by a region where the crystal grain size is insufficiently grown, a pixel circuit in which a logic circuit is connected to a signal line connected in series Column does not work properly. In such a case, there is no difference between the case where all the TFTs constituting a predetermined portion of the serially connected logic circuit fail simultaneously and the case where one of the TFTs fails. Therefore, if the probability that one TFT in such a predetermined portion becomes defective can be reduced, the probability that all the TFTs constituting the predetermined portion become defective simultaneously and the probability that one TFT becomes defective are reduced. May be the same. This is because even if one TFT becomes defective or all the TFTs become defective, the logic circuit becomes defective.

Based on the above concept, the present invention has a configuration in which the channel width direction of a plurality of transistors is parallel to one straight line, and the transistors are arranged in a line along one straight line. The one straight line is a virtual straight line. The same applies to the second straight line described later.

In the above-described TFT panel of the present invention, the thin-film transistor panel includes a plurality of first signal lines and a plurality of second signal lines that are wired in an intersecting manner, and a plurality of pixel transistors located at the intersections. Region, a first signal line circuit region positioned to intersect in a direction in which the first signal line extends along a periphery of the display region, and a second signal line circuit region positioned to intersect in a direction in which the second signal line extends. A driving circuit region including a signal line circuit region, wherein in the first signal line circuit region, first and second transistors are arranged for every predetermined number of first signal lines, and a first transistor and a second transistor are provided. Can be arranged so that their channel width direction is parallel to one straight line and are arranged in a line along the one straight line (claim 3).

According to this structure, two or more transistors arranged at a predetermined number of corresponding pitches are arranged so as to be arranged in a line with the channel width direction along one common virtual straight line. Therefore, the probability that the channel is interrupted by an abnormal shot can be reduced in any one of the transistors, as compared with a case where two or more transistors are arranged along different straight lines.

The one straight line is a predetermined number of first straight lines.
For each signal line, for example, one straight line parallel to each other is determined for each length cycle S in the X direction.
Arranged in columns.

In the TFT panel of the present invention, it is desirable that one straight line is substantially parallel to the first signal line.

Scanning of the substrate arrangement and laser beam during laser annealing, and wiring of signal lines and scanning lines are performed.
It can be done simply and clearly. Further, by making the longitudinal direction of the laser beam cross section along the signal line or the scanning line, damage of an abnormal shot can be limited to a small range.

In the above-described TFT panel of the present invention, the first and second transistors and the transistor arranged in the pixel in the display area are arranged such that their channel width directions are parallel to each other.
They can be arranged in a line along the straight line of the book (claim 5).

With this configuration, it is possible to reduce the probability of occurrence of a failure due to an abnormal shot, including not only the transistors in the drive circuit region but also the transistors in the drive circuit region and the pixel transistors.

In the TFT panel of the present invention, the first and second transistors arranged in one line along one straight line can be transistors of the constituent elements included in the logic circuit. 6).

As a result, even in any one of the two transistors constituting the logic circuit, the probability of occurrence of a failure in the logic circuit due to an abnormal shot can be reduced. The logic circuit may be an inverter circuit, a NOT circuit, a NA
Anything such as an ND circuit and a flip-flop circuit may be used.

In the above-mentioned TFT panel of the present invention, the first and second transistors arranged in one row are located at equal pitch regions of the first signal line circuit region corresponding to a predetermined number of first signal lines. (Claim 7).

According to this configuration, the transistors can be arranged collectively in a line with the channel width direction periodically superposed on one straight line. For this reason, the above-described failure occurrence probability can be reduced over the entire first signal line circuit region. Further, in the sense that the same arrangement is repeated, the labor for designing the TFT panel can be reduced. The above-mentioned equal pitch may be the pitch of the first signal lines, or may be the pitch of a plurality of first signal lines.

In the TFT panel according to the present invention, a second straight line parallel to one straight line is defined in the second signal line circuit area, and at least two transistors arranged in the second signal line circuit area include the second straight line. The channel width direction may be parallel to the second straight line and arranged in a line along the second straight line (claim 8).

According to this configuration, even in the second signal line circuit area, the probability of occurrence of a defect due to an abnormal shot can be reduced as compared with a case where transistors are arranged without taking control of the whole. Note that the second straight line is
One is defined over the second signal line circuit area.

In the TFT panel of the present invention, the at least two transistors arranged in a line along the second straight line can be the constituent transistors included in the logic circuit.

With this configuration, it is possible to reduce the probability that the logic circuit causes a failure in an abnormal shot. The logic circuit may be an inverter circuit, a NOT circuit, a NA
Anything such as an ND circuit and a flip-flop circuit may be used.

In the TFT panel of the present invention, the transistors arranged in the second signal line circuit area can be arranged so that the channel width direction intersects one straight line.

In this configuration, the longitudinal direction of the laser beam is parallel to the channel length direction. For this reason, even if the abnormal shot may reach the channel region of the transistor in the second signal line circuit region, the abnormal shot is not arranged so as to cut off the channel length. Therefore, the transistor in the second signal line circuit area does not fail due to the abnormal shot.

In the TFT panel of the present invention, the first signal line is a signal line, the first signal line circuit area is a signal line circuit area, the second signal line is a scanning line, and the second signal line circuit is The region may be a scanning line circuit region.
1). The first signal line is a scanning line, the first signal line circuit region is a scanning line circuit region, the second signal line is a signal line, and the second signal line circuit region is a signal line circuit region. (Claim 12).

In any case, the generation of defective transistors due to abnormal shots in laser annealing can be minimized, and the process of manufacturing wiring and the like can be made simple and clear.

A liquid crystal display device according to the present invention is a liquid crystal display device comprising a liquid crystal and any one of the above-mentioned TFTs arranged for driving the liquid crystal.

With this configuration, a high yield and therefore an inexpensive TFT panel can be obtained, so that an inexpensive liquid crystal display device can be provided.

[0045]

Embodiments of the present invention will now be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing an arrangement of transistors in a signal line drive circuit region of a TFT according to Embodiment 1 of the present invention. In the signal line circuit region 19, the transistors 30 are arranged so as to overlap with one straight line parallel to the longitudinal direction of the cross section 17 of the laser beam. As a matter of course, the channel 31 and the source / drain portions 32 and 33 are also located so as to overlap the straight line parallel to the longitudinal direction.

In the case where the transistors have such an arrangement, when an abnormal shot cuts off the channel, 3 in FIG.
Block all channels of the transistors. Therefore, when a transistor becomes defective due to an abnormal shot, all three become defective. However, in the case of the arrangement shown in FIG. 1, the probability that one transistor becomes defective is smaller than that in the case of the arrangement shown in FIG.
The extent is roughly one third. In a signal line circuit, a transistor constituting a logic circuit is usually
If even one becomes defective, the logic circuit malfunctions.
It cannot be used as a TFT for a liquid crystal display device. Therefore, 1
The defect of one transistor is the same as the defect of all transistors. Therefore, by adopting the above arrangement, the probability that any one transistor becomes defective can be reduced, which leads to a large improvement in yield.

As a result, by using a simple method of aligning and arranging the channels in one straight line parallel to the longitudinal direction of the laser beam cross section at the design stage, defective TFTs caused by abnormal laser shots can be eliminated. It is possible to prevent occurrence.

(Embodiment 2) FIG. 2 is a schematic diagram showing a liquid crystal display device according to an embodiment of the present invention. A signal line circuit area is formed on the lower edge 19 of the display area 10, and a scanning line circuit area is provided on both sides 2 a and 2 b of the display area 10. In FIG. 2, the drive circuit area is shown larger than it actually is. Signal line circuit area 1
In FIG. 9, an inverter circuit 15 including an n-type transistor 3n and a p-type transistor 3p connected in series is arranged, and the direction of the channel width W of these two transistors is aligned in the Y direction and overlaps each other. That is, the gate G
Are overlapped in the longitudinal direction. In FIG. 2, the straight line parallel to the channel width direction and along one row can be considered as a straight line (virtual one straight line) along the gate passing through the center of the gate G.

Vss is a ground voltage, and Vdd is an external drive voltage for driving the transistor. This inverter circuit outputs a voltage opposite to the high / low voltage input at IN to OU.
This is a circuit that outputs to T and transmits to the next connected logic circuit.

A large number of such inverter circuits are incorporated in the signal line circuit area for every predetermined number of signal lines.
Two transistors constituting the inverter circuit shown in FIG. 2 are arranged in a line with the same channel width W in the same direction. That is, the gates G of the two transistors 3n and 3p overlap. In FIG. 3, a length cycle S in the X direction in which the inverter circuits are arranged is determined by a predetermined number of corresponding signal lines. That is, the cycle S can be considered to be the length in the X direction of the signal line drive region per signal line, or an integral multiple thereof. With the above arrangement, the transistor arrangement factor that causes a defect due to the abnormal shot is L / S, which is reduced to half of the conventional transistor arrangement factor. As a result, the occurrence of malfunctions due to abnormal shots can be reduced by half, which can contribute to an improvement in yield.

In FIG. 2, the inverter circuit in the scanning line circuit area 2a includes any of the transistors 23n, 23p,
Similarly to the inverter circuits in the signal line circuit area, the channels 24n and 24p are arranged in a line along the straight line (virtual second straight line) along the direction of the channel width W. Have been. This one straight line can be considered as a straight line passing through the center of the gate along the gate G. By setting the inverter circuits in the scanning line drive region 2a in the above arrangement, the probability of occurrence of a failure due to an abnormal shot can be reduced as compared with a configuration in which the transistors are randomly shifted in the X direction.

(Embodiment 3) FIG. 4 is a schematic diagram of a liquid crystal display device according to Embodiment 3 of the present invention. In the present embodiment, in the signal line drive region 19, the inverter circuit includes two transistors 3n, 3n, as in the first embodiment.
3p are arranged in one row along one channel G extending in the Y direction along the channel width direction. However, in the scanning line driving region 2a, the two transistors 23n and 24n forming the inverter circuit are arranged on two different gates G parallel to the X direction along the channel width W direction.

In the signal line drive region, as in the first embodiment, the probability of occurrence of a defect caused by an abnormal shot can be halved. In the scanning line driving region 2a, the laser shot is parallel to the channel length L direction.
Even if the laser shot is an abnormal shot,
The abnormal shot does not interrupt the channel length. Thus, the charge carriers can pass through the channel length through a portion that is not affected by the abnormal shot.
For this reason, even if an abnormal shot may hit the channel region, the abnormal shot does not interrupt the channel length, thereby preventing a problem.

(Embodiment 4) FIGS. 5 and 6 show a liquid crystal display device according to Embodiment 4 of the present invention. 5 and 6, one inverter circuit is arranged for each of the plurality of signal lines 5. The gate G of the pixel transistor 13 connected to one of the plurality of signal lines coincides with the direction G of the common gate of the two transistors of the inverter circuit 15. The pixel transistor 13 is disposed in a pixel region 9 where the signal line 5 and the scanning line 6 intersect. Usually, a plurality of pixel transistors are arranged in the pixel region 9 of the color display screen, and the pixel transistor 13 is one of them.

According to the above configuration, it is possible to reduce the probability that not only the transistors constituting the inverter circuit in the signal line driving region but also the channel portion of the pixel transistor will be defective due to an abnormal shot.

Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Not limited. For example, the scope of the present invention includes the following items. (A) The longitudinal direction of the cross section of the laser beam includes a case parallel to the signal line and a case parallel to the scanning line. (B) The set of transistors arranged in one line with the channel width direction along the same straight line is not limited to the inverter circuit. The case where the transistors constituting all the logic circuits such as the flip-flop circuit have the above arrangement is also included. A transistor which does not constitute a logic circuit may be included in the transistors having the above arrangement. (C) In the first signal line circuit area, one straight line is
This indicates that the transistors are arranged in a line with a plurality of straight lines overlapping the channel width direction. It goes without saying that the transistors may be arranged in more than one straight line. That is, any one of more than one straight line may be taken as the one straight line. The same applies to the second straight line in the second signal line circuit area. (D) A plurality of transistors arranged in a line with the channel width direction parallel to a straight line need not be connected to each other in series. A plurality of transistors whose series or parallel is not defined may be arranged in a line in the straight line.

The scope of the present invention is shown by the description of the claims, and further includes meanings equivalent to the claims and all modifications within the scope.

[0059]

By using the liquid crystal display device and the TFT panel of the present invention, even if an abnormal shot occurs during laser annealing of an amorphous silicon film to a polycrystalline silicon film, it does not immediately become a problem. A liquid crystal display device and a TFT panel having a structure can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a liquid crystal display device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating a liquid crystal display device according to Embodiment 2 of the present invention.

FIG. 3 is an enlarged view of an inverter in a signal line driving region of FIG. 2;

FIG. 4 is a diagram illustrating a liquid crystal display device according to Embodiment 3 of the present invention.

FIG. 5 is a diagram illustrating a liquid crystal display device according to Embodiment 4 of the present invention.

6 is a diagram showing a positional relationship between a pixel transistor in FIG. 5 and an inverter circuit in a signal line driving region.

FIG. 7 is a diagram illustrating an outline of a drive circuit of a general liquid crystal display device.

8 is a schematic configuration diagram of a signal line driving circuit of the liquid crystal display device of FIG.

FIG. 9 is a schematic configuration diagram of the analog switch of FIG. 8;

FIG. 10 is a diagram showing a laser shot scanning method in manufacturing an active matrix liquid crystal display device.

FIG. 11 is a diagram showing an energy distribution in a cross section of a laser shot.

FIG. 12 is a diagram illustrating a shift pitch of a laser shot.

FIG. 13 is a diagram illustrating an example of an arrangement of transistors in a driving circuit region of a conventional liquid crystal display device.

FIG. 14 is a diagram showing a display area and a drive area in a conventional liquid crystal display device.

FIG. 15 is a view showing that an inverter circuit is arranged in a signal line driving region and a scanning line driving region in a conventional liquid crystal display device.

FIG. 16 is an enlarged view of a portion B in FIG. 14;

[Explanation of symbols]

2a, 2b scanning line driving area, 3n inverter circuit n-type transistor, 3p inverter circuit p-type transistor, 5 signal lines, 6 scanning lines, 9 pixel areas, 10
Display area, 15 inverter circuit, 17 laser shot irradiation section, 19 signal line drive area, 23n, 23p, 24
n, 24p Transistor of the inverter circuit in the scanning line drive area, 30 transistors (MOS), 31 channels, 32 sources, 33 drains, L channel length, G gate, S Inverter circuit X direction cycle length, W channel width, Vss Ground voltage, Vdd External drive voltage.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 JA24 KA04 KA05 MA30 NA30 PA06 2H093 NA16 NC22 NC34 ND53 5F052 AA02 BA01 BA02 BA04 BA07 BB07 DA01 DB02 JA01 5F110 AA30 BB02 BB03 CC01 GG02 GG13 NN05 NN06 PP03 PP03

Claims (13)

[Claims] 1. A thin film transistor panel having a display region and a drive circuit region formed on a substrate and driving liquid crystal in a liquid crystal display device, wherein the transistor on the thin film transistor panel is a polycrystalline transistor on the substrate. And a polycrystalline silicon film formed by irradiating the amorphous silicon film formed on the substrate with a laser beam shot having a narrow rectangular cross section while shifting the width direction. In the drive circuit region, a first transistor and a second transistor among the transistors have their channel width directions parallel to the longitudinal direction of the rectangular cross section of the laser beam, and are parallel to the longitudinal direction. A thin film transistor panel arranged in a line along a straight line. 2. A thin film transistor panel having a display region and a drive circuit region formed on a substrate and driving liquid crystal in a liquid crystal display device, wherein in the drive circuit region, a transistor on the thin film transistor panel is provided. A thin film transistor panel in which a first transistor and a second transistor are arranged so that their channel width direction is parallel to one straight line and arranged in a line along the one straight line. 3. The thin film transistor panel includes a plurality of first signal lines and a plurality of second signal lines that are wired in an intersecting manner, and the display area including a plurality of pixel transistors located at the intersections thereof. A first signal line circuit area located along the edge of the display area so as to intersect with the direction in which the first signal line extends, and a second signal located so as to intersect with the direction in which the second signal line extends. A driving circuit region comprising a first circuit line region and a first circuit region, wherein the first and second transistors are arranged for every predetermined number of first signal lines in the first signal line circuit region; 3. The thin film transistor according to claim 1, wherein the transistors are arranged so that their channel width direction is parallel to the one straight line and arranged in a line along the one straight line. 4. Nell. 4. The thin film transistor panel according to claim 3, wherein said one straight line is substantially parallel to said first signal line. 5. The first and second transistors,
The thin film transistor panel according to any one of claims 1 to 4, wherein the transistors arranged in the pixels of the display area are arranged in a single line along the one straight line with their channel width directions parallel. 6. A first liner arranged in a line along the one straight line
The thin film transistor panel according to claim 1, wherein the second transistor and the second transistor are transistors included in a logic circuit and are constituent elements thereof. 7. The first and second transistors arranged in one row are located at equal pitch regions of the first signal line circuit region corresponding to the predetermined number of first signal lines, respectively. A thin-film transistor panel according to claim 1. 8. A second straight line parallel to the one straight line is defined in the second signal line circuit region, and at least two transistors disposed in the second signal line circuit region are arranged in a channel width direction. Are arranged in a line along the second straight line parallel to the second straight line.
8. The thin film transistor panel according to any one of claims 1 to 7. 9. The thin film transistor panel according to claim 8, wherein the at least two transistors arranged in a line along the second straight line are transistors included in a logic circuit and are constituent elements thereof. 10. The transistor according to claim 1, wherein the transistor arranged in the second signal line circuit region is arranged so that a channel width direction thereof intersects the one straight line. Thin film transistor panel. 11. The first signal line is a signal line, the first signal line circuit region is a signal line circuit region, and the second signal line circuit region is a signal line circuit region.
The thin film transistor panel according to claim 1, wherein the signal lines are scanning lines, and the second signal line circuit area is a scanning line circuit area. 12. The first signal line is a scanning line, the first signal line circuit region is a scanning line circuit region, and the second signal line is a scanning line circuit region.
The thin film transistor panel according to any one of claims 1 to 10, wherein the signal line is a signal line, and the second signal line circuit region is a signal line circuit region. 13. A liquid crystal display device comprising: a liquid crystal; and the thin film transistor according to claim 1 arranged to drive the liquid crystal.