JP2002269976A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device including a gain cell,
Satisfy RAM compatibility. SOLUTION: A first transistor (101) which is turned on according to the voltage level of a word line (WL) holds an information voltage transmitted from a data line via the first transistor and is based on the information voltage. When the memory cell is configured to include the second transistor (102) capable of outputting information, the second transistor is used as a source follower. As a result, the read information to the data line matches the logical value in the case of writing to the storage node, so that the data can be rewritten to the storage node as it is and DRAM compatibility is satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a PLED (Phase State Low).
The present invention relates to a technique effective when applied to a semiconductor memory device having a memory cell including an Electron number Drive) transistor.

[0002]

2. Description of the Related Art A random access memory (RAM) can be given as an example of a semiconductor memory device. Among them, a dynamic RAM (DRAM) is most widely used as a main memory of a computer. A memory cell for storing data is composed of one storage capacitance (capacitor) and a read transistor for reading out the charge stored therein. Since this memory is realized with the minimum components as a RAM, it is suitable for increasing the scale. Therefore, it has been produced in large quantities at relatively low cost. However, the problem of the DRAM is that the operation tends to be unstable. The biggest instability factor is that the memory cell itself does not have an amplifying effect, the read signal voltage from the memory cell is small, and the operation of the memory cell is easily affected by various noises. Furthermore, the information charge stored in the capacitor is lost due to a pn junction (leak) current existing in the memory cell.
Therefore, the memory cell is periodically refreshed (reproduced and written) before the memory cell disappears to retain the stored information.
This period is called a refresh time, and is 100 m at present.
s, but it is necessary to increase the length as the storage capacity increases.

[0003] PLED (Phase state Lo)
w Electron number number Drive)
The transistor has a multi-phase structure in which silicon is stacked in a sandwich structure in which silicon is separated by a thin insulating film.In a memory using the same, a cell structure in which a PLED transistor is stacked on the gate of a MOS transistor is employed to reduce the memory cell size. Reduction can be achieved. PL
ED transistors can increase the degree of integration without using a process technology or a state-of-the-art technology, so that the current processing technology can be diverted, and a large capital investment in a production line can be avoided.

A semiconductor memory device using a PLED transistor is disclosed, for example, in Japanese Patent Application Laid-Open No. 2000-11368.
As described in Japanese Unexamined Patent Application Publication No. 3 (1999) -2003, a memory cell can be composed of two transistors and one capacitor. A memory cell having such a configuration is called a gain cell or the like because it has a predetermined gain. That is, the memory cell includes a read transistor, a write transistor, and a coupling capacitor that controls the voltage of the memory cell node. One end of the electrode of the coupling capacitor and the gate of the writing transistor are connected to a word line WL, and one end of each of the reading transistor and the writing transistor is commonly connected to a data line.

[0005]

The inventors of the present invention have studied a gain cell using a PLED transistor, and found that the gain cell does not sufficiently satisfy the standard for compatibility with a DRAM. For example, P
When an information voltage of a logical value “1” is written in a memory cell using an LED transistor, the information voltage is read from the memory cell as a voltage of a logical value “0”.

In a DRAM, an information voltage read from a memory cell is read to the outside via a data line. In this case, information on the data line is amplified by a sense amplifier coupled to the data line, and the data voltage is read from the memory. The cell data is rewritten.

However, when a high-level information voltage is written in a memory cell using a PLED transistor, the information voltage is read from the memory cell as a low-level voltage, and is transmitted to a data line. On the other hand, the signal voltage amplified by the sense amplifier cannot be rewritten to the memory cell in the logical state as it is, and therefore cannot satisfy the DRAM compatibility standard, especially the refresh operation.

An object of the present invention is to provide a technique for satisfying DRAM compatibility in a semiconductor memory device including a gain cell.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a first transistor that is turned on in accordance with the voltage level of a word line, an information voltage transmitted from a data line via the first transistor is held, and information can be output based on the information voltage. Second
When a memory cell is configured including a transistor,
The second transistor is a source follower.

According to the above means, since the second transistor is a source follower, for example, the data line is set to the logical value "1" and the information voltage written in the memory cell is set to the logical value "1". The data line can be read as a logical value "0" and the information voltage written to the memory cell can be read as a logical value "0" to the data line. As described above, since the logical value matches the logical value in the case of writing to the storage node, rewriting to the storage node can be performed as it is, and DRAM compatibility is satisfied.

A first transistor which is turned on according to the voltage level of a word line, and an information voltage transmitted from the data line via the first transistor are held and an information output based on the information voltage is enabled. The second
When a semiconductor memory device is configured to include a transistor and a precharge circuit capable of precharging the data line to a low level, the second transistor is an n-channel type and is coupled to the first transistor. A first electrode for forming a storage node, a second electrode to which a voltage capable of pulling up the data line is supplied, and a third electrode for enabling information output based on the information voltage. Comprising.

According to the above means, the precharge circuit comprises:
The data line is precharged to a low level. The second transistor is an n-channel transistor, and is supplied with a first electrode for forming a storage node by being coupled to the first transistor, and a voltage capable of pulling up the data line. Since it includes two electrodes and a third electrode capable of outputting information based on the information voltage, for example, the data line is set to the logical value “1” and the information voltage written to the memory cell is changed to the logical value “1”. , And the information voltage written to the memory cell with the data line set to the logical value “0” can be read out to the data line as the logical value “0”. As described above, since the logical value matches the logical value in the case of writing to the storage node, rewriting to the memory cell can be performed as it is, and DRAM compatibility is satisfied.

A first transistor which is turned on in accordance with the voltage level of the word line, and an information voltage transmitted from the data line via the first transistor is held, and information can be output based on the information voltage. When a semiconductor memory device is configured to include a second transistor to perform a precharge circuit capable of precharging the data line to a high level, the second transistor is a p-channel type and the first transistor is a p-channel type. A first electrode coupled to the transistor to form a storage node, a second electrode supplied with a voltage capable of pulling down the data line,
And a third electrode capable of outputting information based on the information voltage.

According to the above means, the precharge circuit comprises:
The data line is precharged to a high level. The second transistor is an n-channel transistor, and is supplied with a first electrode for forming a storage node by being coupled to the first transistor, and a voltage capable of pulling up the data line. Since it includes two electrodes and a third electrode capable of outputting information based on the information voltage, for example, the data line is set to the logical value “1” and the information voltage written to the memory cell is changed to the logical value “1”. , And the information voltage written to the memory cell with the data line set to the logical value “0” can be read out to the data line as the logical value “0”. As described above, since the logical value matches the logical value in the case of writing to the storage node, rewriting to the memory cell can be performed as it is, and DRAM compatibility is satisfied.

In order to reduce the memory cell size, the first transistor is preferably a PLED transistor including an intrinsic semiconductor region stacked on the second transistor.

[0018]

FIG. 2 shows an overall configuration example of a RAM which is an example of a semiconductor memory device according to the present invention.

Although not particularly limited, the RAM 200 shown in FIG. 2 is a memory LSI formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

Reference numeral 12 denotes a memory cell array formed by arranging a plurality of memory cells in a matrix, and is provided with a plurality of word lines and a plurality of data lines. Each data line is commonly connected to a complementary common data line via a Y selection switch circuit 14 including a plurality of column selection switches coupled one-to-one to the data lines. Although not particularly limited, an address multiplex system is adopted, and row and column address input signals are taken in from a common address terminal by shifting their timing. That is, a multiplexer 21 is arranged at a stage preceding the X address latch and the X decoder 11 and the Y address latch and the Y decoder 20, and the address signal Adr fetched from the outside is supplied to the X address latch and the X decoder 11 by the multiplexer 21. , Y address latch and Y decoder 20. To facilitate such address input, two types of clock signals, a row address strobe signal RAS * (* means low active or signal inversion) and a column address strobe signal CAS *, are externally applied. Since only one operation of reading or writing can be performed during one memory cycle (one cycle of RAS * clock), R
When the AS * clock falls, the row address is
* At the falling edge of the clock, the column address is taken into the internal circuit, and the write enable signal WE *
Can determine whether the cycle is a write cycle or a read cycle. Such determination and operation control of each unit are performed by the control unit 19.

The word driver 22 drives a word line to a selected level based on the X address latch and the decode output of the X decoder 11 disposed at the preceding stage. A column direct peripheral circuit 13 is coupled to the memory cell array 12. As will be described later, this column system direct peripheral circuit 13
Includes a Y selection switch circuit, a sense amplifier, a precharge circuit, an equalize circuit, and the like. The memory cell information is amplified by the above-described sense amplifier, and the Y selection switch circuit is driven based on the Y address latch and the decode output of the Y decoder 20, thereby enabling data to be read from or written to the memory cell. It is said. An input / output buffer 16 is arranged downstream of the column-system direct peripheral circuit 13, and data is exchanged with the outside via the input / output buffer 16.

Next, a detailed configuration of each section will be described.

As shown in FIG. 3, the memory cell array 12 includes a plurality of memory cells MC1, MC2 arranged. The plurality of memory cells MC1 and MC2 have the same configuration. The memory cell MC1 has a PLED transistor 101, n as shown in an enlarged view in FIG.
A gain cell is formed by combining the channel type MOS transistor 102 and the capacitor C. This PLE
The D transistor 101 is an n-channel type and has a drain electrode D, a gate electrode G, and a source electrode S.
In PLED transistor 101, the drain electrode is coupled to data line DL, and the gate electrode is coupled to word line WL. The source electrode is connected to the word line WL and the n-channel MOS transistor 102 via the coupling capacitor 103.
To the gate electrode. The n-channel MOS transistor Q102 holds the information voltage transmitted from the data line DL via the PLED transistor 101, and enables information output based on the information voltage. The storage node N is formed by coupling the gate electrode of the n-channel MOS transistor 102 to the PLED transistor 101. One electrode (drain) of the n-channel MOS transistor 102 is coupled to the high potential side power supply VCC, and the other electrode (source) is coupled to the data line DL. It is supplied to the line DL. That is, n
The channel type MOS transistor 102 is a source follower, which is one of the features of the RAM 200. The coupling capacitor 103 is connected to the storage node N
Is provided to control the voltage of The PLED transistor has a vertical structure.
1 is formed so as to be stacked on the n-channel MOS transistor 102, thereby reducing the chip occupation area.

The word driver 22 is provided with a plurality of drive circuits corresponding to the plurality of word lines WL in the memory cell array 12 on a one-to-one basis. The plurality of driving circuits have the same configuration, and can selectively drive the word line WL to a ternary level. Here, the ternary level is not particularly limited, but the VBB (−3) at the time of standby is used.
V), VDL2 (= 0.5 V) at the time of reading, and VPP (= 3.0 V) at the time of writing. The driving circuit WD, which is one of the plurality of driving circuits, is a p-channel type MO.
S transistors Q20 to Q23 and n-channel MOS transistors Q24 to Q27 are combined. An inverter is formed by connecting the p-channel type MOS transistor Q23 and the n-channel type MOS transistor Q27 in series, and the read / write signal R / W is logically inverted by the inverter. Further, a p-channel type MOS transistor Q20 and an n-channel type
An S transistor Q24 is connected in series, a p-channel MOS transistor Q21 and an n-channel MOS transistor Q25 are connected in series, and a p-channel MOS transistor Q22 and an n-channel MOS transistor Q
26 are connected in series. The address signal AD is transmitted to the source electrode of the p-channel MOS transistor Q20 and the gate electrode of the p-channel MOS transistor Q21.

When the read / write signal R / W is at the high level, the n-channel MOS transistor is turned on, so that the read voltage VDL2 is selectively changed to the p-channel M transistor.
The source electrodes of the OS transistors Q21 and Q are transmitted.
At this time, when the address decode signal AD is set to the high level, the word line WL is set to the voltage VDL2 level. When the read / write signal R / W is at a high level, the p-channel MOS transistor Q23 is turned on, thereby turning on the p-channel MOS transistors Q21 and Q21.
The high voltage VPP for writing is supplied to the source electrodes 22. At this time, when the address decode signal AD is set to the low level, the word line WL is set to the high voltage Vpp level. When the address data signal AD is at a low level, the word line is set to an unselected VBB level.

The column system direct peripheral circuit 13 is configured as follows.

Although not particularly limited, the column-related direct peripheral circuit 13 is based on a precharge circuit 15 for precharging the data lines DL and DLB to a low level based on a precharge control signal PRE, and a column selection signal YS. A Y selection switch circuit for selectively coupling the data lines DL and DLB to the common line LIO;
Equalizing circuit 13 for equalizing L and DLB
3. Includes a sense amplifier 132 for amplifying signals on data lines DL and DLB. The source electrodes of the n-channel MOS transistors Q11 and Q12 are connected to the low-potential-side power supply VS.
Combined with S.

The precharge control signal PRE is supplied to the p-channel type MOS transistor Q13 and the n-channel type
A series circuit with the S transistor Q14 and a p-channel type M
It is supplied through a series circuit of an OS transistor Q17 and an n-channel MOS transistor Q18. The column selection signal YS is generated by decoding the Y address signal in the Y address latch and Y decoder 20.

The precharge circuit 15 is an n-channel type M
It comprises OS transistors Q11 and Q12. The Y selection switch circuit 14 includes n-channel MOS transistors Q1 and Q2. The equalizing circuit 133 includes n-channel MOS transistors Q7 to Q9 whose operation is controlled by an equalizing signal BLEQ. When the equalizing signal BLEQ is at a high level, the data lines DL and DLB are equalized by turning on the n-channel MOS transistors Q7 to Q9.
Equalize signal BLEQ is supplied to p-channel MOS transistor Q15 and n-channel MOS transistor Q16.
Is supplied through a series circuit. Sense amplifier 132
Is formed by combining p-channel MOS transistors Q3 and Q4 and n-channel MOS transistors Q5 and Q6. The p-channel MOS transistors Q3 and Q4 are connected in series, and a voltage VDL is supplied to the series connection node via the p-channel MOS transistor Q28 when the sense amplifier control signal SAP is asserted to a low level. You. Although the voltage VDL is not particularly limited, the high voltage VPP (3 V) and the high voltage VPP (= 3 V)
And a low-potential-side power supply VSS (= 0 V). n-channel type MOS
The transistors Q5 and Q6 are connected in series, and the series connection node is set to the low-potential-side power supply VSS level when the sense amplifier control signal SAN is asserted to the high level.

Next, the operation of the RAM 200 will be described.

A ternary level word voltage pulse is applied to the word line WL. That is, when not selected, the negative voltage VB
B, VRL2 is applied at the time of reading, and VW is applied at the time of writing or rewriting. The read operation is performed while the PLED transistor 101 for writing is kept off. Therefore, the read voltage VDL2 is selected to be smaller than the threshold voltage VTW of the PELD transistor 101. The write voltage VPP is selected to be equal to or higher than VCC + VTW. This is for writing the write voltage (VCC, 0 V) corresponding to the binary information (1, 0) to the storage node N without being affected by VTW.

When the write operation is completed and the voltage of the word WL is changed from VW to VBB to shift to the non-selection state, the coupling capacitance C changes the voltage (VCC or 0 V) written to the storage node N to a negative value. Serves to shift to the side. Here, the unselected word voltage is VBB (negative value)
The reason is that the voltage amplitude of the word voltage is increased to shift the voltage of the node N to the negative side more. The voltage of the storage node N shifted to the negative side becomes M
If the threshold voltage VTR of the OS transistor 102 is set smaller than the threshold voltage VTR, the MOS transistor 102 in the non-selected cell becomes non-conductive. Of course, since the gate voltage of the PLED transistor 101 is set to VBB, the PLED transistor 101 is also turned off. Therefore, even if another memory cell connected to the same data line DL is selected and the data line is at any voltage between VCC and 0 V, the MO in a plurality of unselected cells is
Since the S-transistor 102 is turned off, the unselected cell does not adversely affect the operation of the selected cell.

FIG. 4 shows the operation timing when reading the logical value "1" from the memory cell MC1.

The data DL and DLB are equalized while the equalization control signal BLEQ is at a high level. Then, the data line is precharged by the precharge signal PRE being pulsed to a high level. This precharge level corresponds to the data line D at the time of completion of equalization.
When the levels of L and DLB are set to the logic threshold, the level is set to the low level.

Reading when the logical value "1" is being written to the memory cell MC1 is performed as follows.

The word line WL has a voltage VD for reading.
When L2 is set to L2, the voltage of storage node N is set to MO
If the threshold voltage VTR of S transistor 102 is set higher, MOS transistor 102 is turned on. At this time, since one electrode of the MOS transistor 102 is coupled to the high potential side power supply VCC,
The potential of the data line DL is slightly increased from the precharge level (low level) by pull-up. At this time, the sense amplifier control signals SAP, SAN
Is asserted and the operation of the sense amplifier 132 is started, whereby the minute potential difference between the data lines DL and DLB is amplified. Then, the high-level potential of the data line DL is transmitted to the common line LIO via the Y selection switch circuit 14 for reading data.

Next, the word line WL is connected to the high voltage VPP (3
V), the PLED transistor 10
1 is turned on, and the high level of the data line DL is transmitted to the storage node N via the PLED transistor 101, whereby rewriting is performed.

FIG. 5 shows the operation timing at the time of reading the logical value "0" from the memory cell MC1.

Reading when the logical value "0" is being written to the memory cell MC1 is performed as follows.

The word line WL has a voltage VD for reading.
When L2 is set to L2, the voltage of storage node N is set to MO
If the threshold voltage VTR of S transistor 102 is set lower than VTR, MOS transistor 102 is turned off. At this time, the potential of the data line DL is at the precharge level (low level). However, the sense amplifier control signals SAP and SAN are asserted and the operation of the sense amplifier 132 is started. The data line DL is set to the low-potential-side power supply VSS level by amplifying the minute potential difference of the DLB.
At this time, the low-level potential of the data line DL is transmitted to the common line LIO via the Y selection switch circuit 14 for reading data, and the potential of the word line WL is set to the VPP level to turn on the PLED transistor 101. When this is done, the data is transmitted to the storage node N via the PLED transistor 101 for this rewriting, so that the rewriting is performed.

According to the above example, the following functions and effects can be obtained.

(1) By using the n-channel MOS transistor 102 as a source follower,
Since the write logical value of the memory cell MC1 matches the read logical value of the memory cell MC1, the potential of the data line DL is used as it is to transfer the data to the memory cell MC1 in the same manner as in a normal DRAM. Writing can be performed.

(2) N-channel MOS transistor 1
The PLED transistor 101 is formed vertically by stacking the intrinsic semiconductor region at the position of the gate electrode 02, so that the chip occupation area of the memory cell MC1 can be reduced.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, the memory cell MC1 shown in FIG.
Has been described in which two transistors and a coupling capacitor C are used, and a data line for reading and a data line for writing are shared, which has been described with reference to FIGS. Various modifications are conceivable as shown in C).

FIGS. 6A to 6C show memory cells MC.
Another alternative configuration example is shown.

Memory cell MC1 shown in FIG.
Is different from that shown in FIG.
The difference is that a p-channel MOS transistor 602 is provided as a source follower instead of the S transistor 102. When the p-channel MOS transistor 602 is used for reading as described above, one electrode (drain) of the p-channel MOS transistor is
The other electrode (source) is coupled to the low potential side power supply VSS
Are coupled to data line DL. When the p-channel MOS transistor 602 is used, although not shown, the data lines DL and DL * are precharged to a high level by a precharge circuit.

In the above configuration, when the logical value "1" is written to the storage node N, the p-channel MOS transistor 602 is turned off when the word line WL is set to the selected level. Therefore, the data line DL
Remains at the precharge level (high level),
After being amplified by the sense amplifier, it is transmitted to the common line for reading and transmitted to the storage node N via the PLED transistor 101 for rewriting. When the logical value “0” is written to the storage node N, when the word line WL is set to the selected level, the p-channel MOS transistor 60
2 is turned on, the data line DL is pulled down to a high level, which is a precharge level, which is amplified by a sense amplifier, transmitted to the common line for reading, and re-input. Storage node N via PLED transistor 101 for writing
Is transmitted to As described above, when the p-channel type is applied as the read MOS transistor 602,
The electrode for power supply is connected to the lower potential power supply VSS,
By precharging the data lines DL and DLB to a high level, the write logical value of the memory cell MC1 matches the logical value read from the memory cell MC1, as in the case of the circuit configuration shown in FIG. Therefore, as in the case of a normal DRAM, rewriting to the memory cell MC1 can be performed using the potential of the data line DL as it is.

Memory cell MC1 shown in FIG.
1 is different from that shown in FIG. 1 in that a PLED transistor 601 is a p-channel type and an n-channel type MOS
The voltage VDL is supplied to a source electrode of the transistor 102. The data lines DL and DLB are precharged to a low level.

In the above configuration, when the logical value "1" is written to the storage node N, the n-channel MOS transistor 102 is turned on when the word line WL is set to the selected level. The data line DL is raised from a precharge level (low level) by pull-up, amplified by a sense amplifier, transmitted to a common line for reading, and connected to a PLED transistor 601 for rewriting. Is transmitted to storage node N through The logical value “0” is stored in the storage node N.
Is written, when the word line WL is set to the selection level, the n-channel MOS transistor 102 is off, the data line DL is kept at the low level which is the precharge level, After it is amplified by the sense amplifier, it is transmitted to the common line for reading and PLED for rewriting.
The signal is transmitted to storage node N via transistor 601. Thus, the read MOS transistor 10
In the case where an n-channel type is applied as No. 2, the electrode for power supply is coupled to the low potential side power supply VDL and the data line D
By precharging L and DLB to low level, the write logical value of the memory cell MC1 and the read logical value from the memory cell MC1 match as in the case of the circuit configuration shown in FIG. Normal DRAM
As in the case of (1), rewriting to the memory cell MC1 can be performed using the potential of the data line DL as it is.

Memory cell MC1 shown in FIG.
1 is different from that shown in FIG. 1 in that the PLED transistor 611 is a p-channel
The point is that the transistor 602 is a p-channel type, and an electrode for power supply of the n-channel type MOS transistor 602 is coupled to the lower potential power supply VSS. In this case, the data lines DL and DLB are precharged to a high level.

When the logical value "1" is written to the storage node N, the p-channel MOS transistor 602 is turned off when the word line WL is set to the selected level, so that the data line DL Remains at a precharge level (high level), which is amplified by a sense amplifier, transmitted to a common line for reading, and a PLED transistor 1 for rewriting.
01 to the storage node N. Further, when the logical value “0” is written to the storage node N, the p-channel MOS transistor 602 is turned on when the word line WL is set to the selection level. , It is lowered from the precharge level by pull-down, it is amplified by the sense amplifier, and then transmitted to the common line for reading,
It is transmitted to the storage node N via the PLED transistor 601 for rewriting. As described above, when the p-channel type is applied as the read MOS transistor 602, the electrode for power supply is connected to the low potential side power supply V.
SS, and the data lines DL and DLB are precharged to a high level, so that the write logic value of the memory cell MC1 and the read logic from the memory cell MC1 are similar to the case of the circuit configuration shown in FIG. Since the values match, the rewriting to the memory cell MC1 can be performed using the potential of the data line DL as it is, as in the case of a normal DRAM.

FIG. 7 shows another configuration example of the memory cell array 12 in the RAM 200.

The memory cell array 12 shown in FIG.
3 differs from that shown in FIG. 3 in that the drain electrode of the n-channel MOS transistor 102 serving as a source follower is coupled to the word line WL, and that the other electrode of the n-channel MOS transistor 102 is The point is that it is coupled to the data line DL via a diode 701 arranged for each memory cell. Also, the word line WL
Of the n-channel MOS transistors Q24, Q25, and Q26 in the word driver 22 are coupled to the low-potential-side power supply Vss. And n-channel type M
The voltage VDL is supplied to the source electrode of the OS transistor Q27.

FIG. 8 shows the operation timing when the logical value "1" is stored in the storage node N and is read out, and FIG. 9 stores the logical value "0" in the storage node N. The operation timing when the data is read out is shown.

When the logical value "1" is stored in the storage node N and the word line WL is set to the read selection level (VDL), the n-channel MOS transistor Q102 is turned on, and the n-channel MOS transistor Q102 is turned on. A current flows from the word line WL to the data line DL via the MOS transistor Q102 and the diode 701, and the potential of the data line DL is increased by pull-up. After being amplified by the sense amplifier 132, it is transmitted to the common line LIO via the Y selection switch 14 for reading. When the word line WL is raised to the write selection level (VPP), the PLED transistor 101 is turned on, and the high level of the data line DL is transmitted to the storage node N via the PLED transistor 101. Performs rewriting.

The diode 701 is provided to prevent backflow. That is, when the diode 701 is omitted, the logical value “1” is stored in the storage node of the memory cell coupled to the unselected word line when the above-described rewrite operation is performed. When the data line DL is at the high level, the n-channel MOS transistor 102 in the memory cell is turned on, and the word line WL at the non-selected level is turned off from the data line DL.
The through current flows toward. The above diode 7
By providing 01, the through current in this case is prevented.

When the logical value "0" is stored in the storage node N, the n-channel MOS transistor Q102 is set even if the word line WL is set to the selected level at the time of reading.
Are kept in the off state, and the data lines DL and DLB remain at the precharge level (low level). After the data lines DL and DLB are amplified by the sense amplifier 132, the common lines are read through the Y selection switch 14 for reading. It is transmitted to the LIO. When the word line WL is raised to the selected level at the time of writing, the PLED transistor 101 is turned on, and the high level of the data line DL is transmitted to the storage node N via the PLED transistor 101 to perform rewriting. Is done.

Therefore, even when the configuration shown in FIG. 7 is employed, as in the case of the circuit configuration shown in FIG. 1, the write logical value of memory cell MC1 and the logical value read from memory cell MC1 are read. Therefore, as in the case of a normal DRAM, rewriting to the memory cell MC1 is performed using the potential of the data line DL as it is.

FIGS. 10A to 10D show memory cells M
Another configuration example of C1 is shown.

Memory cell MC1 shown in FIG.
However, what is different from that shown in FIG. 7 is that the PLED transistor 901 is a p-channel type, the MOS transistor 902 which is a source follower is a p-channel type, and a diode 701 for preventing a through current is provided. , FIG.
Are arranged in the opposite direction to the case shown in FIG. Diode 701 blocks current flowing from word line WL to data line DL when a logical value “0” is stored in storage node N.

Further, a diode 701 for preventing a shoot-through current
Is, as shown in FIG. 10B, the word lines WL and n
It may be provided between the channel type MOS transistor 102. Also in this configuration, when the logical value “1” is stored in the storage node of the memory cell coupled to the unselected word line, when the data line DL is at the high level, the n-channel type The MOS transistor 102 is turned on and the data line DL
Therefore, it is possible to prevent a through current from flowing toward the non-selected level word line WL.

FIG. 11 is a plan view of the memory cell array 12 when the configuration shown in FIG. 10B is employed. FIG. 12 also shows a line segment A in FIG.
A sectional view of -B is shown.

Four word lines WL and two data lines D
L are arranged so as to intersect, and a memory cell is formed at the intersection. One memory cell MC1 is configured as follows.

A semiconductor region (n ⁺ ) is formed on a semiconductor substrate (Psub).
Is formed, an n-channel MOS transistor 102 is formed, and a PLED transistor 101 and a diode 701 are formed on the n-channel MOS transistor 102. That is, an n-channel MOS
By stacking the intrinsic semiconductor region (i-Poly) at the position of the gate electrode of the transistor 102, the PLED transistor 101 is formed in a vertical type. A data line DL (DG) is provided on the intrinsic semiconductor region (i-Poly), and a word line WL is formed thereon. Word line W
L is formed so as to cross the data line DL (SG) while crossing it. With such a configuration, the word line W
L (TG) also functions as a gate electrode in the PLED transistor 101. The diode 701 is formed by stacking a semiconductor region p ^{− on} one semiconductor region n ⁺ in the n-channel MOS transistor 102. This diode 701 is coupled to data line DL (SG) by contact TCNT.

The PLE shown in FIG. 1 and other drawings
The D transistor can basically adopt the configuration shown in FIG.

As shown in FIGS. 10C and 10D, read MOS transistors 102 and 103
Are transistors having an asymmetric structure, the diode 701 can be omitted. That is, in FIG. 10C, when the source-side threshold value and the drain-side threshold value of the n-channel MOS transistor 102 are represented by Vths and Vthd, respectively, Vths
When the relationship of> Vthd is established, the current flowing from the data line DL to the word line WL can be blocked as in the case where the diode 701 is provided as shown in FIG. In FIG. 10D, when the source-side threshold value and the drain-side threshold value of the p-channel MOS transistor 902 are represented by Vths and Vthd, respectively, if the relationship of Vths <Vthd holds, As shown in (A), the current flowing from the word line WL to the data line DL can be blocked in the same manner as the case where the diode 701 is provided.

FIGS. 13A to 13C show memory cells M
Another configuration example of C1 is shown.

In memory cell MC1 shown in FIGS. 13A to 13C, a word line WLW for writing and a word line WLR for reading are separately provided, and a MOS transistor for forming a storage node is provided. 102,902
And read MOS transistors 905 and 906 are separately provided.

That is, in the memory cell MC1 shown in FIG. 13A, the gate electrode of the p-channel PLED transistor 901 is coupled to the write word line WLW, and the PLED transistor 901 and the n-channel M
A storage node N is formed at a position where the storage node N is connected to the OS transistor 102. This n-channel MOS transistor 10
The voltage VDL is supplied to one of the two electrodes (drain). An n-channel MOS transistor 905 is connected in series to the n-channel MOS transistor 102. The other electrode (source) of n-channel MOS transistor 905 is coupled to data line DL. Also,
The gate electrode of the n-channel MOS transistor 905 is coupled to a read word line WLR. When the MOS transistors 102 and 905 are connected in series as described above, the MOS transistors 102 and 905 serve as a source follower. The precharge level of the data lines DL and DLB is at a low level.

When the write word line WLW is set to the selected level and the PLED transistor 901 is turned on, information can be written to the storage node N based on the potential of the data line DL at that time. When the write word line WLR is set to the selected level, n
The channel MOS transistor 905 is turned on, and information can be read from the storage node N. For example, when a logical value “1” is written to the storage node N, the n-channel MOS transistor 102 is turned on, and the data line DL is pulled up when the n-channel MOS transistor 905 is turned on. As a result, the potential of the data line DL is increased, so that data reading of the logical value “1” is performed. When the logical value “0” is written to the storage node N, the potential of the data line DL does not rise because the n-channel MOS transistor 102 is not turned on, so that the logical value “0” is read. Since the write logical value of the memory cell MC1 matches the logical value read from the memory cell MC1, the potential of the data line DL is used as it is in the same manner as in a normal DRAM.
Can be rewritten.

Memory cell MC1 shown in FIG.
However, what is different from that shown in FIG. 11A is that the MOS transistors 902 and 906 serving as the source followers are p-type transistors.
It is a channel type. In this case, one electrode (power supply terminal) of the p-channel MOS transistor 902 is supplied with the low-potential-side power supply voltage VSS.
The precharge level of the data line DL is set to a high level.

In this configuration, if a logical value "1" is written to the storage node, the p-channel type MO
Since the S transistor 902 is turned off, the precharge level (high level) of the data line DL is amplified by the sense amplifier, so that read data of the logical value “1” is obtained. When the logical value “0” is written in the storage node, the precharge level (high level) of the data line DL is lowered by pull-down because the p-channel MOS transistor 902 is turned on. Are amplified by the sense amplifier to obtain read data of a logical value “0”. As described above, the write logic value of the memory cell MC1 and the memory cell MC1
Since the logical value read from
As in the case of M, rewriting to the memory cell MC1 can be performed using the potential of the data line DL as it is.

Memory cell MC1 shown in FIG.
However, what is different from that shown in FIG.
Transistor 101 is an n-channel transistor;
The selection level of the word line WLW for writing is shown in FIG.
The only difference is the case. Also in this configuration, the write logic value of the memory cell MC1 and the memory cell M1
Since the logical value read from C1 matches, the normal D
As in the case of the RAM, rewriting to the memory cell MC1 can be performed using the potential of the data line DL as it is, and DRAM compatibility is satisfied.

In the above configuration, the PLED transistor can be a normal MOS transistor.

In the above description, the case where the invention made by the present inventor is mainly applied to a RAM as a memory LSI, which is a field of application, has been described. However, the present invention is not limited to this. The present invention can be widely applied to various semiconductor integrated circuits such as a microcomputer formed on one semiconductor chip.

The present invention can be applied on condition that at least a data line and a word line are included.

[0078]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the second transistor is a source follower, for example, the data line has the logical value “1”.
And the information voltage written to the memory cell can be read out to the data line as the logical value "1". The data line is set to the logical value "0" and the information voltage written to the memory cell is changed to the logical value "0". "Can be read out to the data line. Since the logic read to the data line in this way matches the logic value in the case of writing to the storage node,
Rewriting to the memory cell becomes possible as it is, and DR
AM compatibility is satisfied.

When the data line is precharged to a low level by the precharge circuit,
The second transistor is an n-channel type, and the first transistor
A first electrode coupled to the transistor to form a storage node; a second electrode supplied with a voltage capable of pulling up the data line; and a third electrode capable of outputting information based on the information voltage. Since the data line has the logic value "1", for example, the information voltage written in the memory cell can be read as the logic value "1" on the data line, and the data line can be read as the logic value "0". Thus, the information voltage written in the memory cell can be read out to the data line as a logical value “0”. Since the logic read to the data line matches the logic value in the case of writing to the storage node, rewriting to the memory cell can be performed as it is, and DRAM compatibility is satisfied.

When the data line is precharged to a high level by the precharge circuit, the second transistor is of a p-channel type, and
A first electrode coupled to the first transistor to form a storage node, a second electrode supplied with a voltage capable of pulling down the data line, and a second electrode capable of outputting information based on the information voltage. Since the data line includes three electrodes, for example, the data line is set to the logical value “1”, and the information voltage written to the memory cell can be read to the data line as the logical value “1”. And the information voltage written to the memory cell as "0" can be read out to the data line. Since the logic read to the data line matches the logic value in the case of writing to the storage node, rewriting to the memory cell can be performed as it is, and DRAM compatibility is satisfied.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a memory cell in a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram illustrating an overall configuration example of the semiconductor memory device.

3 is a detailed configuration example circuit diagram of a memory cell array section including the memory cell shown in FIG. 1 and its periphery.

FIG. 4 is an operation timing chart of a main part in the configuration shown in FIG. 3;

FIG. 5 is an operation timing chart of a main part in the configuration shown in FIG. 3;

FIG. 6 is a circuit diagram illustrating another configuration example of the memory cell;

FIG. 7 is a circuit diagram showing another configuration example of the memory cell and its peripheral part.

8 is an operation timing chart of a main part in the configuration shown in FIG. 7;

9 is an operation timing chart of a main part in the configuration shown in FIG. 7;

FIG. 10 is a circuit diagram illustrating another configuration example of the memory cell.

11 is a plan view of a memory cell array including the memory cells shown in FIG.

FIG. 12 is a sectional view taken along line AB in FIG. 11;

FIG. 13 is a circuit diagram illustrating another configuration example of the memory cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 X address latch and X decoder 12 Memory cell array 13 Column direct peripheral circuit 14 Y selection switch circuit 15 Precharge circuit 16 I / O buffer 19 Control unit 20 Y address latch and Y address decoder 21 Multiplexer 22 Word driver 132 Sense amplifier 133 Equalize Circuit 101, 601, 901 PLED transistor 200 RAM

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masaya Murana 5-22-1, Josuihoncho, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Co., Ltd. 5F083 AD01 AD69 5M024 AA91 BB02 BB39 CC02 CC25 CC27 CC35 CC64 EE05 HH20 KK20 LL11 PP01 PP03 PP05 PP07

Claims (4)

[Claims] 1. A semiconductor memory device including a plurality of memory cells coupled to a word line and a data line, wherein the memory cell includes a first transistor that is turned on according to a voltage level of the word line; A second transistor for holding an information voltage transmitted from the data line via the first transistor and enabling information output based on the information voltage, wherein the second transistor is a source follower. A semiconductor memory device characterized by the above-mentioned. 2. A semiconductor memory device including a plurality of memory cells coupled to a word line and a data line, wherein the first transistor is turned on according to a voltage level of the word line; A second transistor that holds an information voltage transmitted from the data line via the data line and enables information output based on the information voltage, and a precharge circuit that can precharge the data line to a low level; The second transistor is an n-channel type, and
A first electrode coupled to the first transistor to form a storage node; and a second electrode supplied with a voltage capable of pulling up the data line.
A semiconductor memory device comprising: an electrode; and a third electrode capable of outputting information based on the information voltage. 3. A semiconductor memory device including a plurality of memory cells coupled to a word line and a data line, wherein the first transistor is turned on in accordance with a voltage level of the word line; A second transistor that holds an information voltage transmitted from the data line via the data line and enables information output based on the information voltage, and a precharge circuit that can precharge the data line to a high level; The second transistor is a p-channel type, and
A first electrode coupled to the first transistor to form a storage node; and a second electrode supplied with a voltage capable of pulling down the data line.
A semiconductor memory device comprising: an electrode; and a third electrode capable of outputting information based on the information voltage. 4. The P-type semiconductor device according to claim 1, wherein the first transistor includes an intrinsic semiconductor region stacked on the second transistor.
4. An LED transistor according to claim 1, wherein the LED transistor is an LED transistor.
13. The semiconductor memory device according to claim 1.