JP2001256270A - Verification result comparison method - Google Patents

Abstract

(57) [Summary] A batch conveyor system in which a compare mismatch of a RAM (cache / TLB) occurs only when a true mismatch occurs (when a defect of a logic to be verified is detected) is used in all verification programs. Provides a highly accurate verification method. Kind Code: A1 A RAM which is not executed by a single instruction sequential execution type instruction simulator but is generated by a contention of the same column such as pre-control, instruction prefetch, and cache executed by a logic simulator which executes a logic verification program. Regarding the mismatch at the time of comparing the (cache / TLB) hierarchical memories, the state of the result value of the logic simulator in the column where the mismatch occurs is checked,
By verifying the validity of the hierarchical memory of the RAM by having a function of comparing the data of the column with the data of the MS which is the lowermost data of the instruction simulator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique related to a logic simulation verification method for comparing a result of executing a logic verification program with a logic simulator and a result of execution with an instruction simulator to verify a logic simulator.

[0002]

2. Description of the Related Art As a technique for supporting high-performance instruction processing, instruction execution is divided into a plurality of processing steps (stages), and each device (control unit) executes a specific stage every one machine cycle. A pipeline processing method for processing is adopted. This pipeline processing, also called the advanced control function, is realized by complex and large-scale logic.
Its depth is also very deep. Therefore, at the time of instruction fetch and data access, prefetching of the RAM (cache, TLB) to be accessed works by the preceding control, and RA
The content of M is updated frequently. The conventional result confirmation method is
Since the update time / unit of the RAM is different for each model, a verification program having a result comparison function unique to each model is executed by the logic to be verified, and the execution result is confirmed by the result comparison function of the verification program itself. Also, in the batch compare method of the execution result of the instruction simulator and the execution result of the logic to be verified, the mismatch occurred because the instruction simulator performed sequential processing for each instruction. This was realized by analyzing whether or not there was a human intervention. As a related art of this kind, for example, a technique described in Japanese Patent Application Laid-Open No. 8-263544 is known.

[0003]

In the prior art, when a result comparison routine compares the execution result (expected value) of the instruction simulator and the execution result of the logic to be verified at once, and the contents of the RAM do not match. In this case, the cause of the mismatch is manually investigated based on information such as an error message. However, it is necessary to examine the instruction trace, the logic execution trace, and the like to determine whether the inconsistency is caused by the prefetch of the RAM by the preceding control of the logic to be verified or the logic to be verified is defective. . Such inconsistency frequently occurs even in a verification program (single instruction test or the like) that does not target the preceding control as a verification target, and it is a situation in which batch comparison of the RAM must be suppressed. Therefore, only the inconsistency that occurred in the verification program for verifying the update control of the RAM was investigated by manual intervention. Since this survey involves manual intervention, the contents of verification (test instruction sequence, target RA
M state, etc.) and the logic to be verified must be grasped, and analysis is difficult. Further, only a part of these verification programs cannot guarantee whether or not the update control of the RAM is appropriate, which is one of the factors that makes it difficult to extract a logic defect.

[0004] An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a high-precision verification method by using a batch conveyor system in which the occurrence of an AM compare mismatch only when a true mismatch occurs (when a defect to be verified is detected) in all the verification programs.

[0005]

In order to achieve the above object, according to the present invention, a logic simulator for executing a logic verification program and an instruction simulator are provided with a function of outputting the result values, thereby collectively collecting the result values. Implement a logic simulation verification method for comparison. RA which is not executed in the instruction simulator, but is generated in the logic simulator due to preceding control executed, instruction prefetch, contention of the same column such as cache, etc.
Regarding the mismatch at the time of comparing the M (cache / TLB) hierarchical memories, the validity of the state of the result value of the logic simulator of the column where the mismatch occurs is checked by checking the holding status of the data of the column in the instruction simulator. The validity of the hierarchical memory of the RAM is verified by comparing the RAMs with each other and comparing the data of the column with the data of the MS which is the lowermost data of the instruction simulator when the RAM is not held. In addition, for the inconsistency that occurs at the time of comparing the MS as the lowermost layer data, the data value on the memory map in the logic simulation is checked for the result value of the address, and the data of the address is compared with the upper layer of the instruction simulator. The state of registration in the memory is checked, and the validity of the data of the MS as the lowermost layer data is verified by comparing with the corresponding memory (RAM, MS).

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a process of updating the contents of a RAM and confirming its validity according to an embodiment of the present invention. A logic simulator (processor operation simulator under development in which a wiring level intermediate language is described) 101
The verification program 100 is executed, and the execution result is collected in the RAM data storage area 103 and the MS data storage area 105. The instruction simulator 102 executes the verification program 100
Is executed, and the execution result is stored in the RAM data storage area 104, M
Collected in the S data storage area 106. At this time, when executing the Branch instruction as shown in FIG. 3, the logic simulator 101 has already performed a process of prefetching a subsequent instruction that is not executed following the Branch instruction into the instruction cache (FIG. 1). Dotted line part). FIG. 3 is a diagram showing an example of the structure of a verification program executed in the embodiment of the present invention. However, the instruction simulator 102
Since instructions are read and executed one by one, prefetching of instructions to the instruction cache is not performed. Therefore, a simple comparison of the results extracted from 103 and 104 in the simple comparison process 107 of the same RAM is incorrect in the above case. Therefore, if the results do not match, the state of the data extracted from 103 is checked.
If the data is valid, the same address data comparison with 106 is performed in the same address comparison processing 108 of the RAM-MS to determine the result of OK / NG.

FIG. 2 is a block diagram showing a process for updating the contents of the MS and confirming its validity. Logic simulation
The data 201 executes the verification program 200 and stores the execution result in the RAM data storage area 203 and the MS data storage area 2.
Collect at 05. The instruction simulator 202 executes the verification program 200 and collects the execution result in the RAM data storage area 204 and the MS data storage area 206. At this time, in the logic simulator 201, as shown in FIG.
When the nch instruction is executed, the cache is replaced by a process of prefetching a subsequent instruction that is not executed following the Branch instruction into the instruction cache (a dotted line portion in FIG. 2). However, instruction simulator 2
In No. 02, the instruction is read out and executed one by one, so that the instruction cache is not prefetched. Therefore, a simple comparison of the results retrieved from 205 and 206 in the simple comparison process 207 of the MS is incorrect in the above case. Therefore, if the results do not match, the state of the data extracted from 205 is checked. If the data is invalid, it is set to WORNING. If the data is valid, MS-
In the same address comparison process 208 of the RAM, the same address data is compared with the data 204 and the result of OK / NG is determined.

FIG. 4 is a diagram showing a validity check process in the RAM result comparison processing units 107 and 108. Hereinafter, each step of FIG. 4 will be described. The state of the corresponding column of the result value 103 created by the logical simulator 101 is checked (301), and if it is valid, the coincidence / mismatch of the registered address and information of the expected value 104 created by the instruction simulator 102 in the column is checked. Inspection (302).
At 302, if the registered address and information of the column match, the data of the column is compared, and if they match, OK is determined if they do not match (ERROR).
4). If the registered address and information of the column do not match at 302, the expected value 10 of the MS created by the instruction simulator 102 whose address matches the data of the column of the result value 103 created by the logic simulator 101
6 are compared, if they match, OK; if they do not match, E
RROR (305).

If the state of the column is invalid at 301, the expected value 104 created by the instruction simulator 102 is generated.
A check is made as to whether the registered address and the information of the corresponding column match or not (303). At 303, if the registered address and information of the column match, the data of the column is compared, and if they match, OK;
ARNING is set (306). If the registered address and the information of the column do not match at 303, WARNI
NG.

FIG. 5 shows the MS result comparison processing units 207 and 2
It is a figure which shows the process of the validity check in 08. Less than,
Each step in FIG. 5 will be described. The registration status of the address of the result value 205 created by the logical simulator 201 is checked (401). At 401, if the latest data at the address is registered in the RAM, the data is compared with the data of the expected value 206 created by the instruction simulator 202. If they match, the result is OK.
(403). If the latest data of the address is not registered in the RAM at 401, the registration status of the address to the expected value 204 is checked (402).

If the address is registered in the RAM at 402, the data of the address of the result value 205 created by the logic simulator 201 and the expected value 204 of the RAM created by the instruction simulator 202 are compared. If they match, it is OK, and if they do not match, it is ERROR (404). If the address is not registered in the RAM at 402, the data is compared with the data of the expected value 206 created by the instruction simulator 202. If they match, the result is OK, and if they do not match, the result is WARNING (405).

[0013]

According to the above-mentioned means, it is possible to automatically check the validity of updating the contents of the RAM, which was conventionally confirmed by manual intervention. As a result, it is possible to check the test results in a shorter time than before, and it is possible to increase the running amount of the test program, thereby improving the quality of the entire verification.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a process of updating the contents of a RAM and checking its validity.

FIG. 2 is a block diagram showing a process of updating the content of an MS and confirming its validity.

FIG. 3 is a diagram illustrating an example of a verification program structure to be executed.

FIG. 4 is a diagram illustrating a validity check process in a RAM result comparison processing unit.

FIG. 5 is a diagram illustrating a validity check process in an MS result comparison processing unit.

[Explanation of symbols]

100 verification program file, 101 logic simulator, 102 single instruction sequential execution type instruction simulator, 103 RAM data storage area, 104 RAM data storage area, 105 MS data storage area, 106
MS data storage area, 107: simple comparison process of the same RAM, 108: same address comparison process of the RAM-MS, 2
00: verification program file, 201: logic simulator, 202: single instruction sequential execution type instruction simulator,
203: RAM data storage area, 204: RAM data storage area, 205: MS data storage area, 206: MS
Data storage area, 207... MS simple comparison processing, 208
... Same address comparison processing of MS-RAM.

Claims (2)

[Claims] 1. A logic simulator for executing a logic verification program and a single instruction sequential execution type instruction simulator (hereinafter referred to as an instruction simulator) having a function of outputting the result value, thereby comparing the result values collectively. This is a logic simulation verification method which is not executed by the instruction simulator, but is generated by the preceding simulator executed by the logic simulator, the prefetch of instructions, and the occurrence of conflicts in the same column such as a cache.
Regarding the mismatch at the time of comparison between the hierarchical memories of the AM (cache / TLB), the state of the result value of the logic simulator of the column where the mismatch occurs is checked, and the data of the column is the data of the MS which is the lowest layer data of the instruction simulator. A logic simulation verification method characterized by verifying the validity of a hierarchical memory of a RAM by having a function of comparing with a logical simulation. 2. The logic simulation verification method according to claim 1, wherein for a mismatch that occurs when comparing the MS as the lowermost layer data, a state of a result value of a logic simulator of a column where the mismatch occurs is checked, and the column is checked. Of the instruction simulator is checked in the upper-layer memory of the RAM of the instruction simulator, and the corresponding memory (RAM,
A logic simulation verification method characterized by verifying the validity of MS data, which is the lowermost layer data, by having a function of comparing with MS (MS).